Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "disassembler_arm.h" |
| 18 | |
Ian Rogers | ef7d42f | 2014-01-06 12:55:46 -0800 | [diff] [blame] | 19 | #include <inttypes.h> |
| 20 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 21 | #include <iostream> |
| 22 | |
Elliott Hughes | 07ed66b | 2012-12-12 18:34:25 -0800 | [diff] [blame] | 23 | #include "base/logging.h" |
Elliott Hughes | e222ee0 | 2012-12-13 14:41:43 -0800 | [diff] [blame] | 24 | #include "base/stringprintf.h" |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 25 | #include "thread.h" |
Elliott Hughes | 0f3c553 | 2012-03-30 14:51:51 -0700 | [diff] [blame] | 26 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 27 | namespace art { |
| 28 | namespace arm { |
| 29 | |
| 30 | DisassemblerArm::DisassemblerArm() { |
| 31 | } |
| 32 | |
Ian Rogers | b23a772 | 2012-10-09 16:54:26 -0700 | [diff] [blame] | 33 | size_t DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin) { |
| 34 | if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) { |
| 35 | DumpArm(os, begin); |
| 36 | return 4; |
| 37 | } else { |
| 38 | // remove thumb specifier bits |
| 39 | begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1); |
| 40 | return DumpThumb16(os, begin); |
| 41 | } |
| 42 | } |
| 43 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 44 | void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) { |
| 45 | if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) { |
| 46 | for (const uint8_t* cur = begin; cur < end; cur += 4) { |
| 47 | DumpArm(os, cur); |
| 48 | } |
| 49 | } else { |
| 50 | // remove thumb specifier bits |
| 51 | begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1); |
| 52 | end = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(end) & ~1); |
| 53 | for (const uint8_t* cur = begin; cur < end;) { |
| 54 | cur += DumpThumb16(os, cur); |
| 55 | } |
| 56 | } |
| 57 | } |
| 58 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 59 | static const char* kConditionCodeNames[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 60 | "eq", // 0000 - equal |
| 61 | "ne", // 0001 - not-equal |
| 62 | "cs", // 0010 - carry-set, greater than, equal or unordered |
| 63 | "cc", // 0011 - carry-clear, less than |
| 64 | "mi", // 0100 - minus, negative |
| 65 | "pl", // 0101 - plus, positive or zero |
| 66 | "vs", // 0110 - overflow |
| 67 | "vc", // 0111 - no overflow |
| 68 | "hi", // 1000 - unsigned higher |
| 69 | "ls", // 1001 - unsigned lower or same |
| 70 | "ge", // 1010 - signed greater than or equal |
| 71 | "lt", // 1011 - signed less than |
| 72 | "gt", // 1100 - signed greater than |
| 73 | "le", // 1101 - signed less than or equal |
| 74 | "", // 1110 - always |
| 75 | "nv", // 1111 - never (mostly obsolete, but might be a clue that we're mistranslating) |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 76 | }; |
| 77 | |
| 78 | void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) { |
| 79 | if (cond < 15) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 80 | os << kConditionCodeNames[cond]; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 81 | } else { |
| 82 | os << "Unexpected condition: " << cond; |
| 83 | } |
| 84 | } |
| 85 | |
Ian Rogers | b122a4b | 2013-11-19 18:00:50 -0800 | [diff] [blame] | 86 | void DisassemblerArm::DumpMemoryDomain(std::ostream& os, uint32_t domain) { |
| 87 | switch (domain) { |
| 88 | case 0b1111: os << "sy"; break; |
| 89 | case 0b1110: os << "st"; break; |
| 90 | case 0b1011: os << "ish"; break; |
| 91 | case 0b1010: os << "ishst"; break; |
| 92 | case 0b0111: os << "nsh"; break; |
| 93 | case 0b0110: os << "nshst"; break; |
| 94 | case 0b0011: os << "osh"; break; |
| 95 | case 0b0010: os << "oshst"; break; |
| 96 | } |
| 97 | } |
| 98 | |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 99 | void DisassemblerArm::DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32) { |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 100 | os << StringPrintf("%+d (%p)", imm32, instr_ptr + imm32); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | static uint32_t ReadU16(const uint8_t* ptr) { |
| 104 | return ptr[0] | (ptr[1] << 8); |
| 105 | } |
| 106 | |
| 107 | static uint32_t ReadU32(const uint8_t* ptr) { |
| 108 | return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); |
| 109 | } |
| 110 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 111 | static const char* kDataProcessingOperations[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 112 | "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", |
| 113 | "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn", |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 114 | }; |
| 115 | |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 116 | static const char* kThumbDataProcessingOperations[] = { |
| 117 | "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", |
| 118 | "tst", "rsb", "cmp", "cmn", "orr", "mul", "bic", "mvn", |
| 119 | }; |
| 120 | |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 121 | static const char* kThumbReverseOperations[] = { |
| 122 | "rev", "rev16", "rbit", "revsh" |
| 123 | }; |
| 124 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 125 | struct ArmRegister { |
Elliott Hughes | 7484741 | 2012-06-20 18:10:21 -0700 | [diff] [blame] | 126 | explicit ArmRegister(uint32_t r) : r(r) { CHECK_LE(r, 15U); } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 127 | ArmRegister(uint32_t instruction, uint32_t at_bit) : r((instruction >> at_bit) & 0xf) { CHECK_LE(r, 15U); } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 128 | uint32_t r; |
| 129 | }; |
| 130 | std::ostream& operator<<(std::ostream& os, const ArmRegister& r) { |
| 131 | if (r.r == 13) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 132 | os << "sp"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 133 | } else if (r.r == 14) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 134 | os << "lr"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 135 | } else if (r.r == 15) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 136 | os << "pc"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 137 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 138 | os << "r" << r.r; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 139 | } |
| 140 | return os; |
| 141 | } |
| 142 | |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 143 | struct ThumbRegister : ArmRegister { |
| 144 | ThumbRegister(uint16_t instruction, uint16_t at_bit) : ArmRegister((instruction >> at_bit) & 0x7) {} |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 145 | }; |
| 146 | |
| 147 | struct Rm { |
Elliott Hughes | 7484741 | 2012-06-20 18:10:21 -0700 | [diff] [blame] | 148 | explicit Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {} |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 149 | uint32_t shift; |
| 150 | ArmRegister rm; |
| 151 | }; |
| 152 | std::ostream& operator<<(std::ostream& os, const Rm& r) { |
| 153 | os << r.rm; |
| 154 | if (r.shift != 0) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 155 | os << "-shift-" << r.shift; // TODO |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 156 | } |
| 157 | return os; |
| 158 | } |
| 159 | |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 160 | struct ShiftedImmediate { |
Elliott Hughes | 7484741 | 2012-06-20 18:10:21 -0700 | [diff] [blame] | 161 | explicit ShiftedImmediate(uint32_t instruction) { |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 162 | uint32_t rotate = ((instruction >> 8) & 0xf); |
| 163 | uint32_t imm = (instruction & 0xff); |
| 164 | value = (imm >> (2 * rotate)) | (imm << (32 - (2 * rotate))); |
| 165 | } |
| 166 | uint32_t value; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 167 | }; |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 168 | std::ostream& operator<<(std::ostream& os, const ShiftedImmediate& rhs) { |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 169 | os << "#" << rhs.value; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 170 | return os; |
| 171 | } |
| 172 | |
| 173 | struct RegisterList { |
Elliott Hughes | 7484741 | 2012-06-20 18:10:21 -0700 | [diff] [blame] | 174 | explicit RegisterList(uint32_t instruction) : register_list(instruction & 0xffff) {} |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 175 | uint32_t register_list; |
| 176 | }; |
| 177 | std::ostream& operator<<(std::ostream& os, const RegisterList& rhs) { |
| 178 | if (rhs.register_list == 0) { |
| 179 | os << "<no register list?>"; |
| 180 | return os; |
| 181 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 182 | os << "{"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 183 | bool first = true; |
| 184 | for (size_t i = 0; i < 16; i++) { |
| 185 | if ((rhs.register_list & (1 << i)) != 0) { |
| 186 | if (first) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 187 | first = false; |
| 188 | } else { |
| 189 | os << ", "; |
| 190 | } |
| 191 | os << ArmRegister(i); |
| 192 | } |
| 193 | } |
| 194 | os << "}"; |
| 195 | return os; |
| 196 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 197 | |
Vladimir Marko | dd577a3 | 2013-11-07 19:25:24 +0000 | [diff] [blame] | 198 | struct FpRegister { |
| 199 | explicit FpRegister(uint32_t instr, uint16_t at_bit, uint16_t extra_at_bit) { |
| 200 | size = (instr >> 8) & 1; |
| 201 | uint32_t Vn = (instr >> at_bit) & 0xF; |
| 202 | uint32_t N = (instr >> extra_at_bit) & 1; |
| 203 | r = (size != 0 ? ((N << 4) | Vn) : ((Vn << 1) | N)); |
| 204 | } |
| 205 | FpRegister(const FpRegister& other, uint32_t offset) |
| 206 | : size(other.size), r(other.r + offset) {} |
| 207 | |
| 208 | uint32_t size; // 0 = f32, 1 = f64 |
| 209 | uint32_t r; |
| 210 | }; |
| 211 | std::ostream& operator<<(std::ostream& os, const FpRegister& rhs) { |
| 212 | return os << ((rhs.size != 0) ? "d" : "s") << rhs.r; |
| 213 | } |
| 214 | |
| 215 | struct FpRegisterRange { |
| 216 | explicit FpRegisterRange(uint32_t instr) |
| 217 | : first(instr, 12, 22), imm8(instr & 0xFF) {} |
| 218 | FpRegister first; |
| 219 | uint32_t imm8; |
| 220 | }; |
| 221 | std::ostream& operator<<(std::ostream& os, const FpRegisterRange& rhs) { |
| 222 | os << "{" << rhs.first; |
| 223 | int count = (rhs.first.size != 0 ? ((rhs.imm8 + 1u) >> 1) : rhs.imm8); |
| 224 | if (count > 1) { |
| 225 | os << "-" << FpRegister(rhs.first, count - 1); |
| 226 | } |
| 227 | if (rhs.imm8 == 0) { |
| 228 | os << " (EMPTY)"; |
| 229 | } else if (rhs.first.size != 0 && (rhs.imm8 & 1) != 0) { |
| 230 | os << rhs.first << " (HALF)"; |
| 231 | } |
| 232 | os << "}"; |
| 233 | return os; |
| 234 | } |
| 235 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 236 | void DisassemblerArm::DumpArm(std::ostream& os, const uint8_t* instr_ptr) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 237 | uint32_t instruction = ReadU32(instr_ptr); |
| 238 | uint32_t cond = (instruction >> 28) & 0xf; |
| 239 | uint32_t op1 = (instruction >> 25) & 0x7; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 240 | std::string opcode; |
| 241 | std::string suffixes; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 242 | std::ostringstream args; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 243 | switch (op1) { |
| 244 | case 0: |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 245 | case 1: // Data processing instructions. |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 246 | { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 247 | if ((instruction & 0x0ff000f0) == 0x01200070) { // BKPT |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 248 | opcode = "bkpt"; |
| 249 | uint32_t imm12 = (instruction >> 8) & 0xfff; |
| 250 | uint32_t imm4 = (instruction & 0xf); |
| 251 | args << '#' << ((imm12 << 4) | imm4); |
| 252 | break; |
| 253 | } |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 254 | if ((instruction & 0x0fffffd0) == 0x012fff10) { // BX and BLX (register) |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 255 | opcode = (((instruction >> 5) & 1) ? "blx" : "bx"); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 256 | args << ArmRegister(instruction & 0xf); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 257 | break; |
| 258 | } |
| 259 | bool i = (instruction & (1 << 25)) != 0; |
| 260 | bool s = (instruction & (1 << 20)) != 0; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 261 | uint32_t op = (instruction >> 21) & 0xf; |
| 262 | opcode = kDataProcessingOperations[op]; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 263 | bool implicit_s = ((op & ~3) == 8); // TST, TEQ, CMP, and CMN. |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 264 | if (implicit_s) { |
| 265 | // Rd is unused (and not shown), and we don't show the 's' suffix either. |
| 266 | } else { |
| 267 | if (s) { |
| 268 | suffixes += 's'; |
| 269 | } |
| 270 | args << ArmRegister(instruction, 12) << ", "; |
| 271 | } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 272 | if (i) { |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 273 | args << ArmRegister(instruction, 16) << ", " << ShiftedImmediate(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 274 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 275 | args << Rm(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 276 | } |
| 277 | } |
| 278 | break; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 279 | case 2: // Load/store word and unsigned byte. |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 280 | { |
| 281 | bool p = (instruction & (1 << 24)) != 0; |
| 282 | bool b = (instruction & (1 << 22)) != 0; |
| 283 | bool w = (instruction & (1 << 21)) != 0; |
| 284 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 285 | opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : "")); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 286 | args << ArmRegister(instruction, 12) << ", "; |
| 287 | ArmRegister rn(instruction, 16); |
| 288 | if (rn.r == 0xf) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 289 | UNIMPLEMENTED(FATAL) << "literals"; |
| 290 | } else { |
| 291 | bool wback = !p || w; |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 292 | uint32_t offset = (instruction & 0xfff); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 293 | if (p && !wback) { |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 294 | args << "[" << rn << ", #" << offset << "]"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 295 | } else if (p && wback) { |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 296 | args << "[" << rn << ", #" << offset << "]!"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 297 | } else if (!p && wback) { |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 298 | args << "[" << rn << "], #" << offset; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 299 | } else { |
| 300 | LOG(FATAL) << p << " " << w; |
| 301 | } |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 302 | if (rn.r == 9) { |
| 303 | args << " ; "; |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 304 | Thread::DumpThreadOffset(args, offset, 4); |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 305 | } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 306 | } |
| 307 | } |
| 308 | break; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 309 | case 4: // Load/store multiple. |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 310 | { |
| 311 | bool p = (instruction & (1 << 24)) != 0; |
| 312 | bool u = (instruction & (1 << 23)) != 0; |
| 313 | bool w = (instruction & (1 << 21)) != 0; |
| 314 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 315 | opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a')); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 316 | args << ArmRegister(instruction, 16) << (w ? "!" : "") << ", " << RegisterList(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 317 | } |
| 318 | break; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 319 | case 5: // Branch/branch with link. |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 320 | { |
| 321 | bool bl = (instruction & (1 << 24)) != 0; |
| 322 | opcode = (bl ? "bl" : "b"); |
Elliott Hughes | d86261e | 2012-04-11 11:23:23 -0700 | [diff] [blame] | 323 | int32_t imm26 = (instruction & 0xffffff) << 2; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 324 | int32_t imm32 = (imm26 << 6) >> 6; // Sign extend. |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 325 | DumpBranchTarget(args, instr_ptr + 8, imm32); |
| 326 | } |
| 327 | break; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 328 | default: |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 329 | opcode = "???"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 330 | break; |
| 331 | } |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 332 | opcode += kConditionCodeNames[cond]; |
| 333 | opcode += suffixes; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 334 | // TODO: a more complete ARM disassembler could generate wider opcodes. |
Ian Rogers | 2bcb4a4 | 2012-11-08 10:39:18 -0800 | [diff] [blame] | 335 | os << StringPrintf("%p: %08x\t%-7s ", instr_ptr, instruction, opcode.c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 336 | } |
| 337 | |
Ian Rogers | a9650dd | 2013-10-04 08:23:32 -0700 | [diff] [blame] | 338 | int32_t ThumbExpand(int32_t imm12) { |
| 339 | if ((imm12 & 0xC00) == 0) { |
| 340 | switch ((imm12 >> 8) & 3) { |
| 341 | case 0: |
| 342 | return imm12 & 0xFF; |
| 343 | case 1: |
| 344 | return ((imm12 & 0xFF) << 16) | (imm12 & 0xFF); |
| 345 | case 2: |
| 346 | return ((imm12 & 0xFF) << 24) | ((imm12 & 0xFF) << 8); |
| 347 | default: // 3 |
| 348 | return ((imm12 & 0xFF) << 24) | ((imm12 & 0xFF) << 16) | ((imm12 & 0xFF) << 8) | |
| 349 | (imm12 & 0xFF); |
| 350 | } |
| 351 | } else { |
| 352 | uint32_t val = 0x80 | (imm12 & 0x7F); |
| 353 | int32_t rotate = (imm12 >> 7) & 0x1F; |
| 354 | return (val >> rotate) | (val << (32 - rotate)); |
| 355 | } |
| 356 | } |
| 357 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 358 | size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) { |
| 359 | uint32_t instr = (ReadU16(instr_ptr) << 16) | ReadU16(instr_ptr + 2); |
| 360 | // |111|1 1|1000000|0000|1111110000000000| |
| 361 | // |5 3|2 1|0987654|3 0|5 0 5 0| |
| 362 | // |---|---|-------|----|----------------| |
| 363 | // |332|2 2|2222222|1111|1111110000000000| |
| 364 | // |1 9|8 7|6543210|9 6|5 0 5 0| |
| 365 | // |---|---|-------|----|----------------| |
| 366 | // |111|op1| op2 | | | |
| 367 | uint32_t op1 = (instr >> 27) & 3; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 368 | if (op1 == 0) { |
| 369 | return DumpThumb16(os, instr_ptr); |
| 370 | } |
| 371 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 372 | uint32_t op2 = (instr >> 20) & 0x7F; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 373 | std::ostringstream opcode; |
| 374 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 375 | switch (op1) { |
| 376 | case 0: |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 377 | break; |
| 378 | case 1: |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 379 | if ((op2 & 0x64) == 0) { // 00x x0xx |
| 380 | // |111|11|10|00|0|00|0000|1111110000000000| |
| 381 | // |5 3|21|09|87|6|54|3 0|5 0 5 0| |
| 382 | // |---|--|--|--|-|--|----|----------------| |
| 383 | // |332|22|22|22|2|22|1111|1111110000000000| |
| 384 | // |1 9|87|65|43|2|10|9 6|5 0 5 0| |
| 385 | // |---|--|--|--|-|--|----|----------------| |
| 386 | // |111|01|00|op|0|WL| Rn | | |
| 387 | // |111|01| op2 | | | |
| 388 | // STM - 111 01 00-01-0-W0 nnnn rrrrrrrrrrrrrrrr |
| 389 | // LDM - 111 01 00-01-0-W1 nnnn rrrrrrrrrrrrrrrr |
| 390 | // PUSH- 111 01 00-01-0-10 1101 0M0rrrrrrrrrrrrr |
| 391 | // POP - 111 01 00-01-0-11 1101 PM0rrrrrrrrrrrrr |
| 392 | uint32_t op = (instr >> 23) & 3; |
| 393 | uint32_t W = (instr >> 21) & 1; |
| 394 | uint32_t L = (instr >> 20) & 1; |
| 395 | ArmRegister Rn(instr, 16); |
| 396 | if (op == 1 || op == 2) { |
| 397 | if (op == 1) { |
| 398 | if (L == 0) { |
| 399 | opcode << "stm"; |
| 400 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 401 | } else { |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 402 | if (Rn.r != 13) { |
| 403 | opcode << "ldm"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 404 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 405 | } else { |
| 406 | opcode << "pop"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 407 | } |
| 408 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 409 | } else { |
| 410 | if (L == 0) { |
| 411 | if (Rn.r != 13) { |
| 412 | opcode << "stmdb"; |
| 413 | args << Rn << (W == 0 ? "" : "!") << ", "; |
| 414 | } else { |
| 415 | opcode << "push"; |
| 416 | } |
| 417 | } else { |
| 418 | opcode << "ldmdb"; |
| 419 | args << Rn << (W == 0 ? "" : "!") << ", "; |
| 420 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 421 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 422 | args << RegisterList(instr); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 423 | } |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 424 | } else if ((op2 & 0x64) == 4) { // 00x x1xx |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 425 | uint32_t op3 = (instr >> 23) & 3; |
| 426 | uint32_t op4 = (instr >> 20) & 3; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 427 | // uint32_t op5 = (instr >> 4) & 0xF; |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 428 | ArmRegister Rn(instr, 16); |
| 429 | ArmRegister Rt(instr, 12); |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 430 | ArmRegister Rd(instr, 8); |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 431 | uint32_t imm8 = instr & 0xFF; |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 432 | if ((op3 & 2) == 2) { // 1x |
| 433 | int W = (instr >> 21) & 1; |
| 434 | int U = (instr >> 23) & 1; |
| 435 | int P = (instr >> 24) & 1; |
| 436 | |
| 437 | if ((op4 & 1) == 1) { |
| 438 | opcode << "ldrd"; |
| 439 | } else { |
| 440 | opcode << "strd"; |
| 441 | } |
| 442 | args << Rt << "," << Rd << ", [" << Rn; |
| 443 | const char *sign = U ? "+" : "-"; |
| 444 | if (P == 0 && W == 1) { |
Vladimir Marko | ad435eb | 2013-11-15 15:21:25 +0000 | [diff] [blame] | 445 | args << "], #" << sign << (imm8 << 2); |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 446 | } else { |
Vladimir Marko | ad435eb | 2013-11-15 15:21:25 +0000 | [diff] [blame] | 447 | args << ", #" << sign << (imm8 << 2) << "]"; |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 448 | if (W == 1) { |
| 449 | args << "!"; |
| 450 | } |
| 451 | } |
| 452 | } else { // 0x |
| 453 | switch (op4) { |
| 454 | case 0: |
| 455 | if (op3 == 0) { // op3 is 00, op4 is 00 |
| 456 | opcode << "strex"; |
| 457 | args << Rd << ", " << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]"; |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 458 | if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || |
| 459 | Rd.r == Rn.r || Rd.r == Rt.r) { |
| 460 | args << " (UNPREDICTABLE)"; |
| 461 | } |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 462 | } else { // op3 is 01, op4 is 00 |
| 463 | // this is one of strexb, strexh or strexd |
| 464 | int op5 = (instr >> 4) & 0xf; |
| 465 | switch (op5) { |
| 466 | case 4: |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 467 | case 5: |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 468 | opcode << ((op5 == 4) ? "strexb" : "strexh"); |
| 469 | Rd = ArmRegister(instr, 0); |
| 470 | args << Rd << ", " << Rt << ", [" << Rn << "]"; |
| 471 | if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || |
| 472 | Rd.r == Rn.r || Rd.r == Rt.r || (instr & 0xf00) != 0xf00) { |
| 473 | args << " (UNPREDICTABLE)"; |
| 474 | } |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 475 | break; |
| 476 | case 7: |
| 477 | opcode << "strexd"; |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 478 | ArmRegister Rt2 = Rd; |
| 479 | Rd = ArmRegister(instr, 0); |
| 480 | args << Rd << ", " << Rt << ", " << Rt2 << ", [" << Rn << "]"; |
| 481 | if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || |
| 482 | Rt2.r == 13 || Rt2.r == 15 || Rn.r == 15 || |
| 483 | Rd.r == Rn.r || Rd.r == Rt.r || Rd.r == Rt2.r) { |
| 484 | args << " (UNPREDICTABLE)"; |
| 485 | } |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 486 | break; |
| 487 | } |
| 488 | } |
| 489 | break; |
| 490 | case 1: |
| 491 | if (op3 == 0) { // op3 is 00, op4 is 01 |
| 492 | opcode << "ldrex"; |
| 493 | args << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]"; |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 494 | if (Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || (instr & 0xf00) != 0xf00) { |
| 495 | args << " (UNPREDICTABLE)"; |
| 496 | } |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 497 | } else { // op3 is 01, op4 is 01 |
| 498 | // this is one of strexb, strexh or strexd |
| 499 | int op5 = (instr >> 4) & 0xf; |
| 500 | switch (op5) { |
| 501 | case 0: |
| 502 | opcode << "tbb"; |
| 503 | break; |
| 504 | case 1: |
| 505 | opcode << "tbh"; |
| 506 | break; |
| 507 | case 4: |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 508 | case 5: |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 509 | opcode << ((op5 == 4) ? "ldrexb" : "ldrexh"); |
| 510 | args << Rt << ", [" << Rn << "]"; |
| 511 | if (Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || (instr & 0xf0f) != 0xf0f) { |
| 512 | args << " (UNPREDICTABLE)"; |
| 513 | } |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 514 | break; |
| 515 | case 7: |
| 516 | opcode << "ldrexd"; |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 517 | args << Rt << ", " << Rd /* Rt2 */ << ", [" << Rn << "]"; |
| 518 | if (Rt.r == 13 || Rt.r == 15 || Rd.r == 13 /* Rt2 */ || Rd.r == 15 /* Rt2 */ || |
| 519 | Rn.r == 15 || (instr & 0x00f) != 0x00f) { |
| 520 | args << " (UNPREDICTABLE)"; |
| 521 | } |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 522 | break; |
| 523 | } |
| 524 | } |
| 525 | break; |
| 526 | case 2: // op3 is 0x, op4 is 10 |
| 527 | case 3: // op3 is 0x, op4 is 11 |
| 528 | if (op4 == 2) { |
| 529 | opcode << "strd"; |
| 530 | } else { |
| 531 | opcode << "ldrd"; |
| 532 | } |
| 533 | int W = (instr >> 21) & 1; |
| 534 | int U = (instr >> 23) & 1; |
| 535 | int P = (instr >> 24) & 1; |
| 536 | |
| 537 | args << Rt << "," << Rd << ", [" << Rn; |
| 538 | const char *sign = U ? "+" : "-"; |
| 539 | if (P == 0 && W == 1) { |
| 540 | args << "], #" << sign << imm8; |
| 541 | } else { |
| 542 | args << ", #" << sign << imm8 << "]"; |
| 543 | if (W == 1) { |
| 544 | args << "!"; |
| 545 | } |
| 546 | } |
| 547 | break; |
| 548 | } |
| 549 | } |
| 550 | |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 551 | } else if ((op2 & 0x60) == 0x20) { // 01x xxxx |
| 552 | // Data-processing (shifted register) |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 553 | // |111|1110|0000|0|0000|1111|1100|00|00|0000| |
| 554 | // |5 3|2109|8765|4|3 0|5 |10 8|7 |5 |3 0| |
| 555 | // |---|----|----|-|----|----|----|--|--|----| |
| 556 | // |332|2222|2222|2|1111|1111|1100|00|00|0000| |
| 557 | // |1 9|8765|4321|0|9 6|5 |10 8|7 |5 |3 0| |
| 558 | // |---|----|----|-|----|----|----|--|--|----| |
| 559 | // |111|0101| op3|S| Rn |imm3| Rd |i2|ty| Rm | |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 560 | uint32_t op3 = (instr >> 21) & 0xF; |
| 561 | uint32_t S = (instr >> 20) & 1; |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 562 | uint32_t imm3 = ((instr >> 12) & 0x7); |
| 563 | uint32_t imm2 = ((instr >> 6) & 0x3); |
| 564 | uint32_t imm5 = ((imm3 << 3) | imm2) & 0x1F; |
| 565 | uint32_t shift_type = ((instr >> 4) & 0x2); |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 566 | ArmRegister Rd(instr, 8); |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 567 | ArmRegister Rn(instr, 16); |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 568 | ArmRegister Rm(instr, 0); |
| 569 | switch (op3) { |
| 570 | case 0x0: |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 571 | if (Rd.r != 0xF) { |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 572 | opcode << "and"; |
| 573 | } else { |
Brian Carlstrom | 4a999e2 | 2013-03-11 16:57:09 -0700 | [diff] [blame] | 574 | if (S != 1U) { |
| 575 | opcode << "UNKNOWN TST-" << S; |
| 576 | break; |
| 577 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 578 | opcode << "tst"; |
| 579 | S = 0; // don't print 's' |
| 580 | } |
| 581 | break; |
| 582 | case 0x1: opcode << "bic"; break; |
| 583 | case 0x2: |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 584 | if (Rn.r != 0xF) { |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 585 | opcode << "orr"; |
| 586 | } else { |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 587 | // TODO: use canonical form if there is a shift (lsl, ...). |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 588 | opcode << "mov"; |
| 589 | } |
| 590 | break; |
| 591 | case 0x3: |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 592 | if (Rn.r != 0xF) { |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 593 | opcode << "orn"; |
| 594 | } else { |
| 595 | opcode << "mvn"; |
| 596 | } |
| 597 | break; |
| 598 | case 0x4: |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 599 | if (Rd.r != 0xF) { |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 600 | opcode << "eor"; |
| 601 | } else { |
Brian Carlstrom | 4a999e2 | 2013-03-11 16:57:09 -0700 | [diff] [blame] | 602 | if (S != 1U) { |
| 603 | opcode << "UNKNOWN TEQ-" << S; |
| 604 | break; |
| 605 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 606 | opcode << "teq"; |
| 607 | S = 0; // don't print 's' |
| 608 | } |
| 609 | break; |
| 610 | case 0x6: opcode << "pkh"; break; |
| 611 | case 0x8: |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 612 | if (Rd.r != 0xF) { |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 613 | opcode << "add"; |
| 614 | } else { |
Brian Carlstrom | 4a999e2 | 2013-03-11 16:57:09 -0700 | [diff] [blame] | 615 | if (S != 1U) { |
| 616 | opcode << "UNKNOWN CMN-" << S; |
| 617 | break; |
| 618 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 619 | opcode << "cmn"; |
| 620 | S = 0; // don't print 's' |
| 621 | } |
| 622 | break; |
| 623 | case 0xA: opcode << "adc"; break; |
| 624 | case 0xB: opcode << "sbc"; break; |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 625 | case 0xD: |
| 626 | if (Rd.r != 0xF) { |
| 627 | opcode << "sub"; |
| 628 | } else { |
Brian Carlstrom | 4a999e2 | 2013-03-11 16:57:09 -0700 | [diff] [blame] | 629 | if (S != 1U) { |
| 630 | opcode << "UNKNOWN CMP-" << S; |
| 631 | break; |
| 632 | } |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 633 | opcode << "cmp"; |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 634 | S = 0; // don't print 's' |
| 635 | } |
| 636 | break; |
| 637 | case 0xE: opcode << "rsb"; break; |
| 638 | default: opcode << "UNKNOWN DPSR-" << op3; break; |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 639 | } |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 640 | |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 641 | if (S == 1) { |
| 642 | opcode << "s"; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 643 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 644 | opcode << ".w"; |
Sebastien Hertz | d9e63c0 | 2013-02-22 15:19:55 +0100 | [diff] [blame] | 645 | |
| 646 | if (Rd.r != 0xF) { |
| 647 | args << Rd << ", "; |
| 648 | } |
| 649 | if (Rn.r != 0xF) { |
| 650 | args << Rn << ", "; |
| 651 | } |
| 652 | args << Rm; |
| 653 | |
| 654 | // Shift operand. |
| 655 | bool noShift = (imm5 == 0 && shift_type != 0x3); |
| 656 | if (!noShift) { |
| 657 | args << ", "; |
| 658 | switch (shift_type) { |
| 659 | case 0x0: args << "lsl"; break; |
| 660 | case 0x1: args << "lsr"; break; |
| 661 | case 0x2: args << "asr"; break; |
| 662 | case 0x3: |
| 663 | if (imm5 == 0) { |
| 664 | args << "rrx"; |
| 665 | } else { |
| 666 | args << "ror"; |
| 667 | } |
| 668 | break; |
| 669 | } |
| 670 | if (shift_type != 0x3 /* rrx */) { |
| 671 | args << StringPrintf(" #%d", imm5); |
| 672 | } |
| 673 | } |
| 674 | |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 675 | } else if ((op2 & 0x40) == 0x40) { // 1xx xxxx |
| 676 | // Co-processor instructions |
| 677 | // |111|1|11|000000|0000|1111|1100|000|0 |0000| |
| 678 | // |5 3|2|10|987654|3 0|54 2|10 8|7 5|4 | 0| |
| 679 | // |---|-|--|------|----|----|----|---|---|----| |
| 680 | // |332|2|22|222222|1111|1111|1100|000|0 |0000| |
| 681 | // |1 9|8|76|543210|9 6|54 2|10 8|7 5|4 | 0| |
| 682 | // |---|-|--|------|----|----|----|---|---|----| |
| 683 | // |111| |11| op3 | Rn | |copr| |op4| | |
| 684 | uint32_t op3 = (instr >> 20) & 0x3F; |
| 685 | uint32_t coproc = (instr >> 8) & 0xF; |
| 686 | uint32_t op4 = (instr >> 4) & 0x1; |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 687 | |
Ian Rogers | ef6a776 | 2013-12-19 17:58:05 -0800 | [diff] [blame] | 688 | if (coproc == 0xA || coproc == 0xB) { // 101x |
Vladimir Marko | dd577a3 | 2013-11-07 19:25:24 +0000 | [diff] [blame] | 689 | if (op3 < 0x20 && (op3 & ~5) != 0) { // 0xxxxx and not 000x0x |
| 690 | // Extension register load/store instructions |
| 691 | // |1111|110|00000|0000|1111|110|0|00000000| |
| 692 | // |5 2|1 9|87654|3 0|5 2|1 9|8|7 0| |
| 693 | // |----|---|-----|----|----|---|-|--------| |
| 694 | // |3322|222|22222|1111|1111|110|0|00000000| |
| 695 | // |1 8|7 5|4 0|9 6|5 2|1 9|8|7 0| |
| 696 | // |----|---|-----|----|----|---|-|--------| |
| 697 | // |1110|110|PUDWL| Rn | Vd |101|S| imm8 | |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 698 | uint32_t P = (instr >> 24) & 1; |
| 699 | uint32_t U = (instr >> 23) & 1; |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 700 | uint32_t W = (instr >> 21) & 1; |
Vladimir Marko | dd577a3 | 2013-11-07 19:25:24 +0000 | [diff] [blame] | 701 | if (P == U && W == 1) { |
| 702 | opcode << "UNDEFINED"; |
| 703 | } else { |
| 704 | uint32_t L = (instr >> 20) & 1; |
| 705 | uint32_t S = (instr >> 8) & 1; |
| 706 | ArmRegister Rn(instr, 16); |
| 707 | if (P == 1 && W == 0) { // VLDR |
| 708 | FpRegister d(instr, 12, 22); |
| 709 | uint32_t imm8 = instr & 0xFF; |
| 710 | opcode << (L == 1 ? "vldr" : "vstr"); |
| 711 | args << d << ", [" << Rn << ", #" << ((U == 1) ? "" : "-") |
| 712 | << (imm8 << 2) << "]"; |
Ian Rogers | ef6a776 | 2013-12-19 17:58:05 -0800 | [diff] [blame] | 713 | if (Rn.r == 15 && U == 1) { |
| 714 | intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr); |
| 715 | lit_adr = RoundDown(lit_adr, 4) + 4 + (imm8 << 2); |
Ian Rogers | ef7d42f | 2014-01-06 12:55:46 -0800 | [diff] [blame] | 716 | args << StringPrintf(" ; 0x%" PRIx64, *reinterpret_cast<int64_t*>(lit_adr)); |
Ian Rogers | ef6a776 | 2013-12-19 17:58:05 -0800 | [diff] [blame] | 717 | } |
Vladimir Marko | dd577a3 | 2013-11-07 19:25:24 +0000 | [diff] [blame] | 718 | } else if (Rn.r == 13 && W == 1 && U == L) { // VPUSH/VPOP |
| 719 | opcode << (L == 1 ? "vpop" : "vpush"); |
| 720 | args << FpRegisterRange(instr); |
| 721 | } else { // VLDM |
| 722 | opcode << (L == 1 ? "vldm" : "vstm"); |
| 723 | args << Rn << ((W == 1) ? "!" : "") << ", " |
| 724 | << FpRegisterRange(instr); |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 725 | } |
Vladimir Marko | dd577a3 | 2013-11-07 19:25:24 +0000 | [diff] [blame] | 726 | opcode << (S == 1 ? ".f64" : ".f32"); |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 727 | } |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 728 | } else if ((op3 >> 1) == 2) { // 00010x |
Vladimir Marko | dd577a3 | 2013-11-07 19:25:24 +0000 | [diff] [blame] | 729 | if ((instr & 0xD0) == 0x10) { |
| 730 | // 64bit transfers between ARM core and extension registers. |
| 731 | uint32_t L = (instr >> 20) & 1; |
| 732 | uint32_t S = (instr >> 8) & 1; |
| 733 | ArmRegister Rt2(instr, 16); |
| 734 | ArmRegister Rt(instr, 12); |
| 735 | FpRegister m(instr, 0, 5); |
| 736 | opcode << "vmov" << (S ? ".f64" : ".f32"); |
| 737 | if (L == 1) { |
| 738 | args << Rt << ", " << Rt2 << ", "; |
| 739 | } |
| 740 | if (S) { |
| 741 | args << m; |
| 742 | } else { |
| 743 | args << m << ", " << FpRegister(m, 1); |
| 744 | } |
| 745 | if (L == 0) { |
| 746 | args << ", " << Rt << ", " << Rt2; |
| 747 | } |
| 748 | if (Rt.r == 15 || Rt.r == 13 || Rt2.r == 15 || Rt2.r == 13 || |
| 749 | (S == 0 && m.r == 31) || (L == 1 && Rt.r == Rt2.r)) { |
| 750 | args << " (UNPREDICTABLE)"; |
| 751 | } |
| 752 | } |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 753 | } else if ((op3 >> 4) == 2 && op4 == 0) { // 10xxxx, op = 0 |
| 754 | // fp data processing |
| 755 | } else if ((op3 >> 4) == 2 && op4 == 1) { // 10xxxx, op = 1 |
Vladimir Marko | dd577a3 | 2013-11-07 19:25:24 +0000 | [diff] [blame] | 756 | if (coproc == 10 && (op3 & 0xE) == 0) { |
| 757 | // VMOV (between ARM core register and single-precision register) |
| 758 | // |1111|1100|000|0 |0000|1111|1100|0|00|0|0000| |
| 759 | // |5 |1 8|7 5|4 |3 0|5 2|1 8|7|65|4|3 0| |
| 760 | // |----|----|---|- |----|----|----|-|--|-|----| |
| 761 | // |3322|2222|222|2 |1111|1111|1100|0|00|0|0000| |
| 762 | // |1 8|7 4|3 1|0 |9 6|5 2|1 8|7|65|4|3 0| |
| 763 | // |----|----|---|- |----|----|----|-|--|-|----| |
| 764 | // |1110|1110|000|op| Vn | Rt |1010|N|00|1|0000| |
| 765 | uint32_t op = op3 & 1; |
| 766 | ArmRegister Rt(instr, 12); |
| 767 | FpRegister n(instr, 16, 7); |
| 768 | opcode << "vmov.f32"; |
| 769 | if (op) { |
| 770 | args << Rt << ", " << n; |
| 771 | } else { |
| 772 | args << n << ", " << Rt; |
| 773 | } |
| 774 | if (Rt.r == 13 || Rt.r == 15 || (instr & 0x6F) != 0) { |
| 775 | args << " (UNPREDICTABLE)"; |
| 776 | } |
| 777 | } else if (coproc == 10 && op3 == 0x2F) { |
| 778 | // VMRS |
| 779 | // |1111|11000000|0000|1111|1100|000|0|0000| |
| 780 | // |5 |1 4|3 0|5 2|1 8|7 5|4|3 0| |
| 781 | // |----|--------|----|----|----|---|-|----| |
| 782 | // |3322|22222222|1111|1111|1100|000|0|0000| |
| 783 | // |1 8|7 0|9 6|5 2|1 8|7 5|4|3 0| |
| 784 | // |----|--------|----|----|----|---|-|----| |
| 785 | // |1110|11101111|reg | Rt |1010|000|1|0000| - last 7 0s are (0) |
| 786 | uint32_t spec_reg = (instr >> 16) & 0xF; |
| 787 | ArmRegister Rt(instr, 12); |
| 788 | opcode << "vmrs"; |
| 789 | if (spec_reg == 1) { |
| 790 | if (Rt.r == 15) { |
| 791 | args << "APSR_nzcv, FPSCR"; |
| 792 | } else if (Rt.r == 13) { |
| 793 | args << Rt << ", FPSCR (UNPREDICTABLE)"; |
| 794 | } else { |
| 795 | args << Rt << ", FPSCR"; |
| 796 | } |
| 797 | } else { |
| 798 | args << "(PRIVILEGED)"; |
| 799 | } |
| 800 | } else if (coproc == 11 && (op3 & 0x9) != 8) { |
| 801 | // VMOV (ARM core register to scalar or vice versa; 8/16/32-bit) |
| 802 | } |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 803 | } |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 804 | } |
| 805 | |
| 806 | if ((op3 & 0x30) == 0x20 && op4 == 0) { // 10 xxxx ... 0 |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 807 | if ((coproc & 0xE) == 0xA) { |
| 808 | // VFP data-processing instructions |
| 809 | // |111|1|1100|0000|0000|1111|110|0|00 |0|0|0000| |
| 810 | // |5 3|2|1098|7654|3 0|54 2|10 |8|76 |5|4|3 0| |
| 811 | // |---|-|----|----|----|----|---|-|----|-|-|----| |
| 812 | // |332|2|2222|2222|1111|1111|110|0|00 |0|0|0000| |
| 813 | // |1 9|8|7654|3210|9 6|54 2|109|8|76 |5|4|3 0| |
| 814 | // |---|-|----|----|----|----|---|-|----|-|-|----| |
| 815 | // |111|T|1110|opc1|opc2| |101| |opc3| | | | |
| 816 | // 111 0 1110|1111 0100 1110 101 0 01 1 0 1001 - eef4ea69 |
| 817 | uint32_t opc1 = (instr >> 20) & 0xF; |
| 818 | uint32_t opc2 = (instr >> 16) & 0xF; |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 819 | uint32_t opc3 = (instr >> 6) & 0x3; |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 820 | if ((opc1 & 0xB) == 0xB) { // 1x11 |
| 821 | // Other VFP data-processing instructions. |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 822 | uint32_t sz = (instr >> 8) & 1; |
Vladimir Marko | dd577a3 | 2013-11-07 19:25:24 +0000 | [diff] [blame] | 823 | FpRegister d(instr, 12, 22); |
| 824 | FpRegister m(instr, 0, 5); |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 825 | switch (opc2) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 826 | case 0x1: // Vneg/Vsqrt |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 827 | // 1110 11101 D 11 0001 dddd 101s o1M0 mmmm |
Vladimir Marko | dd577a3 | 2013-11-07 19:25:24 +0000 | [diff] [blame] | 828 | opcode << (opc3 == 1 ? "vneg" : "vsqrt") << (sz == 1 ? ".f64" : ".f32"); |
| 829 | args << d << ", " << m; |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 830 | break; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 831 | case 0x4: case 0x5: { // Vector compare |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 832 | // 1110 11101 D 11 0100 dddd 101 sE1M0 mmmm |
Vladimir Marko | dd577a3 | 2013-11-07 19:25:24 +0000 | [diff] [blame] | 833 | opcode << (opc3 == 1 ? "vcmp" : "vcmpe") << (sz == 1 ? ".f64" : ".f32"); |
| 834 | args << d << ", " << m; |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 835 | break; |
| 836 | } |
| 837 | } |
| 838 | } |
| 839 | } |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 840 | } else if ((op3 & 0x30) == 0x30) { // 11 xxxx |
| 841 | // Advanced SIMD |
| 842 | if ((instr & 0xFFBF0ED0) == 0xeeb10ac0) { // Vsqrt |
| 843 | // 1110 11101 D 11 0001 dddd 101S 11M0 mmmm |
| 844 | // 1110 11101 0 11 0001 1101 1011 1100 1000 - eeb1dbc8 |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 845 | uint32_t sz = (instr >> 8) & 1; |
Vladimir Marko | dd577a3 | 2013-11-07 19:25:24 +0000 | [diff] [blame] | 846 | FpRegister d(instr, 12, 22); |
| 847 | FpRegister m(instr, 0, 5); |
| 848 | opcode << "vsqrt" << (sz == 1 ? ".f64" : ".f32"); |
| 849 | args << d << ", " << m; |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 850 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 851 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 852 | } |
| 853 | break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 854 | case 2: |
| 855 | if ((instr & 0x8000) == 0 && (op2 & 0x20) == 0) { |
| 856 | // Data-processing (modified immediate) |
| 857 | // |111|11|10|0000|0|0000|1|111|1100|00000000| |
| 858 | // |5 3|21|09|8765|4|3 0|5|4 2|10 8|7 5 0| |
| 859 | // |---|--|--|----|-|----|-|---|----|--------| |
| 860 | // |332|22|22|2222|2|1111|1|111|1100|00000000| |
| 861 | // |1 9|87|65|4321|0|9 6|5|4 2|10 8|7 5 0| |
| 862 | // |---|--|--|----|-|----|-|---|----|--------| |
| 863 | // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii| |
| 864 | // 111 10 x0 xxxx x xxxx opxxx xxxx xxxxxxxx |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 865 | uint32_t i = (instr >> 26) & 1; |
| 866 | uint32_t op3 = (instr >> 21) & 0xF; |
| 867 | uint32_t S = (instr >> 20) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 868 | ArmRegister Rn(instr, 16); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 869 | uint32_t imm3 = (instr >> 12) & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 870 | ArmRegister Rd(instr, 8); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 871 | uint32_t imm8 = instr & 0xFF; |
Jeff Hao | 7cb0f9c | 2013-02-04 16:15:27 -0800 | [diff] [blame] | 872 | int32_t imm32 = (i << 11) | (imm3 << 8) | imm8; |
| 873 | if (Rn.r == 0xF && (op3 == 0x2 || op3 == 0x3)) { |
| 874 | if (op3 == 0x2) { |
| 875 | opcode << "mov"; |
| 876 | if (S == 1) { |
| 877 | opcode << "s"; |
| 878 | } |
| 879 | opcode << ".w"; |
| 880 | } else { |
| 881 | opcode << "mvn"; |
| 882 | if (S == 1) { |
| 883 | opcode << "s"; |
| 884 | } |
| 885 | } |
Ian Rogers | a9650dd | 2013-10-04 08:23:32 -0700 | [diff] [blame] | 886 | args << Rd << ", #" << ThumbExpand(imm32); |
Jeff Hao | 7cb0f9c | 2013-02-04 16:15:27 -0800 | [diff] [blame] | 887 | } else if (Rd.r == 0xF && S == 1 && |
| 888 | (op3 == 0x0 || op3 == 0x4 || op3 == 0x8 || op3 == 0xD)) { |
| 889 | if (op3 == 0x0) { |
| 890 | opcode << "tst"; |
| 891 | } else if (op3 == 0x4) { |
| 892 | opcode << "teq"; |
| 893 | } else if (op3 == 0x8) { |
Vladimir Marko | 2247984 | 2013-11-19 17:04:50 +0000 | [diff] [blame] | 894 | opcode << "cmn.w"; |
Jeff Hao | 7cb0f9c | 2013-02-04 16:15:27 -0800 | [diff] [blame] | 895 | } else { |
| 896 | opcode << "cmp.w"; |
| 897 | } |
Ian Rogers | a9650dd | 2013-10-04 08:23:32 -0700 | [diff] [blame] | 898 | args << Rn << ", #" << ThumbExpand(imm32); |
Jeff Hao | 7cb0f9c | 2013-02-04 16:15:27 -0800 | [diff] [blame] | 899 | } else { |
| 900 | switch (op3) { |
| 901 | case 0x0: opcode << "and"; break; |
| 902 | case 0x1: opcode << "bic"; break; |
| 903 | case 0x2: opcode << "orr"; break; |
| 904 | case 0x3: opcode << "orn"; break; |
| 905 | case 0x4: opcode << "eor"; break; |
| 906 | case 0x8: opcode << "add"; break; |
| 907 | case 0xA: opcode << "adc"; break; |
| 908 | case 0xB: opcode << "sbc"; break; |
| 909 | case 0xD: opcode << "sub"; break; |
| 910 | case 0xE: opcode << "rsb"; break; |
| 911 | default: opcode << "UNKNOWN DPMI-" << op3; break; |
| 912 | } |
| 913 | if (S == 1) { |
| 914 | opcode << "s"; |
| 915 | } |
Ian Rogers | a9650dd | 2013-10-04 08:23:32 -0700 | [diff] [blame] | 916 | args << Rd << ", " << Rn << ", #" << ThumbExpand(imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 917 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 918 | } else if ((instr & 0x8000) == 0 && (op2 & 0x20) != 0) { |
| 919 | // Data-processing (plain binary immediate) |
| 920 | // |111|11|10|00000|0000|1|111110000000000| |
| 921 | // |5 3|21|09|87654|3 0|5|4 0 5 0| |
| 922 | // |---|--|--|-----|----|-|---------------| |
| 923 | // |332|22|22|22222|1111|1|111110000000000| |
| 924 | // |1 9|87|65|43210|9 6|5|4 0 5 0| |
| 925 | // |---|--|--|-----|----|-|---------------| |
| 926 | // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx| |
| 927 | uint32_t op3 = (instr >> 20) & 0x1F; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 928 | switch (op3) { |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame] | 929 | case 0x00: case 0x0A: { |
| 930 | // ADD/SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 931 | ArmRegister Rd(instr, 8); |
| 932 | ArmRegister Rn(instr, 16); |
| 933 | uint32_t i = (instr >> 26) & 1; |
| 934 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 935 | uint32_t imm8 = instr & 0xFF; |
| 936 | uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8; |
| 937 | if (Rn.r != 0xF) { |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame] | 938 | opcode << (op3 == 0 ? "addw" : "subw"); |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 939 | args << Rd << ", " << Rn << ", #" << imm12; |
| 940 | } else { |
| 941 | opcode << "adr"; |
| 942 | args << Rd << ", "; |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame] | 943 | DumpBranchTarget(args, instr_ptr + 4, (op3 == 0) ? imm12 : -imm12); |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 944 | } |
| 945 | break; |
| 946 | } |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame] | 947 | case 0x04: case 0x0C: { |
| 948 | // MOVW/T Rd, #imm16 - 111 10 i0 0010 0 iiii 0 iii dddd iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 949 | ArmRegister Rd(instr, 8); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 950 | uint32_t i = (instr >> 26) & 1; |
| 951 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 952 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 953 | uint32_t Rn = (instr >> 16) & 0xF; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 954 | uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8; |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame] | 955 | opcode << (op3 == 0x04 ? "movw" : "movt"); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 956 | args << Rd << ", #" << imm16; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 957 | break; |
| 958 | } |
jeffhao | eae2691 | 2013-01-28 16:29:54 -0800 | [diff] [blame] | 959 | case 0x16: { |
| 960 | // BFI Rd, Rn, #lsb, #width - 111 10 0 11 011 0 nnnn 0 iii dddd ii 0 iiiii |
| 961 | ArmRegister Rd(instr, 8); |
| 962 | ArmRegister Rn(instr, 16); |
| 963 | uint32_t msb = instr & 0x1F; |
| 964 | uint32_t imm2 = (instr >> 6) & 0x3; |
| 965 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 966 | uint32_t lsb = (imm3 << 2) | imm2; |
| 967 | uint32_t width = msb - lsb + 1; |
| 968 | if (Rn.r != 0xF) { |
| 969 | opcode << "bfi"; |
| 970 | args << Rd << ", " << Rn << ", #" << lsb << ", #" << width; |
| 971 | } else { |
| 972 | opcode << "bfc"; |
| 973 | args << Rd << ", #" << lsb << ", #" << width; |
| 974 | } |
| 975 | break; |
| 976 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 977 | default: |
| 978 | break; |
| 979 | } |
| 980 | } else { |
| 981 | // Branches and miscellaneous control |
| 982 | // |111|11|1000000|0000|1|111|1100|00000000| |
| 983 | // |5 3|21|0987654|3 0|5|4 2|10 8|7 5 0| |
| 984 | // |---|--|-------|----|-|---|----|--------| |
| 985 | // |332|22|2222222|1111|1|111|1100|00000000| |
| 986 | // |1 9|87|6543210|9 6|5|4 2|10 8|7 5 0| |
| 987 | // |---|--|-------|----|-|---|----|--------| |
| 988 | // |111|10| op2 | |1|op3|op4 | | |
| 989 | |
| 990 | uint32_t op3 = (instr >> 12) & 7; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 991 | // uint32_t op4 = (instr >> 8) & 0xF; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 992 | switch (op3) { |
| 993 | case 0: |
| 994 | if ((op2 & 0x38) != 0x38) { |
| 995 | // Conditional branch |
| 996 | // |111|11|1|0000|000000|1|1|1 |1|1 |10000000000| |
| 997 | // |5 3|21|0|9876|543 0|5|4|3 |2|1 |0 5 0| |
| 998 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 999 | // |332|22|2|2222|221111|1|1|1 |1|1 |10000000000| |
| 1000 | // |1 9|87|6|5432|109 6|5|4|3 |2|1 |0 5 0| |
| 1001 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 1002 | // |111|10|S|cond| imm6 |1|0|J1|0|J2| imm11 | |
| 1003 | uint32_t S = (instr >> 26) & 1; |
| 1004 | uint32_t J2 = (instr >> 11) & 1; |
| 1005 | uint32_t J1 = (instr >> 13) & 1; |
| 1006 | uint32_t imm6 = (instr >> 16) & 0x3F; |
| 1007 | uint32_t imm11 = instr & 0x7FF; |
| 1008 | uint32_t cond = (instr >> 22) & 0xF; |
| 1009 | int32_t imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
| 1010 | imm32 = (imm32 << 11) >> 11; // sign extend 21bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1011 | opcode << "b"; |
| 1012 | DumpCond(opcode, cond); |
| 1013 | opcode << ".w"; |
| 1014 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 1015 | } else if (op2 == 0x3B) { |
| 1016 | // Miscellaneous control instructions |
| 1017 | uint32_t op5 = (instr >> 4) & 0xF; |
| 1018 | switch (op5) { |
Ian Rogers | b122a4b | 2013-11-19 18:00:50 -0800 | [diff] [blame] | 1019 | case 4: opcode << "dsb"; DumpMemoryDomain(args, instr & 0xF); break; |
| 1020 | case 5: opcode << "dmb"; DumpMemoryDomain(args, instr & 0xF); break; |
| 1021 | case 6: opcode << "isb"; DumpMemoryDomain(args, instr & 0xF); break; |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 1022 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1023 | } |
| 1024 | break; |
| 1025 | case 2: |
Ian Rogers | d0876a9 | 2013-02-08 11:30:38 -0800 | [diff] [blame] | 1026 | if ((op2 & 0x38) == 0x38) { |
| 1027 | if (op2 == 0x7F) { |
| 1028 | opcode << "udf"; |
| 1029 | } |
| 1030 | break; |
| 1031 | } |
| 1032 | // Else deliberate fall-through to B. |
| 1033 | case 1: case 3: { |
| 1034 | // B |
| 1035 | // |111|11|1|0000|000000|11|1 |1|1 |10000000000| |
| 1036 | // |5 3|21|0|9876|543 0|54|3 |2|1 |0 5 0| |
| 1037 | // |---|--|-|----|------|--|--|-|--|-----------| |
| 1038 | // |332|22|2|2222|221111|11|1 |1|1 |10000000000| |
| 1039 | // |1 9|87|6|5 2|10 6|54|3 |2|1 |0 5 0| |
| 1040 | // |---|--|-|----|------|--|--|-|--|-----------| |
| 1041 | // |111|10|S|cond| imm6 |10|J1|0|J2| imm11 | |
| 1042 | // |111|10|S| imm10 |10|J1|1|J2| imm11 | |
| 1043 | uint32_t S = (instr >> 26) & 1; |
| 1044 | uint32_t cond = (instr >> 22) & 0xF; |
| 1045 | uint32_t J2 = (instr >> 11) & 1; |
| 1046 | uint32_t form = (instr >> 12) & 1; |
| 1047 | uint32_t J1 = (instr >> 13) & 1; |
| 1048 | uint32_t imm10 = (instr >> 16) & 0x3FF; |
| 1049 | uint32_t imm6 = (instr >> 16) & 0x3F; |
| 1050 | uint32_t imm11 = instr & 0x7FF; |
| 1051 | opcode << "b"; |
| 1052 | int32_t imm32; |
| 1053 | if (form == 0) { |
| 1054 | DumpCond(opcode, cond); |
| 1055 | imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
| 1056 | imm32 = (imm32 << 11) >> 11; // sign extend 21 bit immediate. |
| 1057 | } else { |
| 1058 | uint32_t I1 = ~(J1 ^ S); |
| 1059 | uint32_t I2 = ~(J2 ^ S); |
| 1060 | imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
| 1061 | imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate. |
| 1062 | } |
| 1063 | opcode << ".w"; |
| 1064 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1065 | break; |
Ian Rogers | d0876a9 | 2013-02-08 11:30:38 -0800 | [diff] [blame] | 1066 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1067 | case 4: case 6: case 5: case 7: { |
| 1068 | // BL, BLX (immediate) |
| 1069 | // |111|11|1|0000000000|11|1 |1|1 |10000000000| |
| 1070 | // |5 3|21|0|9876543 0|54|3 |2|1 |0 5 0| |
| 1071 | // |---|--|-|----------|--|--|-|--|-----------| |
| 1072 | // |332|22|2|2222221111|11|1 |1|1 |10000000000| |
| 1073 | // |1 9|87|6|5 0 6|54|3 |2|1 |0 5 0| |
| 1074 | // |---|--|-|----------|--|--|-|--|-----------| |
| 1075 | // |111|10|S| imm10 |11|J1|L|J2| imm11 | |
| 1076 | uint32_t S = (instr >> 26) & 1; |
| 1077 | uint32_t J2 = (instr >> 11) & 1; |
| 1078 | uint32_t L = (instr >> 12) & 1; |
| 1079 | uint32_t J1 = (instr >> 13) & 1; |
| 1080 | uint32_t imm10 = (instr >> 16) & 0x3FF; |
| 1081 | uint32_t imm11 = instr & 0x7FF; |
| 1082 | if (L == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1083 | opcode << "bx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1084 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1085 | opcode << "blx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1086 | } |
| 1087 | uint32_t I1 = ~(J1 ^ S); |
| 1088 | uint32_t I2 = ~(J2 ^ S); |
| 1089 | int32_t imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
| 1090 | imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate. |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1091 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1092 | break; |
| 1093 | } |
| 1094 | } |
| 1095 | } |
| 1096 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1097 | case 3: |
| 1098 | switch (op2) { |
| 1099 | case 0x00: case 0x02: case 0x04: case 0x06: // 000xxx0 |
| 1100 | case 0x08: case 0x0A: case 0x0C: case 0x0E: { |
| 1101 | // Store single data item |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1102 | // |111|11|100|000|0|0000|1111|110000|000000| |
| 1103 | // |5 3|21|098|765|4|3 0|5 2|10 6|5 0| |
| 1104 | // |---|--|---|---|-|----|----|------|------| |
| 1105 | // |332|22|222|222|2|1111|1111|110000|000000| |
| 1106 | // |1 9|87|654|321|0|9 6|5 2|10 6|5 0| |
| 1107 | // |---|--|---|---|-|----|----|------|------| |
| 1108 | // |111|11|000|op3|0| | | op4 | | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1109 | uint32_t op3 = (instr >> 21) & 7; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1110 | // uint32_t op4 = (instr >> 6) & 0x3F; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1111 | switch (op3) { |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1112 | case 0x0: case 0x4: { |
| 1113 | // STRB Rt,[Rn,#+/-imm8] - 111 11 00 0 0 00 0 nnnn tttt 1 PUWii ii iiii |
| 1114 | // STRB Rt,[Rn,Rm,lsl #imm2] - 111 11 00 0 0 00 0 nnnn tttt 0 00000 ii mmmm |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1115 | ArmRegister Rn(instr, 16); |
| 1116 | ArmRegister Rt(instr, 12); |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1117 | opcode << "strb"; |
| 1118 | if ((instr & 0x800) != 0) { |
| 1119 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1120 | args << Rt << ", [" << Rn << ",#" << imm8 << "]"; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1121 | } else { |
| 1122 | uint32_t imm2 = (instr >> 4) & 3; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1123 | ArmRegister Rm(instr, 0); |
| 1124 | args << Rt << ", [" << Rn << ", " << Rm; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1125 | if (imm2 != 0) { |
| 1126 | args << ", " << "lsl #" << imm2; |
| 1127 | } |
| 1128 | args << "]"; |
| 1129 | } |
| 1130 | break; |
| 1131 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1132 | case 0x2: case 0x6: { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1133 | ArmRegister Rn(instr, 16); |
| 1134 | ArmRegister Rt(instr, 12); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1135 | if (op3 == 2) { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 1136 | if ((instr & 0x800) != 0) { |
| 1137 | // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii |
| 1138 | uint32_t P = (instr >> 10) & 1; |
| 1139 | uint32_t U = (instr >> 9) & 1; |
| 1140 | uint32_t W = (instr >> 8) & 1; |
| 1141 | uint32_t imm8 = instr & 0xFF; |
| 1142 | int32_t imm32 = (imm8 << 24) >> 24; // sign-extend imm8 |
| 1143 | if (Rn.r == 13 && P == 1 && U == 0 && W == 1 && imm32 == 4) { |
| 1144 | opcode << "push"; |
| 1145 | args << Rt; |
| 1146 | } else if (Rn.r == 15 || (P == 0 && W == 0)) { |
| 1147 | opcode << "UNDEFINED"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1148 | } else { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 1149 | if (P == 1 && U == 1 && W == 0) { |
| 1150 | opcode << "strt"; |
| 1151 | } else { |
| 1152 | opcode << "str"; |
| 1153 | } |
| 1154 | args << Rt << ", [" << Rn; |
| 1155 | if (P == 0 && W == 1) { |
| 1156 | args << "], #" << imm32; |
| 1157 | } else { |
| 1158 | args << ", #" << imm32 << "]"; |
| 1159 | if (W == 1) { |
| 1160 | args << "!"; |
| 1161 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1162 | } |
| 1163 | } |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 1164 | } else { |
| 1165 | // STR Rt, [Rn, Rm, LSL #imm2] - 111 11 000 010 0 nnnn tttt 000000iimmmm |
| 1166 | ArmRegister Rn(instr, 16); |
| 1167 | ArmRegister Rt(instr, 12); |
| 1168 | ArmRegister Rm(instr, 0); |
| 1169 | uint32_t imm2 = (instr >> 4) & 3; |
| 1170 | opcode << "str.w"; |
| 1171 | args << Rt << ", [" << Rn << ", " << Rm; |
| 1172 | if (imm2 != 0) { |
| 1173 | args << ", lsl #" << imm2; |
| 1174 | } |
| 1175 | args << "]"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1176 | } |
| 1177 | } else if (op3 == 6) { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 1178 | // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1179 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1180 | opcode << "str.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1181 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1182 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1183 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1184 | } |
| 1185 | } |
| 1186 | |
| 1187 | break; |
| 1188 | } |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1189 | case 0x03: case 0x0B: case 0x13: case 0x1B: { // 00xx011 |
jeffhao | eae2691 | 2013-01-28 16:29:54 -0800 | [diff] [blame] | 1190 | // Load halfword |
| 1191 | // |111|11|10|0 0|00|0|0000|1111|110000|000000| |
| 1192 | // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0| |
| 1193 | // |---|--|--|---|--|-|----|----|------|------| |
| 1194 | // |332|22|22|2 2|22|2|1111|1111|110000|000000| |
| 1195 | // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0| |
| 1196 | // |---|--|--|---|--|-|----|----|------|------| |
| 1197 | // |111|11|00|op3|01|1| Rn | Rt | op4 | | |
| 1198 | // |111|11| op2 | | | imm12 | |
| 1199 | uint32_t op3 = (instr >> 23) & 3; |
| 1200 | ArmRegister Rn(instr, 16); |
| 1201 | ArmRegister Rt(instr, 12); |
| 1202 | if (Rt.r != 15) { |
| 1203 | if (op3 == 1) { |
| 1204 | // LDRH.W Rt, [Rn, #imm12] - 111 11 00 01 011 nnnn tttt iiiiiiiiiiii |
| 1205 | uint32_t imm12 = instr & 0xFFF; |
| 1206 | opcode << "ldrh.w"; |
| 1207 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
| 1208 | if (Rn.r == 9) { |
| 1209 | args << " ; "; |
| 1210 | Thread::DumpThreadOffset(args, imm12, 4); |
| 1211 | } else if (Rn.r == 15) { |
| 1212 | intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr); |
| 1213 | lit_adr = RoundDown(lit_adr, 4) + 4 + imm12; |
| 1214 | args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr)); |
| 1215 | } |
| 1216 | } else if (op3 == 3) { |
| 1217 | // LDRSH.W Rt, [Rn, #imm12] - 111 11 00 11 011 nnnn tttt iiiiiiiiiiii |
| 1218 | uint32_t imm12 = instr & 0xFFF; |
| 1219 | opcode << "ldrsh.w"; |
| 1220 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
| 1221 | if (Rn.r == 9) { |
| 1222 | args << " ; "; |
| 1223 | Thread::DumpThreadOffset(args, imm12, 4); |
| 1224 | } else if (Rn.r == 15) { |
| 1225 | intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr); |
| 1226 | lit_adr = RoundDown(lit_adr, 4) + 4 + imm12; |
| 1227 | args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr)); |
| 1228 | } |
| 1229 | } |
| 1230 | } |
| 1231 | break; |
| 1232 | } |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 1233 | case 0x29: { // 0101001 |
| 1234 | // |111|11|1000000|0000|1111|1100|00|0 0|0000| |
| 1235 | // |5 3|21|0 4|3 0|5 2|1 8|76|5 4|3 0| |
| 1236 | // |---|--|-------|----|----|----|--|---|----| |
| 1237 | // |332|22|2222222|1111|1111|1100|00|0 0|0000| |
| 1238 | // |1 9|87|6 0|9 6|5 2|1 8|76|5 4|3 0| |
| 1239 | // |---|--|-------|----|----|----|--|---|----| |
| 1240 | // |111|11|0101001| Rm |1111| Rd |11|op3| Rm | |
| 1241 | // REV - 111 11 0101001 mmmm 1111 dddd 1000 mmmm |
| 1242 | // REV16 - 111 11 0101001 mmmm 1111 dddd 1001 mmmm |
| 1243 | // RBIT - 111 11 0101001 mmmm 1111 dddd 1010 mmmm |
| 1244 | // REVSH - 111 11 0101001 mmmm 1111 dddd 1011 mmmm |
| 1245 | if ((instr & 0xf0c0) == 0xf080) { |
| 1246 | uint32_t op3 = (instr >> 4) & 3; |
| 1247 | opcode << kThumbReverseOperations[op3]; |
| 1248 | ArmRegister Rm(instr, 0); |
| 1249 | ArmRegister Rd(instr, 8); |
| 1250 | args << Rd << ", " << Rm; |
| 1251 | ArmRegister Rm2(instr, 16); |
| 1252 | if (Rm.r != Rm2.r || Rm.r == 13 || Rm.r == 15 || Rd.r == 13 || Rd.r == 15) { |
| 1253 | args << " (UNPREDICTABLE)"; |
| 1254 | } |
Vladimir Marko | 1f6754d | 2013-10-28 20:27:17 +0000 | [diff] [blame] | 1255 | } // else unknown instruction |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 1256 | break; |
| 1257 | } |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1258 | case 0x05: case 0x0D: case 0x15: case 0x1D: { // 00xx101 |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1259 | // Load word |
| 1260 | // |111|11|10|0 0|00|0|0000|1111|110000|000000| |
| 1261 | // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0| |
| 1262 | // |---|--|--|---|--|-|----|----|------|------| |
| 1263 | // |332|22|22|2 2|22|2|1111|1111|110000|000000| |
| 1264 | // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0| |
| 1265 | // |---|--|--|---|--|-|----|----|------|------| |
| 1266 | // |111|11|00|op3|10|1| Rn | Rt | op4 | | |
| 1267 | // |111|11| op2 | | | imm12 | |
| 1268 | uint32_t op3 = (instr >> 23) & 3; |
| 1269 | uint32_t op4 = (instr >> 6) & 0x3F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1270 | ArmRegister Rn(instr, 16); |
| 1271 | ArmRegister Rt(instr, 12); |
| 1272 | if (op3 == 1 || Rn.r == 15) { |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1273 | // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii |
| 1274 | // LDR.W Rt, [PC, #imm12] - 111 11 00 0x 101 1111 tttt iiiiiiiiiiii |
| 1275 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1276 | opcode << "ldr.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1277 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 1278 | if (Rn.r == 9) { |
| 1279 | args << " ; "; |
| 1280 | Thread::DumpThreadOffset(args, imm12, 4); |
Ian Rogers | 5b9b1bc | 2012-04-09 22:51:43 -0700 | [diff] [blame] | 1281 | } else if (Rn.r == 15) { |
| 1282 | intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr); |
| 1283 | lit_adr = RoundDown(lit_adr, 4) + 4 + imm12; |
| 1284 | args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr)); |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 1285 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1286 | } else if (op4 == 0) { |
| 1287 | // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm |
| 1288 | uint32_t imm2 = (instr >> 4) & 0xF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1289 | ArmRegister rm(instr, 0); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1290 | opcode << "ldr.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1291 | args << Rt << ", [" << Rn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1292 | if (imm2 != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1293 | args << ", lsl #" << imm2; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1294 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1295 | args << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1296 | } else { |
| 1297 | // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii |
| 1298 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1299 | opcode << "ldrt"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1300 | args << Rt << ", [" << Rn << ", #" << imm8 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1301 | } |
| 1302 | break; |
| 1303 | } |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 1304 | default: // more formats |
| 1305 | if ((op2 >> 4) == 2) { // 010xxxx |
| 1306 | // data processing (register) |
| 1307 | } else if ((op2 >> 3) == 6) { // 0110xxx |
| 1308 | // Multiply, multiply accumulate, and absolute difference |
| 1309 | op1 = (instr >> 20) & 0x7; |
| 1310 | op2 = (instr >> 4) & 0x2; |
| 1311 | ArmRegister Ra(instr, 12); |
| 1312 | ArmRegister Rn(instr, 16); |
| 1313 | ArmRegister Rm(instr, 0); |
| 1314 | ArmRegister Rd(instr, 8); |
| 1315 | switch (op1) { |
| 1316 | case 0: |
| 1317 | if (op2 == 0) { |
| 1318 | if (Ra.r == 0xf) { |
| 1319 | opcode << "mul"; |
| 1320 | args << Rd << ", " << Rn << ", " << Rm; |
| 1321 | } else { |
| 1322 | opcode << "mla"; |
| 1323 | args << Rd << ", " << Rn << ", " << Rm << ", " << Ra; |
| 1324 | } |
| 1325 | } else { |
| 1326 | opcode << "mls"; |
| 1327 | args << Rd << ", " << Rn << ", " << Rm << ", " << Ra; |
| 1328 | } |
| 1329 | break; |
| 1330 | case 1: |
| 1331 | case 2: |
| 1332 | case 3: |
| 1333 | case 4: |
| 1334 | case 5: |
| 1335 | case 6: |
| 1336 | break; // do these sometime |
| 1337 | } |
| 1338 | } else if ((op2 >> 3) == 7) { // 0111xxx |
| 1339 | // Long multiply, long multiply accumulate, and divide |
| 1340 | op1 = (instr >> 20) & 0x7; |
| 1341 | op2 = (instr >> 4) & 0xf; |
| 1342 | ArmRegister Rn(instr, 16); |
| 1343 | ArmRegister Rm(instr, 0); |
| 1344 | ArmRegister Rd(instr, 8); |
| 1345 | ArmRegister RdHi(instr, 8); |
| 1346 | ArmRegister RdLo(instr, 12); |
| 1347 | switch (op1) { |
| 1348 | case 0: |
| 1349 | opcode << "smull"; |
| 1350 | args << RdLo << ", " << RdHi << ", " << Rn << ", " << Rm; |
| 1351 | break; |
| 1352 | case 1: |
| 1353 | opcode << "sdiv"; |
| 1354 | args << Rd << ", " << Rn << ", " << Rm; |
| 1355 | break; |
| 1356 | case 2: |
| 1357 | opcode << "umull"; |
| 1358 | args << RdLo << ", " << RdHi << ", " << Rn << ", " << Rm; |
| 1359 | break; |
| 1360 | case 3: |
| 1361 | opcode << "udiv"; |
| 1362 | args << Rd << ", " << Rn << ", " << Rm; |
| 1363 | break; |
| 1364 | case 4: |
| 1365 | case 5: |
| 1366 | case 6: |
| 1367 | break; // TODO: when we generate these... |
| 1368 | } |
| 1369 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1370 | } |
| 1371 | default: |
| 1372 | break; |
| 1373 | } |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 1374 | |
| 1375 | // Apply any IT-block conditions to the opcode if necessary. |
| 1376 | if (!it_conditions_.empty()) { |
| 1377 | opcode << it_conditions_.back(); |
| 1378 | it_conditions_.pop_back(); |
| 1379 | } |
| 1380 | |
Ian Rogers | 2bcb4a4 | 2012-11-08 10:39:18 -0800 | [diff] [blame] | 1381 | os << StringPrintf("%p: %08x\t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1382 | return 4; |
Brian Carlstrom | 1895ea3 | 2013-07-18 13:28:37 -0700 | [diff] [blame] | 1383 | } // NOLINT(readability/fn_size) |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1384 | |
| 1385 | size_t DisassemblerArm::DumpThumb16(std::ostream& os, const uint8_t* instr_ptr) { |
| 1386 | uint16_t instr = ReadU16(instr_ptr); |
| 1387 | bool is_32bit = ((instr & 0xF000) == 0xF000) || ((instr & 0xF800) == 0xE800); |
| 1388 | if (is_32bit) { |
| 1389 | return DumpThumb32(os, instr_ptr); |
| 1390 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1391 | std::ostringstream opcode; |
| 1392 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1393 | uint16_t opcode1 = instr >> 10; |
| 1394 | if (opcode1 < 0x10) { |
| 1395 | // shift (immediate), add, subtract, move, and compare |
| 1396 | uint16_t opcode2 = instr >> 9; |
| 1397 | switch (opcode2) { |
| 1398 | case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: |
| 1399 | case 0x8: case 0x9: case 0xA: case 0xB: { |
Sebastien Hertz | e78500c | 2013-02-19 14:29:52 +0100 | [diff] [blame] | 1400 | // Logical shift left - 00 000xx iii mmm ddd |
| 1401 | // Logical shift right - 00 001xx iii mmm ddd |
| 1402 | // Arithmetic shift right - 00 010xx iii mmm ddd |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1403 | uint16_t imm5 = (instr >> 6) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1404 | ThumbRegister rm(instr, 3); |
Sebastien Hertz | e78500c | 2013-02-19 14:29:52 +0100 | [diff] [blame] | 1405 | ThumbRegister Rd(instr, 0); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1406 | if (opcode2 <= 3) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1407 | opcode << "lsls"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1408 | } else if (opcode2 <= 7) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1409 | opcode << "lsrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1410 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1411 | opcode << "asrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1412 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1413 | args << Rd << ", " << rm << ", #" << imm5; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1414 | break; |
| 1415 | } |
| 1416 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 1417 | // Add register - 00 01100 mmm nnn ddd |
| 1418 | // Sub register - 00 01101 mmm nnn ddd |
| 1419 | // Add 3-bit immediate - 00 01110 iii nnn ddd |
| 1420 | // Sub 3-bit immediate - 00 01111 iii nnn ddd |
| 1421 | uint16_t imm3_or_Rm = (instr >> 6) & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1422 | ThumbRegister Rn(instr, 3); |
| 1423 | ThumbRegister Rd(instr, 0); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1424 | if ((opcode2 & 2) != 0 && imm3_or_Rm == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1425 | opcode << "mov"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1426 | } else { |
| 1427 | if ((opcode2 & 1) == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1428 | opcode << "adds"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1429 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1430 | opcode << "subs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1431 | } |
| 1432 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1433 | args << Rd << ", " << Rn; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1434 | if ((opcode2 & 2) == 0) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1435 | ArmRegister Rm(imm3_or_Rm); |
| 1436 | args << ", " << Rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1437 | } else if (imm3_or_Rm != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1438 | args << ", #" << imm3_or_Rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1439 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1440 | break; |
| 1441 | } |
| 1442 | case 0x10: case 0x11: case 0x12: case 0x13: |
| 1443 | case 0x14: case 0x15: case 0x16: case 0x17: |
| 1444 | case 0x18: case 0x19: case 0x1A: case 0x1B: |
| 1445 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: { |
| 1446 | // MOVS Rd, #imm8 - 00100 ddd iiiiiiii |
| 1447 | // CMP Rn, #imm8 - 00101 nnn iiiiiiii |
| 1448 | // ADDS Rn, #imm8 - 00110 nnn iiiiiiii |
| 1449 | // SUBS Rn, #imm8 - 00111 nnn iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1450 | ThumbRegister Rn(instr, 8); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1451 | uint16_t imm8 = instr & 0xFF; |
| 1452 | switch (opcode2 >> 2) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1453 | case 4: opcode << "movs"; break; |
| 1454 | case 5: opcode << "cmp"; break; |
| 1455 | case 6: opcode << "adds"; break; |
| 1456 | case 7: opcode << "subs"; break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1457 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1458 | args << Rn << ", #" << imm8; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1459 | break; |
| 1460 | } |
| 1461 | default: |
| 1462 | break; |
| 1463 | } |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 1464 | } else if (opcode1 == 0x10) { |
| 1465 | // Data-processing |
| 1466 | uint16_t opcode2 = (instr >> 6) & 0xF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1467 | ThumbRegister rm(instr, 3); |
| 1468 | ThumbRegister rdn(instr, 0); |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 1469 | opcode << kThumbDataProcessingOperations[opcode2]; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1470 | args << rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1471 | } else if (opcode1 == 0x11) { |
| 1472 | // Special data instructions and branch and exchange |
| 1473 | uint16_t opcode2 = (instr >> 6) & 0x0F; |
| 1474 | switch (opcode2) { |
| 1475 | case 0x0: case 0x1: case 0x2: case 0x3: { |
| 1476 | // Add low registers - 010001 0000 xxxxxx |
| 1477 | // Add high registers - 010001 0001/001x xxxxxx |
| 1478 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1479 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1480 | uint16_t Rdn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1481 | ArmRegister DN_Rdn((DN << 3) | Rdn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1482 | opcode << "add"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1483 | args << DN_Rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1484 | break; |
| 1485 | } |
| 1486 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 1487 | // Move low registers - 010001 1000 xxxxxx |
| 1488 | // Move high registers - 010001 1001/101x xxxxxx |
| 1489 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1490 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1491 | uint16_t Rdn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1492 | ArmRegister DN_Rdn((DN << 3) | Rdn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1493 | opcode << "mov"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1494 | args << DN_Rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1495 | break; |
| 1496 | } |
| 1497 | case 0x5: case 0x6: case 0x7: { |
| 1498 | // Compare high registers - 010001 0101/011x xxxxxx |
| 1499 | uint16_t N = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1500 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1501 | uint16_t Rn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1502 | ArmRegister N_Rn((N << 3) | Rn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1503 | opcode << "cmp"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1504 | args << N_Rn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1505 | break; |
| 1506 | } |
| 1507 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 1508 | // Branch and exchange - 010001 110x xxxxxx |
| 1509 | // Branch with link and exchange - 010001 111x xxxxxx |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1510 | ArmRegister rm(instr, 3); |
| 1511 | opcode << ((opcode2 & 0x2) == 0 ? "bx" : "blx"); |
| 1512 | args << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1513 | break; |
| 1514 | } |
| 1515 | default: |
| 1516 | break; |
| 1517 | } |
jeffhao | eae2691 | 2013-01-28 16:29:54 -0800 | [diff] [blame] | 1518 | } else if (opcode1 == 0x12 || opcode1 == 0x13) { // 01001x |
| 1519 | ThumbRegister Rt(instr, 8); |
| 1520 | uint16_t imm8 = instr & 0xFF; |
| 1521 | opcode << "ldr"; |
| 1522 | args << Rt << ", [pc, #" << (imm8 << 2) << "]"; |
Ian Rogers | d83bc36 | 2012-09-07 17:43:13 -0700 | [diff] [blame] | 1523 | } else if ((opcode1 >= 0x14 && opcode1 <= 0x17) || // 0101xx |
| 1524 | (opcode1 >= 0x18 && opcode1 <= 0x1f) || // 011xxx |
| 1525 | (opcode1 >= 0x20 && opcode1 <= 0x27)) { // 100xxx |
| 1526 | // Load/store single data item |
| 1527 | uint16_t opA = (instr >> 12) & 0xF; |
| 1528 | if (opA == 0x5) { |
| 1529 | uint16_t opB = (instr >> 9) & 0x7; |
| 1530 | ThumbRegister Rm(instr, 6); |
| 1531 | ThumbRegister Rn(instr, 3); |
| 1532 | ThumbRegister Rt(instr, 0); |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame] | 1533 | switch (opB) { |
Ian Rogers | d83bc36 | 2012-09-07 17:43:13 -0700 | [diff] [blame] | 1534 | case 0: opcode << "str"; break; |
| 1535 | case 1: opcode << "strh"; break; |
| 1536 | case 2: opcode << "strb"; break; |
| 1537 | case 3: opcode << "ldrsb"; break; |
| 1538 | case 4: opcode << "ldr"; break; |
| 1539 | case 5: opcode << "ldrh"; break; |
| 1540 | case 6: opcode << "ldrb"; break; |
| 1541 | case 7: opcode << "ldrsh"; break; |
| 1542 | } |
| 1543 | args << Rt << ", [" << Rn << ", " << Rm << "]"; |
| 1544 | } else if (opA == 9) { |
| 1545 | uint16_t opB = (instr >> 11) & 1; |
| 1546 | ThumbRegister Rt(instr, 8); |
| 1547 | uint16_t imm8 = instr & 0xFF; |
| 1548 | opcode << (opB == 0 ? "str" : "ldr"); |
Ian Rogers | 137e88f | 2012-10-08 17:46:47 -0700 | [diff] [blame] | 1549 | args << Rt << ", [sp, #" << (imm8 << 2) << "]"; |
Ian Rogers | d83bc36 | 2012-09-07 17:43:13 -0700 | [diff] [blame] | 1550 | } else { |
| 1551 | uint16_t imm5 = (instr >> 6) & 0x1F; |
| 1552 | uint16_t opB = (instr >> 11) & 1; |
| 1553 | ThumbRegister Rn(instr, 3); |
| 1554 | ThumbRegister Rt(instr, 0); |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame] | 1555 | switch (opA) { |
Ian Rogers | d83bc36 | 2012-09-07 17:43:13 -0700 | [diff] [blame] | 1556 | case 6: |
| 1557 | imm5 <<= 2; |
| 1558 | opcode << (opB == 0 ? "str" : "ldr"); |
| 1559 | break; |
| 1560 | case 7: |
| 1561 | imm5 <<= 0; |
| 1562 | opcode << (opB == 0 ? "strb" : "ldrb"); |
| 1563 | break; |
| 1564 | case 8: |
| 1565 | imm5 <<= 1; |
| 1566 | opcode << (opB == 0 ? "strh" : "ldrh"); |
| 1567 | break; |
| 1568 | } |
| 1569 | args << Rt << ", [" << Rn << ", #" << imm5 << "]"; |
| 1570 | } |
jeffhao | eae2691 | 2013-01-28 16:29:54 -0800 | [diff] [blame] | 1571 | } else if (opcode1 >= 0x34 && opcode1 <= 0x37) { // 1101xx |
Ian Rogers | 7761cb6 | 2013-06-17 14:10:46 -0700 | [diff] [blame] | 1572 | int8_t imm8 = instr & 0xFF; |
jeffhao | eae2691 | 2013-01-28 16:29:54 -0800 | [diff] [blame] | 1573 | uint32_t cond = (instr >> 8) & 0xF; |
| 1574 | opcode << "b"; |
| 1575 | DumpCond(opcode, cond); |
| 1576 | DumpBranchTarget(args, instr_ptr + 4, (imm8 << 1)); |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 1577 | } else if ((instr & 0xF800) == 0xA800) { |
| 1578 | // Generate SP-relative address |
| 1579 | ThumbRegister rd(instr, 8); |
| 1580 | int imm8 = instr & 0xFF; |
| 1581 | opcode << "add"; |
| 1582 | args << rd << ", sp, #" << (imm8 << 2); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1583 | } else if ((instr & 0xF000) == 0xB000) { |
| 1584 | // Miscellaneous 16-bit instructions |
| 1585 | uint16_t opcode2 = (instr >> 5) & 0x7F; |
| 1586 | switch (opcode2) { |
| 1587 | case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: { |
| 1588 | // Add immediate to SP - 1011 00000 ii iiiii |
| 1589 | // Subtract immediate from SP - 1011 00001 ii iiiii |
| 1590 | int imm7 = instr & 0x7F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1591 | opcode << ((opcode2 & 4) == 0 ? "add" : "sub"); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1592 | args << "sp, sp, #" << (imm7 << 2); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1593 | break; |
| 1594 | } |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1595 | case 0x08: case 0x09: case 0x0A: case 0x0B: // 0001xxx |
Ian Rogers | ebbc577 | 2012-04-11 17:00:08 -0700 | [diff] [blame] | 1596 | case 0x0C: case 0x0D: case 0x0E: case 0x0F: |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame] | 1597 | case 0x18: case 0x19: case 0x1A: case 0x1B: // 0011xxx |
| 1598 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: |
Ian Rogers | ebbc577 | 2012-04-11 17:00:08 -0700 | [diff] [blame] | 1599 | case 0x48: case 0x49: case 0x4A: case 0x4B: // 1001xxx |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame] | 1600 | case 0x4C: case 0x4D: case 0x4E: case 0x4F: |
| 1601 | case 0x58: case 0x59: case 0x5A: case 0x5B: // 1011xxx |
| 1602 | case 0x5C: case 0x5D: case 0x5E: case 0x5F: { |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1603 | // CBNZ, CBZ |
| 1604 | uint16_t op = (instr >> 11) & 1; |
| 1605 | uint16_t i = (instr >> 9) & 1; |
| 1606 | uint16_t imm5 = (instr >> 3) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1607 | ThumbRegister Rn(instr, 0); |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1608 | opcode << (op != 0 ? "cbnz" : "cbz"); |
Ian Rogers | 828a07f | 2013-06-18 22:27:34 -0700 | [diff] [blame] | 1609 | uint32_t imm32 = (i << 6) | (imm5 << 1); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1610 | args << Rn << ", "; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1611 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
| 1612 | break; |
| 1613 | } |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 1614 | case 0x50: case 0x51: // 101000x |
| 1615 | case 0x52: case 0x53: // 101001x |
| 1616 | case 0x56: case 0x57: { // 101011x |
| 1617 | uint16_t op = (instr >> 6) & 3; |
| 1618 | opcode << kThumbReverseOperations[op]; |
| 1619 | ThumbRegister Rm(instr, 3); |
| 1620 | ThumbRegister Rd(instr, 0); |
| 1621 | args << Rd << ", " << Rm; |
| 1622 | break; |
| 1623 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1624 | case 0x78: case 0x79: case 0x7A: case 0x7B: // 1111xxx |
| 1625 | case 0x7C: case 0x7D: case 0x7E: case 0x7F: { |
| 1626 | // If-Then, and hints |
| 1627 | uint16_t opA = (instr >> 4) & 0xF; |
| 1628 | uint16_t opB = instr & 0xF; |
| 1629 | if (opB == 0) { |
| 1630 | switch (opA) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1631 | case 0: opcode << "nop"; break; |
| 1632 | case 1: opcode << "yield"; break; |
| 1633 | case 2: opcode << "wfe"; break; |
| 1634 | case 3: opcode << "sev"; break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1635 | default: break; |
| 1636 | } |
| 1637 | } else { |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame] | 1638 | uint32_t first_cond = opA; |
| 1639 | uint32_t mask = opB; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1640 | opcode << "it"; |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame] | 1641 | |
| 1642 | // Flesh out the base "it" opcode with the specific collection of 't's and 'e's, |
| 1643 | // and store up the actual condition codes we'll want to add to the next few opcodes. |
| 1644 | size_t count = 3 - CTZ(mask); |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1645 | it_conditions_.resize(count + 2); // Plus the implicit 't', plus the "" for the IT itself. |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame] | 1646 | for (size_t i = 0; i < count; ++i) { |
| 1647 | bool positive_cond = ((first_cond & 1) != 0); |
| 1648 | bool positive_mask = ((mask & (1 << (3 - i))) != 0); |
| 1649 | if (positive_mask == positive_cond) { |
| 1650 | opcode << 't'; |
| 1651 | it_conditions_[i] = kConditionCodeNames[first_cond]; |
| 1652 | } else { |
| 1653 | opcode << 'e'; |
| 1654 | it_conditions_[i] = kConditionCodeNames[first_cond ^ 1]; |
| 1655 | } |
| 1656 | } |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1657 | it_conditions_[count] = kConditionCodeNames[first_cond]; // The implicit 't'. |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame] | 1658 | |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1659 | it_conditions_[count + 1] = ""; // No condition code for the IT itself... |
| 1660 | DumpCond(args, first_cond); // ...because it's considered an argument. |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1661 | } |
| 1662 | break; |
| 1663 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1664 | default: |
| 1665 | break; |
| 1666 | } |
| 1667 | } else if (((instr & 0xF000) == 0x5000) || ((instr & 0xE000) == 0x6000) || |
| 1668 | ((instr & 0xE000) == 0x8000)) { |
| 1669 | // Load/store single data item |
| 1670 | uint16_t opA = instr >> 12; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1671 | // uint16_t opB = (instr >> 9) & 7; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1672 | switch (opA) { |
| 1673 | case 0x6: { |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 1674 | // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt |
| 1675 | // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1676 | uint16_t imm5 = (instr >> 6) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1677 | ThumbRegister Rn(instr, 3); |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 1678 | ThumbRegister Rt(instr, 0); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1679 | opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); |
| 1680 | args << Rt << ", [" << Rn << ", #" << (imm5 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1681 | break; |
| 1682 | } |
| 1683 | case 0x9: { |
| 1684 | // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii |
| 1685 | // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii |
| 1686 | uint16_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1687 | ThumbRegister Rt(instr, 8); |
| 1688 | opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); |
| 1689 | args << Rt << ", [sp, #" << (imm8 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1690 | break; |
| 1691 | } |
| 1692 | default: |
| 1693 | break; |
| 1694 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1695 | } else if (opcode1 == 0x38 || opcode1 == 0x39) { |
| 1696 | uint16_t imm11 = instr & 0x7FFF; |
| 1697 | int32_t imm32 = imm11 << 1; |
| 1698 | imm32 = (imm32 << 20) >> 20; // sign extend 12 bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1699 | opcode << "b"; |
| 1700 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1701 | } |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame] | 1702 | |
| 1703 | // Apply any IT-block conditions to the opcode if necessary. |
| 1704 | if (!it_conditions_.empty()) { |
| 1705 | opcode << it_conditions_.back(); |
| 1706 | it_conditions_.pop_back(); |
| 1707 | } |
| 1708 | |
Ian Rogers | 2bcb4a4 | 2012-11-08 10:39:18 -0800 | [diff] [blame] | 1709 | os << StringPrintf("%p: %04x \t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1710 | } |
| 1711 | return 2; |
| 1712 | } |
| 1713 | |
| 1714 | } // namespace arm |
| 1715 | } // namespace art |