Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ |
| 19 | |
| 20 | #include "arm64_lir.h" |
| 21 | #include "dex/compiler_internals.h" |
| 22 | |
| 23 | namespace art { |
| 24 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 25 | class Arm64Mir2Lir : public Mir2Lir { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 26 | public: |
| 27 | Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); |
| 28 | |
| 29 | // Required for target - codegen helpers. |
| 30 | bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
| 31 | RegLocation rl_dest, int lit); |
| 32 | bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
| 33 | LIR* CheckSuspendUsingLoad() OVERRIDE; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 34 | RegStorage LoadHelper(A64ThreadOffset offset); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 35 | LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
| 36 | OpSize size) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 37 | LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 38 | OpSize size) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 39 | LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 40 | RegStorage r_dest, OpSize size) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 41 | LIR* LoadConstantNoClobber(RegStorage r_dest, int value); |
| 42 | LIR* LoadConstantWide(RegStorage r_dest, int64_t value); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 43 | LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, |
| 44 | OpSize size) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 45 | LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 46 | OpSize size) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 47 | LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 48 | RegStorage r_src, OpSize size) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 49 | void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); |
| 50 | |
| 51 | // Required for target - register utilities. |
| 52 | RegStorage AllocTypedTemp(bool fp_hint, int reg_class); |
| 53 | RegStorage AllocTypedTempWide(bool fp_hint, int reg_class); |
| 54 | RegStorage TargetReg(SpecialTargetRegister reg); |
| 55 | RegStorage GetArgMappingToPhysicalReg(int arg_num); |
| 56 | RegLocation GetReturnAlt(); |
| 57 | RegLocation GetReturnWideAlt(); |
| 58 | RegLocation LocCReturn(); |
| 59 | RegLocation LocCReturnDouble(); |
| 60 | RegLocation LocCReturnFloat(); |
| 61 | RegLocation LocCReturnWide(); |
| 62 | uint64_t GetRegMaskCommon(RegStorage reg); |
| 63 | void AdjustSpillMask(); |
| 64 | void ClobberCallerSave(); |
| 65 | void FreeCallTemps(); |
| 66 | void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); |
| 67 | void LockCallTemps(); |
| 68 | void MarkPreservedSingle(int v_reg, RegStorage reg); |
| 69 | void MarkPreservedDouble(int v_reg, RegStorage reg); |
| 70 | void CompilerInitializeRegAlloc(); |
| 71 | RegStorage AllocPreservedDouble(int s_reg); |
| 72 | |
| 73 | // Required for target - miscellaneous. |
| 74 | void AssembleLIR(); |
| 75 | uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset); |
| 76 | int AssignInsnOffsets(); |
| 77 | void AssignOffsets(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 78 | uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 79 | void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix); |
| 80 | void SetupTargetResourceMasks(LIR* lir, uint64_t flags); |
| 81 | const char* GetTargetInstFmt(int opcode); |
| 82 | const char* GetTargetInstName(int opcode); |
| 83 | std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); |
| 84 | uint64_t GetPCUseDefEncoding(); |
| 85 | uint64_t GetTargetInstFlags(int opcode); |
| 86 | int GetInsnSize(LIR* lir); |
| 87 | bool IsUnconditionalBranch(LIR* lir); |
| 88 | |
| 89 | // Required for target - Dalvik-level generators. |
| 90 | void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 91 | RegLocation rl_src1, RegLocation rl_src2); |
| 92 | void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
| 93 | RegLocation rl_index, RegLocation rl_dest, int scale); |
| 94 | void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, |
| 95 | RegLocation rl_src, int scale, bool card_mark); |
| 96 | void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 97 | RegLocation rl_src1, RegLocation rl_shift); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 98 | void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 99 | void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 100 | RegLocation rl_src2); |
| 101 | void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 102 | RegLocation rl_src2); |
| 103 | void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 104 | RegLocation rl_src2); |
| 105 | void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 106 | RegLocation rl_src2); |
| 107 | void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 108 | RegLocation rl_src2); |
| 109 | void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 110 | RegLocation rl_src2); |
| 111 | void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); |
| 112 | bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); |
| 113 | bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); |
| 114 | bool GenInlinedSqrt(CallInfo* info); |
| 115 | bool GenInlinedPeek(CallInfo* info, OpSize size); |
| 116 | bool GenInlinedPoke(CallInfo* info, OpSize size); |
| 117 | void GenNegLong(RegLocation rl_dest, RegLocation rl_src); |
| 118 | void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 119 | RegLocation rl_src2); |
| 120 | void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 121 | RegLocation rl_src2); |
| 122 | void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 123 | RegLocation rl_src2); |
| 124 | RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); |
| 125 | RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); |
| 126 | void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| 127 | void GenDivZeroCheckWide(RegStorage reg); |
| 128 | void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); |
| 129 | void GenExitSequence(); |
| 130 | void GenSpecialExitSequence(); |
| 131 | void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); |
| 132 | void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); |
| 133 | void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); |
| 134 | void GenSelect(BasicBlock* bb, MIR* mir); |
| 135 | void GenMemBarrier(MemBarrierKind barrier_kind); |
| 136 | void GenMonitorEnter(int opt_flags, RegLocation rl_src); |
| 137 | void GenMonitorExit(int opt_flags, RegLocation rl_src); |
| 138 | void GenMoveException(RegLocation rl_dest); |
| 139 | void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
| 140 | int first_bit, int second_bit); |
| 141 | void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); |
| 142 | void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); |
| 143 | void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); |
| 144 | void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 145 | bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); |
| 146 | |
| 147 | uint32_t GenPairWise(uint32_t reg_mask, int* reg1, int* reg2); |
| 148 | void UnSpillCoreRegs(RegStorage base, int offset, uint32_t reg_mask); |
| 149 | void SpillCoreRegs(RegStorage base, int offset, uint32_t reg_mask); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 150 | |
| 151 | // Required for target - single operation generators. |
| 152 | LIR* OpUnconditionalBranch(LIR* target); |
| 153 | LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); |
| 154 | LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); |
| 155 | LIR* OpCondBranch(ConditionCode cc, LIR* target); |
| 156 | LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); |
| 157 | LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); |
| 158 | LIR* OpIT(ConditionCode cond, const char* guide); |
| 159 | void OpEndIT(LIR* it); |
| 160 | LIR* OpMem(OpKind op, RegStorage r_base, int disp); |
| 161 | LIR* OpPcRelLoad(RegStorage reg, LIR* target); |
| 162 | LIR* OpReg(OpKind op, RegStorage r_dest_src); |
| 163 | void OpRegCopy(RegStorage r_dest, RegStorage r_src); |
| 164 | LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 165 | LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value, bool is_wide); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 166 | LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); |
| 167 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); |
| 168 | LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); |
| 169 | LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); |
| 170 | LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); |
| 171 | LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); |
| 172 | LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); |
| 173 | LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); |
| 174 | LIR* OpTestSuspend(LIR* target); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 175 | LIR* OpThreadMem(OpKind op, A64ThreadOffset thread_offset); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 176 | LIR* OpVldm(RegStorage r_base, int count); |
| 177 | LIR* OpVstm(RegStorage r_base, int count); |
| 178 | void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); |
| 179 | void OpRegCopyWide(RegStorage dest, RegStorage src); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 180 | void OpTlsCmp(A64ThreadOffset offset, int val); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 181 | |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 182 | LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 183 | LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 184 | LIR* OpRegRegRegShift(OpKind op, int r_dest, int r_src1, int r_src2, int shift, |
| 185 | bool is_wide = false); |
| 186 | LIR* OpRegRegShift(OpKind op, int r_dest_src1, int r_src2, int shift, bool is_wide = false); |
| 187 | static const ArmEncodingMap EncodingMap[kA64Last]; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 188 | int EncodeShift(int code, int amount); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 189 | int EncodeExtend(int extend_type, int amount); |
| 190 | bool IsExtendEncoding(int encoded_value); |
| 191 | int EncodeLogicalImmediate(bool is_wide, uint64_t value); |
| 192 | uint64_t DecodeLogicalImmediate(bool is_wide, int value); |
| 193 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 194 | ArmConditionCode ArmConditionEncoding(ConditionCode code); |
| 195 | bool InexpensiveConstantInt(int32_t value); |
| 196 | bool InexpensiveConstantFloat(int32_t value); |
| 197 | bool InexpensiveConstantLong(int64_t value); |
| 198 | bool InexpensiveConstantDouble(int64_t value); |
| 199 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 200 | void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); |
| 201 | int LoadArgRegs(CallInfo* info, int call_state, |
| 202 | NextCallInsn next_call_insn, |
| 203 | const MethodReference& target_method, |
| 204 | uint32_t vtable_idx, |
| 205 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
| 206 | bool skip_this); |
| 207 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 208 | private: |
| 209 | void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val, |
| 210 | ConditionCode ccode); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 211 | LIR* LoadFPConstantValue(int r_dest, int32_t value); |
| 212 | LIR* LoadFPConstantValueWide(int r_dest, int64_t value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 213 | void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); |
| 214 | void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); |
| 215 | void AssignDataOffsets(); |
| 216 | RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 217 | bool is_div, bool check_zero); |
| 218 | RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 219 | }; |
| 220 | |
| 221 | } // namespace art |
| 222 | |
| 223 | #endif // ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ |