1. b5860fb Register promotion support for 64-bit targets by buzbee · 10 years ago
  2. 6f9dbb8 Merge "ART: Quick compiler: More size checks, add TargetReg variants" by Andreas Gampe · 10 years ago
  3. 4b537a8 ART: Quick compiler: More size checks, add TargetReg variants by Andreas Gampe · 10 years ago
  4. baa7c88 AArch64: Rename A64_/A32_ register prefix to x/w. by Zheng Xu · 10 years ago
  5. 903989d AArch64: Fix OpRegRegImm64 add/sub for large negative imm. by Vladimir Marko · 10 years ago
  6. a64d728 Merge "AArch64: implement easy division and reminder." by Bill Buzbee · 10 years ago
  7. 3c12c51 Revert "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter"" by Andreas Gampe · 10 years ago
  8. de68676 Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter" by Andreas Gampe · 10 years ago
  9. 2689fba ART: Split out more cases of Load/StoreRef, volatile as parameter by Andreas Gampe · 10 years ago
  10. c61b3c9 AArch64: implement easy division and reminder. by Matteo Franchin · 10 years ago
  11. 47b31aa ART: Start implementation of OpRegRegRegExtend for ARM64 by Andreas Gampe · 10 years ago
  12. f987927 ART: Reserve 8B for float literals on ARM64 by Andreas Gampe · 10 years ago
  13. 9f975bf ART: Change rrr add and sub for ARM64 by Andreas Gampe · 10 years ago
  14. c41e6dc AArch64: improve 64-bit immediates loads. by Matteo Franchin · 10 years ago
  15. 33ae558 Arm64 hard-float by buzbee · 10 years ago
  16. 169489b AArch64: Add support for inlined methods by Serban Constantinescu · 10 years ago
  17. e2eb29e AArch64: Enable MOVE_*, some CONST_*, CMP_*. by Zheng Xu · 10 years ago
  18. c0090a4 Merge "Rewrite use/def masks to support 128 bits." by Vladimir Marko · 10 years ago
  19. 8dea81c Rewrite use/def masks to support 128 bits. by Vladimir Marko · 10 years ago
  20. adea0aa Merge "ART: arm64 explicit stack overflow checks" by Bill Buzbee · 10 years ago
  21. f8ec48e ART: arm64 explicit stack overflow checks by Stuart Monteith · 10 years ago
  22. fd2e291 AArch64: fix MarkGCCard, enabling more MIR opcodes. by Matteo Franchin · 10 years ago
  23. 2d41a65 AArch64: Fix kOpLsl, rem-float/double. by Zheng Xu · 10 years ago
  24. 0955f7e AArch64: fixing some assertions. by Matteo Franchin · 10 years ago
  25. ed65c5e AArch64: Enable LONG_* and INT_* opcodes. by Serban Constantinescu · 10 years ago
  26. bc6d197 AArch64: fixes in A64 code generation. by Matteo Franchin · 10 years ago
  27. 2f244e9 ART: Add more ThreadOffset in Mir2Lir and backends by Andreas Gampe · 10 years ago
  28. 674744e Use atomic load/store for volatile IGET/IPUT/SGET/SPUT. by Vladimir Marko · 10 years ago
  29. e45fb9e AArch64: Change arm64 backend to produce A64 code. by Matteo Franchin · 10 years ago
  30. 3bf7c60 Cleanup ARM load/store wide and remove unused param s_reg. by Vladimir Marko · 10 years ago
  31. 455759b Remove LoadBaseDispWide and StoreBaseDispWide. by Vladimir Marko · 10 years ago
  32. 43ec873 AArch64: Added arm64 quick backend as an arm clone. by Matteo Franchin · 10 years ago