WAsm SIMD version of PPMM microkernel
PiperOrigin-RevId: 322944335
diff --git a/test/f32-ppmm-minmax.cc b/test/f32-ppmm-minmax.cc
index f5fdc9b..88766ee 100644
--- a/test/f32-ppmm-minmax.cc
+++ b/test/f32-ppmm-minmax.cc
@@ -2050,6 +2050,642 @@
#endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC
+#if XNN_ARCH_WASMSIMD
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, k_eq_1) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, strided_cn) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .cn_stride(11)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, k_eq_1_strided_a) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .a_stride(3)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, k_eq_1_subtile) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ for (uint32_t n = 1; n <= 8; n++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(n)
+ .k(1)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, k_eq_1_subtile_m) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(8)
+ .k(1)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, k_eq_1_subtile_n) {
+ for (uint32_t n = 1; n <= 8; n++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(n)
+ .k(1)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, k_gt_1) {
+ for (size_t k = 2; k < 10; k++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(k)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, k_gt_1_subtile) {
+ for (size_t k = 2; k < 10; k++) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ for (uint32_t n = 1; n <= 8; n++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(n)
+ .k(k)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, n_gt_8) {
+ for (uint32_t n = 9; n < 16; n++) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(k)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, n_gt_8_strided_cn) {
+ for (uint32_t n = 9; n < 16; n++) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(k)
+ .cn_stride(11)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, n_gt_8_strided_a) {
+ for (uint32_t n = 9; n < 16; n++) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(n)
+ .k(k)
+ .a_stride(7)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, n_gt_8_subtile) {
+ for (uint32_t n = 9; n < 16; n++) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(n)
+ .k(k)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, n_div_8) {
+ for (uint32_t n = 16; n <= 24; n += 8) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(k)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, n_div_8_strided_cn) {
+ for (uint32_t n = 16; n <= 24; n += 8) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(n)
+ .k(k)
+ .cn_stride(11)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, n_div_8_strided_a) {
+ for (uint32_t n = 16; n <= 24; n += 8) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(n)
+ .k(k)
+ .a_stride(7)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, n_div_8_subtile) {
+ for (uint32_t n = 16; n <= 24; n += 8) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(n)
+ .k(k)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, strided_cm_subtile) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ for (uint32_t n = 1; n <= 8; n++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(n)
+ .k(k)
+ .cm_stride(11)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, qmin) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .qmin(128)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, qmax) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .qmax(128)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_ARM, strided_cm) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .cm_stride(11)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm);
+ }
+#endif // XNN_ARCH_WASMSIMD
+
+
+#if XNN_ARCH_WASMSIMD
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, k_eq_1) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, strided_cn) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .cn_stride(11)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, k_eq_1_strided_a) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .a_stride(3)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, k_eq_1_subtile) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ for (uint32_t n = 1; n <= 8; n++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(n)
+ .k(1)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, k_eq_1_subtile_m) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(8)
+ .k(1)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, k_eq_1_subtile_n) {
+ for (uint32_t n = 1; n <= 8; n++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(n)
+ .k(1)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, k_gt_1) {
+ for (size_t k = 2; k < 10; k++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(k)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, k_gt_1_subtile) {
+ for (size_t k = 2; k < 10; k++) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ for (uint32_t n = 1; n <= 8; n++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(n)
+ .k(k)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, n_gt_8) {
+ for (uint32_t n = 9; n < 16; n++) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(k)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, n_gt_8_strided_cn) {
+ for (uint32_t n = 9; n < 16; n++) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(k)
+ .cn_stride(11)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, n_gt_8_strided_a) {
+ for (uint32_t n = 9; n < 16; n++) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(n)
+ .k(k)
+ .a_stride(7)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, n_gt_8_subtile) {
+ for (uint32_t n = 9; n < 16; n++) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(n)
+ .k(k)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, n_div_8) {
+ for (uint32_t n = 16; n <= 24; n += 8) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(k)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, n_div_8_strided_cn) {
+ for (uint32_t n = 16; n <= 24; n += 8) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(n)
+ .k(k)
+ .cn_stride(11)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, n_div_8_strided_a) {
+ for (uint32_t n = 16; n <= 24; n += 8) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(n)
+ .k(k)
+ .a_stride(7)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, n_div_8_subtile) {
+ for (uint32_t n = 16; n <= 24; n += 8) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(n)
+ .k(k)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, strided_cm_subtile) {
+ for (size_t k = 1; k <= 5; k += 2) {
+ for (uint32_t m = 1; m <= 4; m++) {
+ for (uint32_t n = 1; n <= 8; n++) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(m)
+ .n(n)
+ .k(k)
+ .cm_stride(11)
+ .iterations(1)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+ }
+ }
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, qmin) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .qmin(128)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, qmax) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .qmax(128)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+
+ TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_SPLAT_X86, strided_cm) {
+ GemmMicrokernelTester()
+ .mr(4)
+ .nr(8)
+ .kr(1)
+ .sr(1)
+ .m(4)
+ .n(8)
+ .k(1)
+ .cm_stride(11)
+ .Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86);
+ }
+#endif // XNN_ARCH_WASMSIMD
+
+
TEST(F32_PPMM_MINMAX_4X2__SCALAR, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
diff --git a/test/f32-ppmm-minmax.yaml b/test/f32-ppmm-minmax.yaml
index 98da3b2..57207d7 100644
--- a/test/f32-ppmm-minmax.yaml
+++ b/test/f32-ppmm-minmax.yaml
@@ -14,6 +14,10 @@
k-block: 1
- name: xnn_f32_ppmm_minmax_ukernel_4x8__psimd
k-block: 1
+- name: xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_arm
+ k-block: 1
+- name: xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_splat_x86
+ k-block: 1
- name: xnn_f32_ppmm_minmax_ukernel_4x2__scalar
k-block: 1
- name: xnn_f32_ppmm_minmax_ukernel_2x4__scalar