commit 14d3ce8fbce5ebdb9061628c32264e97c311fdd0
author Marat Dukhan <maratek@google.com> Fri Jul 31 16:19:15 2020 -0700
committer XNNPACK Team <xnnpack-github-robot@google.com> Fri Jul 31 16:19:58 2020 -0700
tree c33776a9a5ea1ac180c1d7b34286f496420811fa
parent 733d0be4f4bdc02daba3b676d05825f4d563cb87

Add LD64 suffix in QS8 GEMM/IGEMM microkernels

LD64 denotes that weights are loaded 64 bits at a time and sign-extended to 128
bits

PiperOrigin-RevId: 324305250

BUILD.bazel

diff --git a/BUILD.bazel b/BUILD.bazel
index 88c2245..af62d1c 100644
--- a/BUILD.bazel
+++ b/BUILD.bazel
@@ -1640,12 +1640,12 @@
     "src/qs8-requantization/precise-sse2.c",
     "src/qs8-requantization/fp32-sse2.c",
     "src/qs8-requantization/q31-sse2.c",
-    "src/qs8-gemm/gen/1x4c2-minmax-sse2.c",
-    "src/qs8-gemm/gen/4x4c2-minmax-sse2.c",
-    "src/qs8-gemm/gen/1x4c8-minmax-sse2.c",
-    "src/qs8-gemm/gen/2x4c8-minmax-sse2.c",
-    "src/qs8-igemm/gen/1x4c2-minmax-sse2.c",
-    "src/qs8-igemm/gen/4x4c2-minmax-sse2.c",
+    "src/qs8-gemm/gen/1x4c2-minmax-sse2-ld64.c",
+    "src/qs8-gemm/gen/4x4c2-minmax-sse2-ld64.c",
+    "src/qs8-gemm/gen/1x4c8-minmax-sse2-ld64.c",
+    "src/qs8-gemm/gen/2x4c8-minmax-sse2-ld64.c",
+    "src/qs8-igemm/gen/1x4c2-minmax-sse2-ld64.c",
+    "src/qs8-igemm/gen/4x4c2-minmax-sse2-ld64.c",
     "src/qu8-avgpool/9p8x-minmax-sse2-c8.c",
     "src/qu8-avgpool/9x-minmax-sse2-c8.c",
     "src/qu8-igemm/4x4c2-minmax-sse2.c",
@@ -1680,12 +1680,12 @@
 ]
 
 SSSE3_UKERNELS = [
-    "src/qs8-gemm/gen/1x4c2-minmax-ssse3.c",
-    "src/qs8-gemm/gen/4x4c2-minmax-ssse3.c",
-    "src/qs8-gemm/gen/1x4c8-minmax-ssse3.c",
-    "src/qs8-gemm/gen/2x4c8-minmax-ssse3.c",
-    "src/qs8-igemm/gen/1x4c2-minmax-ssse3.c",
-    "src/qs8-igemm/gen/4x4c2-minmax-ssse3.c",
+    "src/qs8-gemm/gen/1x4c2-minmax-ssse3-ld64.c",
+    "src/qs8-gemm/gen/4x4c2-minmax-ssse3-ld64.c",
+    "src/qs8-gemm/gen/1x4c8-minmax-ssse3-ld64.c",
+    "src/qs8-gemm/gen/2x4c8-minmax-ssse3-ld64.c",
+    "src/qs8-igemm/gen/1x4c2-minmax-ssse3-ld64.c",
+    "src/qs8-igemm/gen/4x4c2-minmax-ssse3-ld64.c",
     "src/qs8-requantization/precise-ssse3.c",
     "src/qs8-requantization/q31-ssse3.c",
     "src/qu8-requantization/precise-ssse3.c",
@@ -1711,12 +1711,12 @@
     "src/f32-vrnd/gen/vrndu-sse41-x8.c",
     "src/f32-vrnd/gen/vrndd-sse41-x4.c",
     "src/f32-vrnd/gen/vrndd-sse41-x8.c",
-    "src/qs8-gemm/gen/1x4c2-minmax-sse41.c",
-    "src/qs8-gemm/gen/4x4c2-minmax-sse41.c",
-    "src/qs8-gemm/gen/1x4c8-minmax-sse41.c",
-    "src/qs8-gemm/gen/2x4c8-minmax-sse41.c",
-    "src/qs8-igemm/gen/1x4c2-minmax-sse41.c",
-    "src/qs8-igemm/gen/4x4c2-minmax-sse41.c",
+    "src/qs8-gemm/gen/1x4c2-minmax-sse41-ld64.c",
+    "src/qs8-gemm/gen/4x4c2-minmax-sse41-ld64.c",
+    "src/qs8-gemm/gen/1x4c8-minmax-sse41-ld64.c",
+    "src/qs8-gemm/gen/2x4c8-minmax-sse41-ld64.c",
+    "src/qs8-igemm/gen/1x4c2-minmax-sse41-ld64.c",
+    "src/qs8-igemm/gen/4x4c2-minmax-sse41-ld64.c",
     "src/qs8-requantization/fp32-sse4.c",
     "src/qs8-requantization/precise-sse4.c",
     "src/qs8-requantization/q31-sse4.c",