commit 2894e99467622d7a3a0b2f76b4c4ba03f9d8cf09
author Marat Dukhan <maratek@google.com> Thu Dec 30 08:29:48 2021 -0800
committer XNNPACK Team <xnnpack-github-robot@google.com> Thu Dec 30 08:30:42 2021 -0800
tree e9857e82256e482e0ae380929ffff38b29ed178b
parent b7c1b71b8fa351d7af67650075bb71ceca43bf17

Refactor F32 VLRELU microkernels

Split F32 VLRELU parameter initialization by ISA

PiperOrigin-RevId: 418962853

src/f32-vlrelu/wasmsimd-bitselect.c.in

diff --git a/src/f32-vlrelu/wasmsimd-bitselect.c.in b/src/f32-vlrelu/wasmsimd-bitselect.c.in
index 674ca0e..f8bbfd4 100644
--- a/src/f32-vlrelu/wasmsimd-bitselect.c.in
+++ b/src/f32-vlrelu/wasmsimd-bitselect.c.in
@@ -23,7 +23,7 @@
   assert(n != 0);
   assert(n % sizeof(float) == 0);
 
-  const v128_t vslope = wasm_v128_load32_splat(&params->scalar.slope);
+  const v128_t vslope = wasm_v128_load64_splat(params->wasmsimd.slope);
   $if BATCH_TILE > 4:
     for (; n >= ${BATCH_TILE} * sizeof(float); n -= ${BATCH_TILE} * sizeof(float)) {
       const v128_t vx${ABC[0:4]} = wasm_v128_load(x);