commit 484bfc4cc2df7124aa23cd44360684a0cea9f37f
author Frank Barchard <fbarchard@google.com> Wed Feb 05 11:31:56 2020 -0800
committer XNNPACK Team <xnnpack-github-robot@google.com> Wed Feb 05 11:32:26 2020 -0800
tree a026c209ccd863ffe94bc7a1af3ea16189fb3789
parent fbbb40e479d1d4d347d510da235e484e85d5b153

Kryo, Cortex-A77 and Exynos-M5 use IGEMM 4x8 with no prefetch.

PiperOrigin-RevId: 293413265

src/init.c

diff --git a/src/init.c b/src/init.c
index 18d9320..43d0abf 100644
--- a/src/init.c
+++ b/src/init.c
@@ -365,16 +365,6 @@
   #ifndef XNN_NO_F32_OPERATORS
     #if XNN_ENABLE_ASSEMBLY
       switch (cpuinfo_get_core(0)->uarch) {
-        case cpuinfo_uarch_kryo:
-          xnn_params.f32.gemm = (struct gemm_parameters) {
-            .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_4x8__aarch64_neonfma_cortex_a57,
-            .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x8__aarch64_neonfma_cortex_a75,
-            .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__aarch64_neonfma_cortex_a75,
-            .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__aarch64_neonfma_cortex_a75,
-            .mr = 4,
-            .nr = 8,
-          };
-          break;
         case cpuinfo_uarch_cortex_a57:
           xnn_params.f32.gemm = (struct gemm_parameters) {
             .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_6x8__aarch64_neonfma_cortex_a57,
@@ -395,16 +385,6 @@
             .nr = 8,
           };
           break;
-        case cpuinfo_uarch_cortex_a77:
-        case cpuinfo_uarch_exynos_m5:
-          xnn_params.f32.gemm = (struct gemm_parameters) {
-            .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_4x8__aarch64_neonfma_cortex_a57,
-            .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x8__aarch64_neonfma_cortex_a75,
-            .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__aarch64_neonfma_cortex_a75,
-            .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__aarch64_neonfma_cortex_a75,
-            .mr = 4,
-            .nr = 8,
-          };
         case cpuinfo_uarch_cortex_a75:
         case cpuinfo_uarch_cortex_a76:
         case cpuinfo_uarch_exynos_m3:
@@ -453,11 +433,14 @@
           };
           break;
         default:
+        case cpuinfo_uarch_cortex_a77:
+        case cpuinfo_uarch_exynos_m5:
+        case cpuinfo_uarch_kryo:
           xnn_params.f32.gemm = (struct gemm_parameters) {
             .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_4x8__aarch64_neonfma_cortex_a57,
-            .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x8__aarch64_neonfma_cortex_a75,
-            .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__aarch64_neonfma_cortex_a75,
-            .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__aarch64_neonfma_cortex_a75,
+            .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x8__aarch64_neonfma_cortex_a57,
+            .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__aarch64_neonfma_cortex_a57,
+            .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__aarch64_neonfma_cortex_a57,
             .mr = 4,
             .nr = 8,
           };