commit 4a7b70f2262b95276ee291b5455ae50bf1874e4f
author Marat Dukhan <maratek@google.com> Mon Aug 02 18:18:10 2021 -0700
committer XNNPACK Team <xnnpack-github-robot@google.com> Mon Aug 02 18:19:05 2021 -0700
tree e52d929c45bc58594088e3560a5b052023182f6c
parent 79993410e8170efddd914a47d91e5544633c6a3c

QS8/QU8 VMUL[C] microkernels in NEON implementation

PiperOrigin-RevId: 388349072

BUILD.bazel

diff --git a/BUILD.bazel b/BUILD.bazel
index 4ed7cc0..a7069fa 100644
--- a/BUILD.bazel
+++ b/BUILD.bazel
@@ -2509,6 +2509,12 @@
     "src/qs8-vaddc/gen/minmax-neon-ld64-x32.c",
     "src/qs8-vaddc/gen/minmax-neon-ld128-x16.c",
     "src/qs8-vaddc/gen/minmax-neon-ld128-x32.c",
+    "src/qs8-vmul/gen/minmax-fp32-neon-ld64-x8.c",
+    "src/qs8-vmul/gen/minmax-fp32-neon-ld64-x16.c",
+    "src/qs8-vmul/gen/minmax-fp32-neon-ld128-x16.c",
+    "src/qs8-vmulc/gen/minmax-fp32-neon-ld64-x8.c",
+    "src/qs8-vmulc/gen/minmax-fp32-neon-ld64-x16.c",
+    "src/qs8-vmulc/gen/minmax-fp32-neon-ld128-x16.c",
     "src/qu8-avgpool/9p8x-minmax-neon-c8.c",
     "src/qu8-avgpool/9x-minmax-neon-c8.c",
     "src/qu8-dwconv/gen/up8x9-minmax-fp32-neon-mul16.c",
@@ -2546,6 +2552,12 @@
     "src/qu8-vaddc/gen/minmax-neon-ld64-x8.c",
     "src/qu8-vaddc/gen/minmax-neon-ld64-x16.c",
     "src/qu8-vaddc/gen/minmax-neon-ld128-x16.c",
+    "src/qu8-vmul/gen/minmax-fp32-neon-ld64-x8.c",
+    "src/qu8-vmul/gen/minmax-fp32-neon-ld64-x16.c",
+    "src/qu8-vmul/gen/minmax-fp32-neon-ld128-x16.c",
+    "src/qu8-vmulc/gen/minmax-fp32-neon-ld64-x8.c",
+    "src/qu8-vmulc/gen/minmax-fp32-neon-ld64-x16.c",
+    "src/qu8-vmulc/gen/minmax-fp32-neon-ld128-x16.c",
     "src/u8-maxpool/9p8x-minmax-neon-c16.c",
     "src/u8-rmax/neon.c",
     "src/u8-vclamp/neon-x64.c",
@@ -3006,6 +3018,12 @@
     "src/qs8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
     "src/qs8-igemm/gen/2x8c8-minmax-fp32-neonv8-mlal-padal.c",
     "src/qs8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
+    "src/qs8-vmul/gen/minmax-fp32-neonv8-ld64-x8.c",
+    "src/qs8-vmul/gen/minmax-fp32-neonv8-ld64-x16.c",
+    "src/qs8-vmul/gen/minmax-fp32-neonv8-ld128-x16.c",
+    "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld64-x8.c",
+    "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld64-x16.c",
+    "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld128-x16.c",
     "src/qu8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul16.c",
     "src/qu8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul16.c",
     "src/qu8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul16.c",
@@ -3018,6 +3036,12 @@
     "src/qu8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
     "src/qu8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
     "src/qu8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
+    "src/qu8-vmul/gen/minmax-fp32-neonv8-ld64-x8.c",
+    "src/qu8-vmul/gen/minmax-fp32-neonv8-ld64-x16.c",
+    "src/qu8-vmul/gen/minmax-fp32-neonv8-ld128-x16.c",
+    "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld64-x8.c",
+    "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld64-x16.c",
+    "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld128-x16.c",
 ]
 
 PROD_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS = [