Minimally support WebAssembly Relaxed SIMD builds
Relaxed SIMD currently use the same code paths and microkernels as WAsm SIMD128
PiperOrigin-RevId: 417704438
diff --git a/test/f16-f32-vcvt.cc b/test/f16-f32-vcvt.cc
index 964c759..5db03d1 100644
--- a/test/f16-f32-vcvt.cc
+++ b/test/f16-f32-vcvt.cc
@@ -1423,7 +1423,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F16_F32_VCVT__WASMSIMD_INT16_X8, batch_eq_8) {
VCvtMicrokernelTester()
.batch_size(8)
@@ -1453,10 +1453,10 @@
.Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x8);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F16_F32_VCVT__WASMSIMD_INT16_X16, batch_eq_16) {
VCvtMicrokernelTester()
.batch_size(16)
@@ -1486,10 +1486,10 @@
.Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x16);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F16_F32_VCVT__WASMSIMD_INT16_X24, batch_eq_24) {
VCvtMicrokernelTester()
.batch_size(24)
@@ -1519,10 +1519,10 @@
.Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x24);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F16_F32_VCVT__WASMSIMD_INT16_X32, batch_eq_32) {
VCvtMicrokernelTester()
.batch_size(32)
@@ -1552,10 +1552,10 @@
.Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int16_x32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F16_F32_VCVT__WASMSIMD_INT32_X8, batch_eq_8) {
VCvtMicrokernelTester()
.batch_size(8)
@@ -1585,10 +1585,10 @@
.Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x8);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F16_F32_VCVT__WASMSIMD_INT32_X16, batch_eq_16) {
VCvtMicrokernelTester()
.batch_size(16)
@@ -1618,10 +1618,10 @@
.Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x16);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F16_F32_VCVT__WASMSIMD_INT32_X24, batch_eq_24) {
VCvtMicrokernelTester()
.batch_size(24)
@@ -1651,10 +1651,10 @@
.Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x24);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F16_F32_VCVT__WASMSIMD_INT32_X32, batch_eq_32) {
VCvtMicrokernelTester()
.batch_size(32)
@@ -1684,7 +1684,7 @@
.Test(xnn_f16_f32_vcvt_ukernel__wasmsimd_int32_x32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F16_F32_VCVT__SCALAR_FLOAT_X1, batch_eq_1) {
diff --git a/test/f32-argmaxpool.cc b/test/f32-argmaxpool.cc
index f0f667b..791a525 100644
--- a/test/f32-argmaxpool.cc
+++ b/test/f32-argmaxpool.cc
@@ -547,7 +547,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_ARGMAXPOOL_4X__WASMSIMD_C4, channels_eq_4_unipass_fulltile) {
ArgMaxPoolMicrokernelTester()
.pooling_elements(4)
@@ -789,7 +789,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_ARGMAXPOOL_4X__SCALAR_C1, channels_eq_1_unipass_fulltile) {
@@ -1472,7 +1472,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_ARGMAXPOOL_9X__WASMSIMD_C4, channels_eq_4_unipass_fulltile) {
ArgMaxPoolMicrokernelTester()
.pooling_elements(9)
@@ -1714,7 +1714,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_ARGMAXPOOL_9X__SCALAR_C1, channels_eq_1_unipass_fulltile) {
@@ -2607,7 +2607,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_ARGMAXPOOL_9P8X__WASMSIMD_C4, channels_eq_4_twopass_fulltile) {
ArgMaxPoolMicrokernelTester()
@@ -2946,7 +2946,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
diff --git a/test/f32-avgpool-minmax.cc b/test/f32-avgpool-minmax.cc
index 33c9aa7..91d278b 100644
--- a/test/f32-avgpool-minmax.cc
+++ b/test/f32-avgpool-minmax.cc
@@ -1647,7 +1647,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_AVGPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_twopass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(17)
@@ -2398,10 +2398,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_AVGPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_twopass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(17)
@@ -3152,10 +3152,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_AVGPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_twopass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(17)
@@ -3576,7 +3576,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_AVGPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_fulltile) {
@@ -5070,7 +5070,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_AVGPOOL_MINMAX_9X__WASMSIMD_ARM_C4, channels_eq_4_unipass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(9)
@@ -5563,10 +5563,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_AVGPOOL_MINMAX_9X__WASMSIMD_X86_C4, channels_eq_4_unipass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(9)
@@ -6059,10 +6059,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_AVGPOOL_MINMAX_9X__WASM_C1, channels_eq_1_unipass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(9)
@@ -6359,7 +6359,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_AVGPOOL_MINMAX_9X__SCALAR_C1, channels_eq_1_unipass_fulltile) {
diff --git a/test/f32-dwconv-minmax.cc b/test/f32-dwconv-minmax.cc
index d24e142..30b7846 100644
--- a/test/f32-dwconv-minmax.cc
+++ b/test/f32-dwconv-minmax.cc
@@ -21233,7 +21233,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X25__WASMSIMD_ARM, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -21401,10 +21401,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X25__WASMSIMD_ARM_ACC2, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -21572,10 +21572,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X25__WASMSIMD_ARM, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -21743,10 +21743,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X25__WASMSIMD_ARM_ACC2, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -21914,10 +21914,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X25__WASMSIMD_X86, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -22085,10 +22085,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X25__WASMSIMD_X86_ACC2, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -22256,10 +22256,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X25__WASMSIMD_X86, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -22427,10 +22427,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X25__WASMSIMD_X86_ACC2, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -22598,10 +22598,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X9__WASMSIMD_ARM, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -22769,10 +22769,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X9__WASMSIMD_ARM_ACC2, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -22940,10 +22940,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X9__WASMSIMD_ARM, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -23111,10 +23111,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X9__WASMSIMD_ARM_ACC2, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -23282,10 +23282,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X9__WASMSIMD_X86, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -23453,10 +23453,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X9__WASMSIMD_X86_ACC2, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -23624,10 +23624,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X9__WASMSIMD_X86, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -23795,10 +23795,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X9__WASMSIMD_X86_ACC2, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -23966,10 +23966,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X3__WASMSIMD_ARM, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -24137,10 +24137,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X3__WASMSIMD_ARM_ACC2, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -24308,10 +24308,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X4__WASMSIMD_ARM, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -24479,10 +24479,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X4__WASMSIMD_ARM_ACC2, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -24650,10 +24650,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X3__WASMSIMD_ARM, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -24821,10 +24821,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X3__WASMSIMD_ARM_ACC2, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -24992,10 +24992,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X4__WASMSIMD_ARM, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -25163,10 +25163,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X4__WASMSIMD_ARM_ACC2, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -25334,10 +25334,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X3__WASMSIMD_X86, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -25505,10 +25505,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X3__WASMSIMD_X86_ACC2, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -25676,10 +25676,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X4__WASMSIMD_X86, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -25847,10 +25847,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP4X4__WASMSIMD_X86_ACC2, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -26018,10 +26018,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X3__WASMSIMD_X86, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -26189,10 +26189,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X3__WASMSIMD_X86_ACC2, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -26360,10 +26360,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X4__WASMSIMD_X86, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -26531,10 +26531,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP8X4__WASMSIMD_X86_ACC2, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -26702,10 +26702,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP1X3__WASM, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -26831,10 +26831,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP1X3__WASM_ACC2, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -26960,10 +26960,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP1X4__WASM, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -27089,10 +27089,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -27218,10 +27218,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP2X3__WASM, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -27389,10 +27389,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP2X3__WASM_ACC2, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -27560,10 +27560,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP2X4__WASM, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -27731,10 +27731,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -27902,10 +27902,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP1X9__WASM, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -28031,10 +28031,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -28160,10 +28160,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP2X9__WASM, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -28331,10 +28331,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -28502,10 +28502,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP1X25__WASM, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -28631,10 +28631,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -28760,10 +28760,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP2X25__WASM, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -28931,10 +28931,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -29102,7 +29102,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_MINMAX_UP1X3__SCALAR, c_eq_1) {
diff --git a/test/f32-dwconv.cc b/test/f32-dwconv.cc
index becfbc0..cdc5d91 100644
--- a/test/f32-dwconv.cc
+++ b/test/f32-dwconv.cc
@@ -20,7 +20,7 @@
#include "dwconv-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP4X25__WASMSIMD, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -120,10 +120,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP8X25__WASMSIMD, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -223,10 +223,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP4X9__WASMSIMD, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -326,10 +326,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP8X9__WASMSIMD, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -429,10 +429,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP4X3__WASMSIMD, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -532,10 +532,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP4X4__WASMSIMD, c_eq_4) {
DWConvMicrokernelTester()
.cr(4)
@@ -635,10 +635,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP8X3__WASMSIMD, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -738,10 +738,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP8X4__WASMSIMD, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -841,10 +841,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP1X3__WASM, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -924,10 +924,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP1X3__WASM_ACC2, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -1007,10 +1007,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP1X4__WASM, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -1090,10 +1090,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP1X4__WASM_ACC2, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -1173,10 +1173,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP2X3__WASM, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -1276,10 +1276,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP2X3__WASM_ACC2, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -1379,10 +1379,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP2X4__WASM, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -1482,10 +1482,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP2X4__WASM_ACC2, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -1585,10 +1585,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP1X9__WASM, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -1668,10 +1668,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP1X9__WASM_ACC2, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -1751,10 +1751,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP2X9__WASM, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -1854,10 +1854,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP2X9__WASM_ACC2, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -1957,10 +1957,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP1X25__WASM, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -2040,10 +2040,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP1X25__WASM_ACC2, c_eq_1) {
DWConvMicrokernelTester()
.cr(1)
@@ -2123,10 +2123,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP2X25__WASM, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -2226,10 +2226,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP2X25__WASM_ACC2, c_eq_2) {
DWConvMicrokernelTester()
.cr(2)
@@ -2329,7 +2329,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV_UP1X3__SCALAR, c_eq_1) {
diff --git a/test/f32-dwconv2d-chw.cc b/test/f32-dwconv2d-chw.cc
index 80b3e82..2047580 100644
--- a/test/f32-dwconv2d-chw.cc
+++ b/test/f32-dwconv2d-chw.cc
@@ -16731,7 +16731,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_SPLAT_1X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -16811,10 +16811,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_SPLAT_2X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -16930,10 +16930,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_SPLAT_3X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -17049,10 +17049,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_SPLAT_4X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -17168,10 +17168,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_SPLAT_5X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -17287,10 +17287,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_SPLAT_6X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -17406,10 +17406,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_SPLAT_1X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -17489,10 +17489,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_SPLAT_1X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -17572,10 +17572,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_SPLAT_1X4_ACC4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -17655,10 +17655,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_SPLAT_2X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -17774,10 +17774,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_SPLAT_1X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -17857,10 +17857,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_SPLAT_2X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -17976,10 +17976,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_SPLAT_3X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -18095,10 +18095,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_SPLAT_4X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -18214,10 +18214,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_SPLAT_5X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -18333,10 +18333,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_SPLAT_6X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -18452,10 +18452,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_SPLAT_1X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -18535,10 +18535,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_SPLAT_1X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -18618,10 +18618,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_SPLAT_1X4_ACC4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -18701,10 +18701,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_SPLAT_2X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -18820,10 +18820,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_LOADSPLAT_1X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -18903,10 +18903,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_LOADSPLAT_2X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -19022,10 +19022,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_LOADSPLAT_3X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -19141,10 +19141,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_LOADSPLAT_4X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -19260,10 +19260,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_LOADSPLAT_5X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -19379,10 +19379,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_LOADSPLAT_6X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -19498,10 +19498,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_LOADSPLAT_1X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -19581,10 +19581,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_LOADSPLAT_1X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -19664,10 +19664,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_LOADSPLAT_1X4_ACC4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -19747,10 +19747,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_ARM_LOADSPLAT_2X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -19866,10 +19866,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_LOADSPLAT_1X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -19949,10 +19949,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_LOADSPLAT_2X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -20068,10 +20068,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_LOADSPLAT_3X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -20187,10 +20187,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_LOADSPLAT_4X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -20306,10 +20306,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_LOADSPLAT_5X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -20425,10 +20425,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_LOADSPLAT_6X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -20544,10 +20544,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_LOADSPLAT_1X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -20627,10 +20627,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_LOADSPLAT_1X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -20710,10 +20710,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_LOADSPLAT_1X4_ACC4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -20793,10 +20793,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__WASMSIMD_X86_LOADSPLAT_2X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -20912,10 +20912,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_LOADSPLAT_1X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -21033,10 +21033,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_LOADSPLAT_2X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -21190,10 +21190,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_LOADSPLAT_3X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -21347,10 +21347,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_LOADSPLAT_4X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -21504,10 +21504,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_LOADSPLAT_1X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -21625,10 +21625,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_LOADSPLAT_1X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -21746,10 +21746,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_LOADSPLAT_1X4_ACC4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -21867,10 +21867,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_LOADSPLAT_2X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -22024,10 +22024,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_LOADSPLAT_1X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -22145,10 +22145,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_LOADSPLAT_2X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -22302,10 +22302,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_LOADSPLAT_3X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -22459,10 +22459,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_LOADSPLAT_4X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -22616,10 +22616,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_LOADSPLAT_1X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -22737,10 +22737,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_LOADSPLAT_1X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -22858,10 +22858,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_LOADSPLAT_1X4_ACC4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -22979,10 +22979,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_LOADSPLAT_2X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -23136,10 +23136,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_SPLAT_1X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -23257,10 +23257,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_SPLAT_2X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -23414,10 +23414,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_SPLAT_3X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -23571,10 +23571,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_SPLAT_4X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -23728,10 +23728,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_SPLAT_1X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -23849,10 +23849,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_SPLAT_1X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -23970,10 +23970,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_SPLAT_1X4_ACC4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -24091,10 +24091,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_ARM_SPLAT_2X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -24248,10 +24248,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_SPLAT_1X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -24369,10 +24369,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_SPLAT_2X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -24526,10 +24526,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_SPLAT_3X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -24683,10 +24683,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_SPLAT_4X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -24840,10 +24840,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_SPLAT_1X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -24961,10 +24961,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_SPLAT_1X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -25082,10 +25082,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_SPLAT_1X4_ACC4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -25203,10 +25203,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3S2P1__WASMSIMD_X86_SPLAT_2X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -25360,10 +25360,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_1X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -25443,10 +25443,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_1X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -25526,10 +25526,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_1X4_ACC4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -25609,10 +25609,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_1X4_ACC5, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -25692,10 +25692,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_1X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -25775,10 +25775,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_2X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -25894,10 +25894,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_2X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -26013,10 +26013,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_2X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -26132,10 +26132,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_3X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -26251,10 +26251,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_3X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -26370,10 +26370,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_4X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -26489,10 +26489,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_4X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -26608,10 +26608,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_LOADSPLAT_5X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -26727,10 +26727,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_1X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -26810,10 +26810,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_1X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -26893,10 +26893,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_1X4_ACC4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -26976,10 +26976,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_1X4_ACC5, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -27059,10 +27059,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_1X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -27142,10 +27142,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_2X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -27261,10 +27261,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_2X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -27380,10 +27380,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_2X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -27499,10 +27499,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_3X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -27618,10 +27618,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_3X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -27737,10 +27737,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_4X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -27856,10 +27856,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_4X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -27975,10 +27975,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_LOADSPLAT_5X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -28094,10 +28094,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_1X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -28177,10 +28177,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_1X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -28260,10 +28260,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_1X4_ACC4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -28343,10 +28343,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_1X4_ACC5, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -28426,10 +28426,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_1X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -28509,10 +28509,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_2X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -28628,10 +28628,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_2X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -28747,10 +28747,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_2X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -28866,10 +28866,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_3X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -28985,10 +28985,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_3X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -29104,10 +29104,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_4X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -29223,10 +29223,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_4X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -29342,10 +29342,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_ARM_SPLAT_5X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -29461,10 +29461,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_1X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -29544,10 +29544,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_1X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -29627,10 +29627,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_1X4_ACC4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -29710,10 +29710,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_1X4_ACC5, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -29793,10 +29793,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_1X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -29876,10 +29876,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_2X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -29995,10 +29995,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_2X4_ACC3, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -30114,10 +30114,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_2X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -30233,10 +30233,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_3X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -30352,10 +30352,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_3X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -30471,10 +30471,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_4X4_ACC2, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -30590,10 +30590,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_4X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -30709,10 +30709,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5P2__WASMSIMD_X86_SPLAT_5X4, output_width_eq_4) {
DWConv2DMicrokernelTester()
.input_width(4)
@@ -30828,10 +30828,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_LOADSPLAT_1X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -30949,10 +30949,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_LOADSPLAT_2X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -31106,10 +31106,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_LOADSPLAT_3X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -31263,10 +31263,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_LOADSPLAT_1X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -31384,10 +31384,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_LOADSPLAT_1X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -31505,10 +31505,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_LOADSPLAT_1X4_ACC4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -31626,10 +31626,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_LOADSPLAT_1X4_ACC5, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -31747,10 +31747,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_LOADSPLAT_2X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -31904,10 +31904,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_LOADSPLAT_2X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -32061,10 +32061,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_LOADSPLAT_3X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -32218,10 +32218,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_LOADSPLAT_1X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -32339,10 +32339,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_LOADSPLAT_2X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -32496,10 +32496,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_LOADSPLAT_3X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -32653,10 +32653,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_LOADSPLAT_1X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -32774,10 +32774,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_LOADSPLAT_1X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -32895,10 +32895,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_LOADSPLAT_1X4_ACC4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -33016,10 +33016,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_LOADSPLAT_1X4_ACC5, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -33137,10 +33137,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_LOADSPLAT_2X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -33294,10 +33294,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_LOADSPLAT_2X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -33451,10 +33451,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_LOADSPLAT_3X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -33608,10 +33608,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_SPLAT_1X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -33729,10 +33729,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_SPLAT_2X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -33886,10 +33886,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_SPLAT_3X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -34043,10 +34043,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_SPLAT_1X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -34164,10 +34164,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_SPLAT_1X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -34285,10 +34285,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_SPLAT_1X4_ACC4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -34406,10 +34406,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_SPLAT_1X4_ACC5, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -34527,10 +34527,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_SPLAT_2X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -34684,10 +34684,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_SPLAT_2X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -34841,10 +34841,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_ARM_SPLAT_3X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -34998,10 +34998,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_SPLAT_1X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -35119,10 +35119,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_SPLAT_2X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -35276,10 +35276,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_SPLAT_3X4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -35433,10 +35433,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_SPLAT_1X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -35554,10 +35554,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_SPLAT_1X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -35675,10 +35675,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_SPLAT_1X4_ACC4, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -35796,10 +35796,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_SPLAT_1X4_ACC5, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -35917,10 +35917,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_SPLAT_2X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -36074,10 +36074,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_SPLAT_2X4_ACC3, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -36231,10 +36231,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_5X5S2P2__WASMSIMD_X86_SPLAT_3X4_ACC2, output_width_eq_4) {
for (size_t input_width = 7; input_width < 9; input_width++) {
DWConv2DMicrokernelTester()
@@ -36388,7 +36388,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_DWCONV2D_CHW_3X3P1__SCALAR_1X1, output_width_eq_1) {
diff --git a/test/f32-f16-vcvt.cc b/test/f32-f16-vcvt.cc
index 2a16160..6933cbf 100644
--- a/test/f32-f16-vcvt.cc
+++ b/test/f32-f16-vcvt.cc
@@ -831,7 +831,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_F16_VCVT__WASMSIMD_X8, batch_eq_8) {
VCvtMicrokernelTester()
.batch_size(8)
@@ -861,10 +861,10 @@
.Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x8);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_F16_VCVT__WASMSIMD_X16, batch_eq_16) {
VCvtMicrokernelTester()
.batch_size(16)
@@ -894,10 +894,10 @@
.Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x16);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_F16_VCVT__WASMSIMD_X24, batch_eq_24) {
VCvtMicrokernelTester()
.batch_size(24)
@@ -927,10 +927,10 @@
.Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x24);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_F16_VCVT__WASMSIMD_X32, batch_eq_32) {
VCvtMicrokernelTester()
.batch_size(32)
@@ -960,7 +960,7 @@
.Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_F16_VCVT__SCALAR_BITCAST_X1, batch_eq_1) {
diff --git a/test/f32-gavgpool-minmax.cc b/test/f32-gavgpool-minmax.cc
index 23eb9eb..f8a0ddb 100644
--- a/test/f32-gavgpool-minmax.cc
+++ b/test/f32-gavgpool-minmax.cc
@@ -550,7 +550,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GAVGPOOL_MINMAX_7P7X__WASMSIMD_ARM_C4, channels_eq_4_2pass_fulltile) {
GAvgPoolMicrokernelTester()
.rows(14)
@@ -788,10 +788,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GAVGPOOL_MINMAX_7P7X__WASMSIMD_X86_C4, channels_eq_4_2pass_fulltile) {
GAvgPoolMicrokernelTester()
.rows(14)
@@ -1029,10 +1029,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GAVGPOOL_MINMAX_7P7X__WASM_C1, channels_eq_1_2pass_fulltile) {
GAvgPoolMicrokernelTester()
.rows(14)
@@ -1207,7 +1207,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GAVGPOOL_MINMAX_7P7X__SCALAR_C1, channels_eq_1_2pass_fulltile) {
@@ -1702,7 +1702,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GAVGPOOL_MINMAX_7X__WASMSIMD_ARM_C4, channels_eq_4_fulltile) {
GAvgPoolMicrokernelTester()
.rows(7)
@@ -1842,10 +1842,10 @@
.Test(xnn_f32_gavgpool_minmax_ukernel_7x__wasmsimd_arm_c4);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GAVGPOOL_MINMAX_7X__WASMSIMD_X86_C4, channels_eq_4_fulltile) {
GAvgPoolMicrokernelTester()
.rows(7)
@@ -1985,10 +1985,10 @@
.Test(xnn_f32_gavgpool_minmax_ukernel_7x__wasmsimd_x86_c4);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GAVGPOOL_MINMAX_7X__WASM_C1, channels_eq_1_fulltile) {
GAvgPoolMicrokernelTester()
.rows(7)
@@ -2068,7 +2068,7 @@
.Test(xnn_f32_gavgpool_minmax_ukernel_7x__wasm_c1);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GAVGPOOL_MINMAX_7X__SCALAR_C1, channels_eq_1_fulltile) {
diff --git a/test/f32-gemm-minmax.cc b/test/f32-gemm-minmax.cc
index b37e32b..8f48f4c 100644
--- a/test/f32-gemm-minmax.cc
+++ b/test/f32-gemm-minmax.cc
@@ -45817,7 +45817,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_1X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -46147,10 +46147,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_1x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_3X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(3)
@@ -46480,10 +46480,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_3x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_4X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -46813,10 +46813,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_4x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_5X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(5)
@@ -47146,10 +47146,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_5x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_6X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(6)
@@ -47479,10 +47479,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_6x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_1X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -47812,10 +47812,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_1x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_3X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(3)
@@ -48145,10 +48145,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_3x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_4X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -48478,10 +48478,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_4x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_5X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(5)
@@ -48811,10 +48811,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_5x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_6X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(6)
@@ -49144,10 +49144,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_6x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_1X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -49573,10 +49573,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_1x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_3X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -50002,10 +50002,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_3x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_4X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -50431,10 +50431,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_4x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_5X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -50860,10 +50860,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_5x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_6X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -51289,10 +51289,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_6x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_1X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -51718,10 +51718,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_1x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_3X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -52147,10 +52147,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_3x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_4X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -52576,10 +52576,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_4x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_5X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -53005,10 +53005,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_5x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_6X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -53434,10 +53434,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_6x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_1X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -53863,10 +53863,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_1x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_3X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -54292,10 +54292,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_3x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_4X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -54721,10 +54721,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_4x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_5X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -55150,10 +55150,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_5x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_6X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -55579,10 +55579,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_6x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_1X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -56008,10 +56008,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_1x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_3X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -56437,10 +56437,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_3x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_4X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -56866,10 +56866,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_4x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_5X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -57295,10 +57295,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_5x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_6X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -57724,10 +57724,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_minmax_ukernel_6x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_4X2C4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -58153,10 +58153,10 @@
.cm_stride(5)
.Test(xnn_f32_gemm_minmax_ukernel_4x2c4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_4X2C4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -58582,10 +58582,10 @@
.cm_stride(5)
.Test(xnn_f32_gemm_minmax_ukernel_4x2c4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_1X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -58915,10 +58915,10 @@
.cm_stride(7)
.Test(xnn_f32_gemm_minmax_ukernel_1x4__wasm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_2X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(2)
@@ -59248,10 +59248,10 @@
.cm_stride(7)
.Test(xnn_f32_gemm_minmax_ukernel_2x4__wasm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_4X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -59581,10 +59581,10 @@
.cm_stride(7)
.Test(xnn_f32_gemm_minmax_ukernel_4x4__wasm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_4X2__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -59914,7 +59914,7 @@
.cm_stride(5)
.Test(xnn_f32_gemm_minmax_ukernel_4x2__wasm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_MINMAX_1X4__SCALAR, k_eq_1) {
diff --git a/test/f32-gemm-relu.cc b/test/f32-gemm-relu.cc
index ca6bc29..85320a7 100644
--- a/test/f32-gemm-relu.cc
+++ b/test/f32-gemm-relu.cc
@@ -22,7 +22,7 @@
#include "gemm-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_RELU_1X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -422,10 +422,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_relu_ukernel_1x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_RELU_4X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -825,10 +825,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_relu_ukernel_4x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_RELU_5X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -1228,10 +1228,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_relu_ukernel_5x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_RELU_4X2C4__WASMSIMD, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -1631,10 +1631,10 @@
.cm_stride(5)
.Test(xnn_f32_gemm_relu_ukernel_4x2c4__wasmsimd);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_RELU_1X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -1938,10 +1938,10 @@
.cm_stride(7)
.Test(xnn_f32_gemm_relu_ukernel_1x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_RELU_2X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(2)
@@ -2245,10 +2245,10 @@
.cm_stride(7)
.Test(xnn_f32_gemm_relu_ukernel_2x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_RELU_4X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -2552,10 +2552,10 @@
.cm_stride(7)
.Test(xnn_f32_gemm_relu_ukernel_4x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_RELU_4X2__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -2859,7 +2859,7 @@
.cm_stride(5)
.Test(xnn_f32_gemm_relu_ukernel_4x2__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_RELU_1X4__SCALAR, k_eq_1) {
diff --git a/test/f32-gemm.cc b/test/f32-gemm.cc
index 8754f7e..2b43087 100644
--- a/test/f32-gemm.cc
+++ b/test/f32-gemm.cc
@@ -425,7 +425,7 @@
#endif // XNN_ARCH_ARM && XNN_ENABLE_ASSEMBLY
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_1X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -825,10 +825,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_ukernel_1x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_4X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -1228,10 +1228,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_ukernel_4x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_5X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -1631,10 +1631,10 @@
.cm_stride(11)
.Test(xnn_f32_gemm_ukernel_5x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_4X2C4__WASMSIMD, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -2034,10 +2034,10 @@
.cm_stride(5)
.Test(xnn_f32_gemm_ukernel_4x2c4__wasmsimd);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_1X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -2341,10 +2341,10 @@
.cm_stride(7)
.Test(xnn_f32_gemm_ukernel_1x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_2X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(2)
@@ -2648,10 +2648,10 @@
.cm_stride(7)
.Test(xnn_f32_gemm_ukernel_2x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_4X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -2955,10 +2955,10 @@
.cm_stride(7)
.Test(xnn_f32_gemm_ukernel_4x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_4X2__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -3262,7 +3262,7 @@
.cm_stride(5)
.Test(xnn_f32_gemm_ukernel_4x2__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMM_1X4__SCALAR, k_eq_1) {
diff --git a/test/f32-gemminc-minmax.cc b/test/f32-gemminc-minmax.cc
index f4dcb54..b0e9af1 100644
--- a/test/f32-gemminc-minmax.cc
+++ b/test/f32-gemminc-minmax.cc
@@ -41014,7 +41014,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_1X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -41344,10 +41344,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_1x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_3X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(3)
@@ -41677,10 +41677,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_3x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_4X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -42010,10 +42010,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_4x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_5X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(5)
@@ -42343,10 +42343,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_5x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_6X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(6)
@@ -42676,10 +42676,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_6x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_1X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -43009,10 +43009,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_1x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_3X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(3)
@@ -43342,10 +43342,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_3x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_4X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -43675,10 +43675,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_4x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_5X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(5)
@@ -44008,10 +44008,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_5x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_6X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(6)
@@ -44341,10 +44341,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_6x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_1X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -44770,10 +44770,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_1x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_3X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -45199,10 +45199,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_3x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_4X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -45628,10 +45628,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_4x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_5X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -46057,10 +46057,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_5x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_6X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -46486,10 +46486,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_6x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_1X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -46915,10 +46915,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_1x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_3X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -47344,10 +47344,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_3x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_4X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -47773,10 +47773,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_4x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_5X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -48202,10 +48202,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_5x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_6X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -48631,10 +48631,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_6x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_1X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -49060,10 +49060,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_1x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_3X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -49489,10 +49489,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_3x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_4X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -49918,10 +49918,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_4x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_5X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -50347,10 +50347,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_5x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_6X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -50776,10 +50776,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_6x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_1X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -51205,10 +51205,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_1x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_3X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -51634,10 +51634,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_3x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_4X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -52063,10 +52063,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_4x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_5X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -52492,10 +52492,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_5x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_6X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -52921,10 +52921,10 @@
.cm_stride(11)
.Test(xnn_f32_gemminc_minmax_ukernel_6x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_1X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -53254,10 +53254,10 @@
.cm_stride(7)
.Test(xnn_f32_gemminc_minmax_ukernel_1x4__wasm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_2X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(2)
@@ -53587,10 +53587,10 @@
.cm_stride(7)
.Test(xnn_f32_gemminc_minmax_ukernel_2x4__wasm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_4X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -53920,7 +53920,7 @@
.cm_stride(7)
.Test(xnn_f32_gemminc_minmax_ukernel_4x4__wasm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_GEMMINC_MINMAX_1X4__SCALAR, k_eq_1) {
diff --git a/test/f32-ibilinear-chw.cc b/test/f32-ibilinear-chw.cc
index 73f753f..052ce24 100644
--- a/test/f32-ibilinear-chw.cc
+++ b/test/f32-ibilinear-chw.cc
@@ -236,7 +236,7 @@
}
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IBILINEAR_CHW__WASMSIMD_P4, pixels_eq_4) {
IBilinearMicrokernelTester()
.pixels(4)
@@ -314,10 +314,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IBILINEAR_CHW__WASMSIMD_P8, pixels_eq_8) {
IBilinearMicrokernelTester()
.pixels(8)
@@ -395,7 +395,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
#if XNN_ARCH_ARM || XNN_ARCH_ARM64
diff --git a/test/f32-ibilinear.cc b/test/f32-ibilinear.cc
index 6b96f8e..1d54f2d 100644
--- a/test/f32-ibilinear.cc
+++ b/test/f32-ibilinear.cc
@@ -680,7 +680,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IBILINEAR__WASMSIMD_C4, channels_eq_4) {
IBilinearMicrokernelTester()
.pixels(1)
@@ -749,10 +749,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IBILINEAR__WASMSIMD_C8, channels_eq_8) {
IBilinearMicrokernelTester()
.pixels(1)
@@ -821,4 +821,4 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
diff --git a/test/f32-igemm-minmax.cc b/test/f32-igemm-minmax.cc
index 02dfb8c..4448319 100644
--- a/test/f32-igemm-minmax.cc
+++ b/test/f32-igemm-minmax.cc
@@ -47284,7 +47284,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_1X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -47656,10 +47656,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_1x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_3X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(3)
@@ -48031,10 +48031,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_3x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_4X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -48406,10 +48406,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_4x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_5X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(5)
@@ -48781,10 +48781,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_5x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_6X8__WASMSIMD_ARM_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(6)
@@ -49156,10 +49156,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_6x8__wasmsimd_arm_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_1X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -49531,10 +49531,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_1x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_3X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(3)
@@ -49906,10 +49906,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_3x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_4X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -50281,10 +50281,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_4x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_5X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(5)
@@ -50656,10 +50656,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_5x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_6X8__WASMSIMD_X86_LOADSPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(6)
@@ -51031,10 +51031,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_6x8__wasmsimd_x86_loadsplat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_1X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -51472,10 +51472,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_1x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_3X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -51913,10 +51913,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_3x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_4X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -52354,10 +52354,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_4x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_5X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -52795,10 +52795,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_5x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_6X8__WASMSIMD_ARM_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -53236,10 +53236,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_6x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_1X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -53677,10 +53677,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_1x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_3X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -54118,10 +54118,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_3x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_4X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -54559,10 +54559,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_4x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_5X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -55000,10 +55000,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_5x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_6X8__WASMSIMD_X86_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -55441,10 +55441,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_6x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_1X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -55882,10 +55882,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_1x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_3X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -56323,10 +56323,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_3x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_4X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -56764,10 +56764,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_4x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_5X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -57205,10 +57205,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_5x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_6X8S4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -57646,10 +57646,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_6x8s4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_1X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -58087,10 +58087,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_1x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_3X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(3)
@@ -58528,10 +58528,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_3x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_4X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -58969,10 +58969,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_4x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_5X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -59410,10 +59410,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_5x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_6X8S4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(6)
@@ -59851,10 +59851,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_minmax_ukernel_6x8s4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_4X2C4__WASMSIMD_ARM, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -60292,10 +60292,10 @@
.cm_stride(5)
.Test(xnn_f32_igemm_minmax_ukernel_4x2c4__wasmsimd_arm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_4X2C4__WASMSIMD_X86, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -60733,10 +60733,10 @@
.cm_stride(5)
.Test(xnn_f32_igemm_minmax_ukernel_4x2c4__wasmsimd_x86, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_1X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -61108,10 +61108,10 @@
.cm_stride(7)
.Test(xnn_f32_igemm_minmax_ukernel_1x4__wasm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_2X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(2)
@@ -61483,10 +61483,10 @@
.cm_stride(7)
.Test(xnn_f32_igemm_minmax_ukernel_2x4__wasm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_4X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -61858,10 +61858,10 @@
.cm_stride(7)
.Test(xnn_f32_igemm_minmax_ukernel_4x4__wasm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_4X2__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -62233,7 +62233,7 @@
.cm_stride(5)
.Test(xnn_f32_igemm_minmax_ukernel_4x2__wasm, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_MINMAX_1X4__SCALAR, k_eq_1) {
diff --git a/test/f32-igemm-relu.cc b/test/f32-igemm-relu.cc
index 0eb9647..c5547b5 100644
--- a/test/f32-igemm-relu.cc
+++ b/test/f32-igemm-relu.cc
@@ -22,7 +22,7 @@
#include "gemm-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_RELU_1X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -434,10 +434,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_relu_ukernel_1x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_RELU_4X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -849,10 +849,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_relu_ukernel_4x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_RELU_5X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -1264,10 +1264,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_relu_ukernel_5x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_RELU_4X2C4__WASMSIMD, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -1679,10 +1679,10 @@
.cm_stride(5)
.Test(xnn_f32_igemm_relu_ukernel_4x2c4__wasmsimd);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_RELU_1X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -2028,10 +2028,10 @@
.cm_stride(7)
.Test(xnn_f32_igemm_relu_ukernel_1x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_RELU_2X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(2)
@@ -2377,10 +2377,10 @@
.cm_stride(7)
.Test(xnn_f32_igemm_relu_ukernel_2x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_RELU_4X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -2726,10 +2726,10 @@
.cm_stride(7)
.Test(xnn_f32_igemm_relu_ukernel_4x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_RELU_4X2__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -3075,7 +3075,7 @@
.cm_stride(5)
.Test(xnn_f32_igemm_relu_ukernel_4x2__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_RELU_1X4__SCALAR, k_eq_1) {
diff --git a/test/f32-igemm.cc b/test/f32-igemm.cc
index 7376243..1aecd9a 100644
--- a/test/f32-igemm.cc
+++ b/test/f32-igemm.cc
@@ -22,7 +22,7 @@
#include "gemm-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(1)
@@ -434,10 +434,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -849,10 +849,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, k_eq_4) {
GemmMicrokernelTester()
.mr(5)
@@ -1264,10 +1264,10 @@
.cm_stride(11)
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_4X2C4__WASMSIMD, k_eq_4) {
GemmMicrokernelTester()
.mr(4)
@@ -1679,10 +1679,10 @@
.cm_stride(5)
.Test(xnn_f32_igemm_ukernel_4x2c4__wasmsimd);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_1X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(1)
@@ -2028,10 +2028,10 @@
.cm_stride(7)
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_2X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(2)
@@ -2377,10 +2377,10 @@
.cm_stride(7)
.Test(xnn_f32_igemm_ukernel_2x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_4X4__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -2726,10 +2726,10 @@
.cm_stride(7)
.Test(xnn_f32_igemm_ukernel_4x4__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_4X2__WASM, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -3075,7 +3075,7 @@
.cm_stride(5)
.Test(xnn_f32_igemm_ukernel_4x2__wasm);
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_IGEMM_1X4__SCALAR, k_eq_1) {
diff --git a/test/f32-maxpool-minmax.cc b/test/f32-maxpool-minmax.cc
index 44e632f..e9f945c 100644
--- a/test/f32-maxpool-minmax.cc
+++ b/test/f32-maxpool-minmax.cc
@@ -1794,7 +1794,7 @@
#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_unipass_fulltile) {
MaxPoolMicrokernelTester()
.pooling_elements(9)
@@ -2608,10 +2608,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_MAXPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_unipass_fulltile) {
MaxPoolMicrokernelTester()
.pooling_elements(9)
@@ -3425,10 +3425,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_MAXPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_unipass_fulltile) {
MaxPoolMicrokernelTester()
.pooling_elements(9)
@@ -3868,7 +3868,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_fulltile) {
diff --git a/test/f32-pavgpool-minmax.cc b/test/f32-pavgpool-minmax.cc
index 76ca010..65654ac 100644
--- a/test/f32-pavgpool-minmax.cc
+++ b/test/f32-pavgpool-minmax.cc
@@ -1647,7 +1647,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PAVGPOOL_MINMAX_9P8X__WASMSIMD_ARM_C4, channels_eq_4_twopass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(17)
@@ -2398,10 +2398,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PAVGPOOL_MINMAX_9P8X__WASMSIMD_X86_C4, channels_eq_4_twopass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(17)
@@ -3152,10 +3152,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PAVGPOOL_MINMAX_9P8X__WASM_C1, channels_eq_1_twopass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(17)
@@ -3576,7 +3576,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PAVGPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_twopass_fulltile) {
@@ -5070,7 +5070,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PAVGPOOL_MINMAX_9X__WASMSIMD_ARM_C4, channels_eq_4_unipass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(9)
@@ -5563,10 +5563,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PAVGPOOL_MINMAX_9X__WASMSIMD_X86_C4, channels_eq_4_unipass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(9)
@@ -6059,10 +6059,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PAVGPOOL_MINMAX_9X__WASM_C1, channels_eq_1_unipass_fulltile) {
AvgPoolMicrokernelTester()
.pooling_elements(9)
@@ -6359,7 +6359,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PAVGPOOL_MINMAX_9X__SCALAR_C1, channels_eq_1_unipass_fulltile) {
diff --git a/test/f32-ppmm-minmax.cc b/test/f32-ppmm-minmax.cc
index 382b037..11026ab 100644
--- a/test/f32-ppmm-minmax.cc
+++ b/test/f32-ppmm-minmax.cc
@@ -1712,7 +1712,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_ARM_SPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -2027,10 +2027,10 @@
.cm_stride(11)
.Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_arm_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PPMM_MINMAX_4X8__WASMSIMD_X86_SPLAT, k_eq_1) {
GemmMicrokernelTester()
.mr(4)
@@ -2345,7 +2345,7 @@
.cm_stride(11)
.Test(xnn_f32_ppmm_minmax_ukernel_4x8__wasmsimd_x86_splat, xnn_init_f32_minmax_scalar_params);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PPMM_MINMAX_4X2__SCALAR, k_eq_1) {
diff --git a/test/f32-prelu.cc b/test/f32-prelu.cc
index f1a3105..01006bc 100644
--- a/test/f32-prelu.cc
+++ b/test/f32-prelu.cc
@@ -2206,7 +2206,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_BITSELECT_1X4, channels_eq_4) {
PReLUMicrokernelTester()
.rows(1)
@@ -2290,10 +2290,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_BITSELECT_1X8, channels_eq_8) {
PReLUMicrokernelTester()
.rows(1)
@@ -2377,10 +2377,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_BITSELECT_1X16, channels_eq_16) {
PReLUMicrokernelTester()
.rows(1)
@@ -2464,10 +2464,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_BITSELECT_2X4, channels_eq_4) {
PReLUMicrokernelTester()
.rows(2)
@@ -2573,10 +2573,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_BITSELECT_2X8, channels_eq_8) {
PReLUMicrokernelTester()
.rows(2)
@@ -2682,10 +2682,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_BITSELECT_2X16, channels_eq_16) {
PReLUMicrokernelTester()
.rows(2)
@@ -2791,10 +2791,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_BITSELECT_4X4, channels_eq_4) {
PReLUMicrokernelTester()
.rows(4)
@@ -2900,10 +2900,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_BITSELECT_4X8, channels_eq_8) {
PReLUMicrokernelTester()
.rows(4)
@@ -3009,10 +3009,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_BITSELECT_4X16, channels_eq_16) {
PReLUMicrokernelTester()
.rows(4)
@@ -3118,10 +3118,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_MINMAX_1X4, channels_eq_4) {
PReLUMicrokernelTester()
.rows(1)
@@ -3205,10 +3205,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_MINMAX_1X8, channels_eq_8) {
PReLUMicrokernelTester()
.rows(1)
@@ -3292,10 +3292,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_MINMAX_1X16, channels_eq_16) {
PReLUMicrokernelTester()
.rows(1)
@@ -3379,10 +3379,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_MINMAX_2X4, channels_eq_4) {
PReLUMicrokernelTester()
.rows(2)
@@ -3488,10 +3488,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_MINMAX_2X8, channels_eq_8) {
PReLUMicrokernelTester()
.rows(2)
@@ -3597,10 +3597,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_MINMAX_2X16, channels_eq_16) {
PReLUMicrokernelTester()
.rows(2)
@@ -3706,10 +3706,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_MINMAX_4X4, channels_eq_4) {
PReLUMicrokernelTester()
.rows(4)
@@ -3815,10 +3815,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_MINMAX_4X8, channels_eq_8) {
PReLUMicrokernelTester()
.rows(4)
@@ -3924,10 +3924,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASMSIMD_MINMAX_4X16, channels_eq_16) {
PReLUMicrokernelTester()
.rows(4)
@@ -4033,10 +4033,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASM_2X1, channels_eq_1) {
PReLUMicrokernelTester()
.rows(2)
@@ -4124,10 +4124,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__WASM_2X4, channels_eq_4) {
PReLUMicrokernelTester()
.rows(2)
@@ -4233,7 +4233,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_PRELU__SCALAR_2X1, channels_eq_1) {
diff --git a/test/f32-qs8-vcvt.cc b/test/f32-qs8-vcvt.cc
index d50c4f9..c0fb128 100644
--- a/test/f32-qs8-vcvt.cc
+++ b/test/f32-qs8-vcvt.cc
@@ -3461,7 +3461,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASMSIMD_CVT_X8, batch_eq_8) {
VCvtMicrokernelTester()
.batch_size(8)
@@ -3571,10 +3571,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASMSIMD_CVT_X16, batch_eq_16) {
VCvtMicrokernelTester()
.batch_size(16)
@@ -3684,10 +3684,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASMSIMD_CVT_X24, batch_eq_24) {
VCvtMicrokernelTester()
.batch_size(24)
@@ -3797,10 +3797,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASMSIMD_CVT_X32, batch_eq_32) {
VCvtMicrokernelTester()
.batch_size(32)
@@ -3910,10 +3910,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASMSIMD_MAGIC_X8, batch_eq_8) {
VCvtMicrokernelTester()
.batch_size(8)
@@ -4023,10 +4023,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASMSIMD_MAGIC_X16, batch_eq_16) {
VCvtMicrokernelTester()
.batch_size(16)
@@ -4136,10 +4136,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASMSIMD_MAGIC_X24, batch_eq_24) {
VCvtMicrokernelTester()
.batch_size(24)
@@ -4249,10 +4249,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASMSIMD_MAGIC_X32, batch_eq_32) {
VCvtMicrokernelTester()
.batch_size(32)
@@ -4362,10 +4362,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASM_MAGIC_FMINMAX_X1, batch_eq_1) {
VCvtMicrokernelTester()
.batch_size(1)
@@ -4455,10 +4455,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASM_MAGIC_FMINMAX_X2, batch_eq_2) {
VCvtMicrokernelTester()
.batch_size(2)
@@ -4568,10 +4568,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASM_MAGIC_FMINMAX_X3, batch_eq_3) {
VCvtMicrokernelTester()
.batch_size(3)
@@ -4681,10 +4681,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__WASM_MAGIC_FMINMAX_X4, batch_eq_4) {
VCvtMicrokernelTester()
.batch_size(4)
@@ -4794,7 +4794,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QS8_VCVT__SCALAR_MAGIC_FMINMAX_X1, batch_eq_1) {
diff --git a/test/f32-qu8-vcvt.cc b/test/f32-qu8-vcvt.cc
index b64c941..fcdecbf 100644
--- a/test/f32-qu8-vcvt.cc
+++ b/test/f32-qu8-vcvt.cc
@@ -3065,7 +3065,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASMSIMD_CVT_X8, batch_eq_8) {
VCvtMicrokernelTester()
.batch_size(8)
@@ -3179,10 +3179,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASMSIMD_CVT_X16, batch_eq_16) {
VCvtMicrokernelTester()
.batch_size(16)
@@ -3296,10 +3296,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASMSIMD_CVT_X24, batch_eq_24) {
VCvtMicrokernelTester()
.batch_size(24)
@@ -3413,10 +3413,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASMSIMD_CVT_X32, batch_eq_32) {
VCvtMicrokernelTester()
.batch_size(32)
@@ -3530,10 +3530,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASMSIMD_MAGIC_X8, batch_eq_8) {
VCvtMicrokernelTester()
.batch_size(8)
@@ -3647,10 +3647,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASMSIMD_MAGIC_X16, batch_eq_16) {
VCvtMicrokernelTester()
.batch_size(16)
@@ -3764,10 +3764,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASMSIMD_MAGIC_X24, batch_eq_24) {
VCvtMicrokernelTester()
.batch_size(24)
@@ -3881,10 +3881,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASMSIMD_MAGIC_X32, batch_eq_32) {
VCvtMicrokernelTester()
.batch_size(32)
@@ -3998,10 +3998,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASM_MAGIC_FMINMAX_X1, batch_eq_1) {
VCvtMicrokernelTester()
.batch_size(1)
@@ -4095,10 +4095,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASM_MAGIC_FMINMAX_X2, batch_eq_2) {
VCvtMicrokernelTester()
.batch_size(2)
@@ -4212,10 +4212,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASM_MAGIC_FMINMAX_X3, batch_eq_3) {
VCvtMicrokernelTester()
.batch_size(3)
@@ -4329,10 +4329,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__WASM_MAGIC_FMINMAX_X4, batch_eq_4) {
VCvtMicrokernelTester()
.batch_size(4)
@@ -4446,7 +4446,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_QU8_VCVT__SCALAR_MAGIC_FMINMAX_X1, batch_eq_1) {
diff --git a/test/f32-raddstoreexpminusmax.cc b/test/f32-raddstoreexpminusmax.cc
index 0c0788c..14185bb 100644
--- a/test/f32-raddstoreexpminusmax.cc
+++ b/test/f32-raddstoreexpminusmax.cc
@@ -3125,7 +3125,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X4, elements_eq_4) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(4)
@@ -3155,10 +3155,10 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x4);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X8, elements_eq_8) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(8)
@@ -3188,10 +3188,10 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x8);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X8_ACC2, elements_eq_8) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(8)
@@ -3221,10 +3221,10 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x8_acc2);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12, elements_eq_12) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(12)
@@ -3254,10 +3254,10 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12_ACC2, elements_eq_12) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(12)
@@ -3287,10 +3287,10 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12_acc2);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X12_ACC3, elements_eq_12) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(12)
@@ -3320,10 +3320,10 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x12_acc3);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16, elements_eq_16) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(16)
@@ -3353,10 +3353,10 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16_ACC2, elements_eq_16) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(16)
@@ -3386,10 +3386,10 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16_acc2);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X16_ACC4, elements_eq_16) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(16)
@@ -3419,10 +3419,10 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x16_acc4);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20, elements_eq_20) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(20)
@@ -3452,10 +3452,10 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20_ACC2, elements_eq_20) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(20)
@@ -3485,10 +3485,10 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20_acc2);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__WASMSIMD_P5_X20_ACC5, elements_eq_20) {
RAddStoreExpMinusMaxMicrokernelTester()
.elements(20)
@@ -3518,7 +3518,7 @@
.Test(xnn_f32_raddstoreexpminusmax_ukernel__wasmsimd_p5_x20_acc5);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_RADDSTOREEXPMINUSMAX__SCALAR_P5_X1, elements_eq_1) {
diff --git a/test/f32-spmm-minmax.cc b/test/f32-spmm-minmax.cc
index 451b6c3..dc20d88 100644
--- a/test/f32-spmm-minmax.cc
+++ b/test/f32-spmm-minmax.cc
@@ -7971,7 +7971,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_4X1__WASMSIMD_ARM, k_eq_1) {
SpMMMicrokernelTester()
.mr(4)
@@ -8139,10 +8139,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_8X1__WASMSIMD_ARM, k_eq_1) {
SpMMMicrokernelTester()
.mr(8)
@@ -8310,10 +8310,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_16X1__WASMSIMD_ARM, k_eq_1) {
SpMMMicrokernelTester()
.mr(16)
@@ -8481,10 +8481,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_32X1__WASMSIMD_ARM, k_eq_1) {
SpMMMicrokernelTester()
.mr(32)
@@ -8652,10 +8652,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_4X1__WASMSIMD_X86, k_eq_1) {
SpMMMicrokernelTester()
.mr(4)
@@ -8823,10 +8823,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_8X1__WASMSIMD_X86, k_eq_1) {
SpMMMicrokernelTester()
.mr(8)
@@ -8994,10 +8994,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_16X1__WASMSIMD_X86, k_eq_1) {
SpMMMicrokernelTester()
.mr(16)
@@ -9165,10 +9165,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_32X1__WASMSIMD_X86, k_eq_1) {
SpMMMicrokernelTester()
.mr(32)
@@ -9336,10 +9336,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_4X1__WASMSIMD_ARM_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(4)
@@ -9533,10 +9533,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_8X1__WASMSIMD_ARM_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(8)
@@ -9730,10 +9730,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_16X1__WASMSIMD_ARM_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(16)
@@ -9927,10 +9927,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_32X1__WASMSIMD_ARM_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(32)
@@ -10124,10 +10124,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_4X1__WASMSIMD_X86_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(4)
@@ -10321,10 +10321,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_8X1__WASMSIMD_X86_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(8)
@@ -10518,10 +10518,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_16X1__WASMSIMD_X86_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(16)
@@ -10715,10 +10715,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_32X1__WASMSIMD_X86_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(32)
@@ -10912,10 +10912,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_4X1__WASMSIMD_ARM_X4, k_eq_4) {
SpMMMicrokernelTester()
.mr(4)
@@ -11109,10 +11109,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_8X1__WASMSIMD_ARM_X4, k_eq_4) {
SpMMMicrokernelTester()
.mr(8)
@@ -11306,10 +11306,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_16X1__WASMSIMD_ARM_X4, k_eq_4) {
SpMMMicrokernelTester()
.mr(16)
@@ -11503,10 +11503,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_32X1__WASMSIMD_ARM_X4, k_eq_4) {
SpMMMicrokernelTester()
.mr(32)
@@ -11700,10 +11700,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_4X1__WASMSIMD_X86_X4, k_eq_4) {
SpMMMicrokernelTester()
.mr(4)
@@ -11897,10 +11897,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_8X1__WASMSIMD_X86_X4, k_eq_4) {
SpMMMicrokernelTester()
.mr(8)
@@ -12094,10 +12094,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_16X1__WASMSIMD_X86_X4, k_eq_4) {
SpMMMicrokernelTester()
.mr(16)
@@ -12291,10 +12291,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_32X1__WASMSIMD_X86_X4, k_eq_4) {
SpMMMicrokernelTester()
.mr(32)
@@ -12488,10 +12488,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_4X1__WASMSIMD_ARM_PIPELINED, k_eq_1) {
SpMMMicrokernelTester()
.mr(4)
@@ -12659,10 +12659,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_8X1__WASMSIMD_ARM_PIPELINED, k_eq_1) {
SpMMMicrokernelTester()
.mr(8)
@@ -12830,10 +12830,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_16X1__WASMSIMD_ARM_PIPELINED, k_eq_1) {
SpMMMicrokernelTester()
.mr(16)
@@ -13001,10 +13001,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_32X1__WASMSIMD_ARM_PIPELINED, k_eq_1) {
SpMMMicrokernelTester()
.mr(32)
@@ -13172,10 +13172,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_4X1__WASMSIMD_X86_PIPELINED, k_eq_1) {
SpMMMicrokernelTester()
.mr(4)
@@ -13343,10 +13343,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_8X1__WASMSIMD_X86_PIPELINED, k_eq_1) {
SpMMMicrokernelTester()
.mr(8)
@@ -13514,10 +13514,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_16X1__WASMSIMD_X86_PIPELINED, k_eq_1) {
SpMMMicrokernelTester()
.mr(16)
@@ -13685,10 +13685,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_32X1__WASMSIMD_X86_PIPELINED, k_eq_1) {
SpMMMicrokernelTester()
.mr(32)
@@ -13856,10 +13856,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_4X1__WASMSIMD_ARM_PIPELINED_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(4)
@@ -14053,10 +14053,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_8X1__WASMSIMD_ARM_PIPELINED_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(8)
@@ -14250,10 +14250,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_16X1__WASMSIMD_ARM_PIPELINED_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(16)
@@ -14447,10 +14447,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_32X1__WASMSIMD_ARM_PIPELINED_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(32)
@@ -14644,10 +14644,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_4X1__WASMSIMD_X86_PIPELINED_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(4)
@@ -14841,10 +14841,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_8X1__WASMSIMD_X86_PIPELINED_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(8)
@@ -15038,10 +15038,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_16X1__WASMSIMD_X86_PIPELINED_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(16)
@@ -15235,10 +15235,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_32X1__WASMSIMD_X86_PIPELINED_X2, k_eq_2) {
SpMMMicrokernelTester()
.mr(32)
@@ -15432,7 +15432,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_SPMM_MINMAX_1X1__SCALAR, k_eq_1) {
diff --git a/test/f32-vabs.cc b/test/f32-vabs.cc
index 72533bd..f5a7d4a 100644
--- a/test/f32-vabs.cc
+++ b/test/f32-vabs.cc
@@ -393,7 +393,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VABS__WASMSIMD_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -432,10 +432,10 @@
.Test(xnn_f32_vabs_ukernel__wasmsimd_x4, VUnaryMicrokernelTester::OpType::Abs);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VABS__WASMSIMD_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -474,7 +474,7 @@
.Test(xnn_f32_vabs_ukernel__wasmsimd_x8, VUnaryMicrokernelTester::OpType::Abs);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VABS__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vadd-minmax.cc b/test/f32-vadd-minmax.cc
index 542b303..0a5e605 100644
--- a/test/f32-vadd-minmax.cc
+++ b/test/f32-vadd-minmax.cc
@@ -722,7 +722,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_MINMAX__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -798,10 +798,10 @@
.Test(xnn_f32_vadd_minmax_ukernel__wasmsimd_arm_x4, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_MINMAX__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -877,10 +877,10 @@
.Test(xnn_f32_vadd_minmax_ukernel__wasmsimd_arm_x8, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_MINMAX__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -956,10 +956,10 @@
.Test(xnn_f32_vadd_minmax_ukernel__wasmsimd_x86_x4, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_MINMAX__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -1035,10 +1035,10 @@
.Test(xnn_f32_vadd_minmax_ukernel__wasmsimd_x86_x8, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_MINMAX__WASM_X1, batch_eq_1) {
VBinaryMicrokernelTester()
.batch_size(1)
@@ -1098,10 +1098,10 @@
.Test(xnn_f32_vadd_minmax_ukernel__wasm_x1, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_MINMAX__WASM_X2, batch_eq_2) {
VBinaryMicrokernelTester()
.batch_size(2)
@@ -1177,10 +1177,10 @@
.Test(xnn_f32_vadd_minmax_ukernel__wasm_x2, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_MINMAX__WASM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -1256,7 +1256,7 @@
.Test(xnn_f32_vadd_minmax_ukernel__wasm_x4, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vadd-relu.cc b/test/f32-vadd-relu.cc
index 7eef96d..d488ca2 100644
--- a/test/f32-vadd-relu.cc
+++ b/test/f32-vadd-relu.cc
@@ -18,7 +18,7 @@
#include "vbinary-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_RELU__WASMSIMD_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -76,10 +76,10 @@
.Test(xnn_f32_vadd_relu_ukernel__wasmsimd_x4, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_RELU__WASMSIMD_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -137,10 +137,10 @@
.Test(xnn_f32_vadd_relu_ukernel__wasmsimd_x8, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_RELU__WASMSIMD_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -198,10 +198,10 @@
.Test(xnn_f32_vadd_relu_ukernel__wasmsimd_x16, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_RELU__WASM_X1, batch_eq_1) {
VBinaryMicrokernelTester()
.batch_size(1)
@@ -243,10 +243,10 @@
.Test(xnn_f32_vadd_relu_ukernel__wasm_x1, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_RELU__WASM_X2, batch_eq_2) {
VBinaryMicrokernelTester()
.batch_size(2)
@@ -304,10 +304,10 @@
.Test(xnn_f32_vadd_relu_ukernel__wasm_x2, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_RELU__WASM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -365,10 +365,10 @@
.Test(xnn_f32_vadd_relu_ukernel__wasm_x4, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_RELU__WASM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -426,7 +426,7 @@
.Test(xnn_f32_vadd_relu_ukernel__wasm_x8, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD_RELU__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vadd.cc b/test/f32-vadd.cc
index 960ca7f..843b7d3 100644
--- a/test/f32-vadd.cc
+++ b/test/f32-vadd.cc
@@ -18,7 +18,7 @@
#include "vbinary-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD__WASMSIMD_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -76,10 +76,10 @@
.Test(xnn_f32_vadd_ukernel__wasmsimd_x4, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD__WASMSIMD_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -137,10 +137,10 @@
.Test(xnn_f32_vadd_ukernel__wasmsimd_x8, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD__WASMSIMD_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -198,7 +198,7 @@
.Test(xnn_f32_vadd_ukernel__wasmsimd_x16, VBinaryMicrokernelTester::OpType::Add);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADD__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vaddc-minmax.cc b/test/f32-vaddc-minmax.cc
index ced170e..75e656e 100644
--- a/test/f32-vaddc-minmax.cc
+++ b/test/f32-vaddc-minmax.cc
@@ -554,7 +554,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_MINMAX__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -611,10 +611,10 @@
.Test(xnn_f32_vaddc_minmax_ukernel__wasmsimd_arm_x4, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_MINMAX__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -671,10 +671,10 @@
.Test(xnn_f32_vaddc_minmax_ukernel__wasmsimd_arm_x8, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_MINMAX__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -731,10 +731,10 @@
.Test(xnn_f32_vaddc_minmax_ukernel__wasmsimd_arm_x16, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_MINMAX__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -791,10 +791,10 @@
.Test(xnn_f32_vaddc_minmax_ukernel__wasmsimd_x86_x4, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_MINMAX__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -851,10 +851,10 @@
.Test(xnn_f32_vaddc_minmax_ukernel__wasmsimd_x86_x8, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_MINMAX__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -911,10 +911,10 @@
.Test(xnn_f32_vaddc_minmax_ukernel__wasmsimd_x86_x16, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_MINMAX__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -955,10 +955,10 @@
.Test(xnn_f32_vaddc_minmax_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_MINMAX__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -1015,10 +1015,10 @@
.Test(xnn_f32_vaddc_minmax_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_MINMAX__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -1075,10 +1075,10 @@
.Test(xnn_f32_vaddc_minmax_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_MINMAX__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -1135,7 +1135,7 @@
.Test(xnn_f32_vaddc_minmax_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vaddc-relu.cc b/test/f32-vaddc-relu.cc
index 57d4db1..45fc680 100644
--- a/test/f32-vaddc-relu.cc
+++ b/test/f32-vaddc-relu.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_RELU__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vaddc_relu_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_RELU__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vaddc_relu_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_RELU__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,10 +141,10 @@
.Test(xnn_f32_vaddc_relu_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_RELU__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -167,10 +167,10 @@
.Test(xnn_f32_vaddc_relu_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_RELU__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -209,10 +209,10 @@
.Test(xnn_f32_vaddc_relu_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_RELU__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -251,10 +251,10 @@
.Test(xnn_f32_vaddc_relu_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_RELU__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -293,7 +293,7 @@
.Test(xnn_f32_vaddc_relu_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC_RELU__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vaddc.cc b/test/f32-vaddc.cc
index a288f48..b5f1b27 100644
--- a/test/f32-vaddc.cc
+++ b/test/f32-vaddc.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vaddc_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vaddc_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,7 +141,7 @@
.Test(xnn_f32_vaddc_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::AddC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VADDC__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vclamp.cc b/test/f32-vclamp.cc
index 2894ffa..5764b64 100644
--- a/test/f32-vclamp.cc
+++ b/test/f32-vclamp.cc
@@ -585,7 +585,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VCLAMP__WASMSIMD_ARM_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -646,10 +646,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VCLAMP__WASMSIMD_ARM_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -710,10 +710,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VCLAMP__WASMSIMD_X86_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -774,10 +774,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VCLAMP__WASMSIMD_X86_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -838,10 +838,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VCLAMP__WASM_X1, batch_eq_1) {
VUnaryMicrokernelTester()
.batch_size(1)
@@ -886,10 +886,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VCLAMP__WASM_X2, batch_eq_2) {
VUnaryMicrokernelTester()
.batch_size(2)
@@ -950,10 +950,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VCLAMP__WASM_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -1014,7 +1014,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VCLAMP__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vdiv-minmax.cc b/test/f32-vdiv-minmax.cc
index 16f6328..6f908d9 100644
--- a/test/f32-vdiv-minmax.cc
+++ b/test/f32-vdiv-minmax.cc
@@ -722,7 +722,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_MINMAX__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -798,10 +798,10 @@
.Test(xnn_f32_vdiv_minmax_ukernel__wasmsimd_arm_x4, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_MINMAX__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -877,10 +877,10 @@
.Test(xnn_f32_vdiv_minmax_ukernel__wasmsimd_arm_x8, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_MINMAX__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -956,10 +956,10 @@
.Test(xnn_f32_vdiv_minmax_ukernel__wasmsimd_arm_x16, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_MINMAX__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -1035,10 +1035,10 @@
.Test(xnn_f32_vdiv_minmax_ukernel__wasmsimd_x86_x4, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_MINMAX__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -1114,10 +1114,10 @@
.Test(xnn_f32_vdiv_minmax_ukernel__wasmsimd_x86_x8, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_MINMAX__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -1193,10 +1193,10 @@
.Test(xnn_f32_vdiv_minmax_ukernel__wasmsimd_x86_x16, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_MINMAX__WASM_X1, batch_eq_1) {
VBinaryMicrokernelTester()
.batch_size(1)
@@ -1256,10 +1256,10 @@
.Test(xnn_f32_vdiv_minmax_ukernel__wasm_x1, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_MINMAX__WASM_X2, batch_eq_2) {
VBinaryMicrokernelTester()
.batch_size(2)
@@ -1335,10 +1335,10 @@
.Test(xnn_f32_vdiv_minmax_ukernel__wasm_x2, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_MINMAX__WASM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -1414,10 +1414,10 @@
.Test(xnn_f32_vdiv_minmax_ukernel__wasm_x4, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_MINMAX__WASM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -1493,7 +1493,7 @@
.Test(xnn_f32_vdiv_minmax_ukernel__wasm_x8, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vdiv-relu.cc b/test/f32-vdiv-relu.cc
index 691f47c..33b9fb1 100644
--- a/test/f32-vdiv-relu.cc
+++ b/test/f32-vdiv-relu.cc
@@ -18,7 +18,7 @@
#include "vbinary-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_RELU__WASMSIMD_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -76,10 +76,10 @@
.Test(xnn_f32_vdiv_relu_ukernel__wasmsimd_x4, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_RELU__WASMSIMD_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -137,10 +137,10 @@
.Test(xnn_f32_vdiv_relu_ukernel__wasmsimd_x8, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_RELU__WASMSIMD_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -198,10 +198,10 @@
.Test(xnn_f32_vdiv_relu_ukernel__wasmsimd_x16, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_RELU__WASM_X1, batch_eq_1) {
VBinaryMicrokernelTester()
.batch_size(1)
@@ -243,10 +243,10 @@
.Test(xnn_f32_vdiv_relu_ukernel__wasm_x1, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_RELU__WASM_X2, batch_eq_2) {
VBinaryMicrokernelTester()
.batch_size(2)
@@ -304,10 +304,10 @@
.Test(xnn_f32_vdiv_relu_ukernel__wasm_x2, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_RELU__WASM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -365,10 +365,10 @@
.Test(xnn_f32_vdiv_relu_ukernel__wasm_x4, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_RELU__WASM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -426,7 +426,7 @@
.Test(xnn_f32_vdiv_relu_ukernel__wasm_x8, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV_RELU__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vdiv.cc b/test/f32-vdiv.cc
index 8b5c925..97b7358 100644
--- a/test/f32-vdiv.cc
+++ b/test/f32-vdiv.cc
@@ -18,7 +18,7 @@
#include "vbinary-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV__WASMSIMD_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -76,10 +76,10 @@
.Test(xnn_f32_vdiv_ukernel__wasmsimd_x4, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV__WASMSIMD_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -137,10 +137,10 @@
.Test(xnn_f32_vdiv_ukernel__wasmsimd_x8, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV__WASMSIMD_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -198,7 +198,7 @@
.Test(xnn_f32_vdiv_ukernel__wasmsimd_x16, VBinaryMicrokernelTester::OpType::Div);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIV__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vdivc-minmax.cc b/test/f32-vdivc-minmax.cc
index 46ebd7a..547b83e 100644
--- a/test/f32-vdivc-minmax.cc
+++ b/test/f32-vdivc-minmax.cc
@@ -554,7 +554,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_MINMAX__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -611,10 +611,10 @@
.Test(xnn_f32_vdivc_minmax_ukernel__wasmsimd_arm_x4, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_MINMAX__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -671,10 +671,10 @@
.Test(xnn_f32_vdivc_minmax_ukernel__wasmsimd_arm_x8, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_MINMAX__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -731,10 +731,10 @@
.Test(xnn_f32_vdivc_minmax_ukernel__wasmsimd_arm_x16, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_MINMAX__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -791,10 +791,10 @@
.Test(xnn_f32_vdivc_minmax_ukernel__wasmsimd_x86_x4, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_MINMAX__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -851,10 +851,10 @@
.Test(xnn_f32_vdivc_minmax_ukernel__wasmsimd_x86_x8, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_MINMAX__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -911,10 +911,10 @@
.Test(xnn_f32_vdivc_minmax_ukernel__wasmsimd_x86_x16, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_MINMAX__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -955,10 +955,10 @@
.Test(xnn_f32_vdivc_minmax_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_MINMAX__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -1015,10 +1015,10 @@
.Test(xnn_f32_vdivc_minmax_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_MINMAX__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -1075,10 +1075,10 @@
.Test(xnn_f32_vdivc_minmax_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_MINMAX__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -1135,7 +1135,7 @@
.Test(xnn_f32_vdivc_minmax_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vdivc-relu.cc b/test/f32-vdivc-relu.cc
index 09d0158..f92bdee 100644
--- a/test/f32-vdivc-relu.cc
+++ b/test/f32-vdivc-relu.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_RELU__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vdivc_relu_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_RELU__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vdivc_relu_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_RELU__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,10 +141,10 @@
.Test(xnn_f32_vdivc_relu_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_RELU__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -167,10 +167,10 @@
.Test(xnn_f32_vdivc_relu_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_RELU__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -209,10 +209,10 @@
.Test(xnn_f32_vdivc_relu_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_RELU__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -251,10 +251,10 @@
.Test(xnn_f32_vdivc_relu_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_RELU__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -293,7 +293,7 @@
.Test(xnn_f32_vdivc_relu_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC_RELU__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vdivc.cc b/test/f32-vdivc.cc
index f31014e..9a4e7eb 100644
--- a/test/f32-vdivc.cc
+++ b/test/f32-vdivc.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vdivc_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vdivc_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,7 +141,7 @@
.Test(xnn_f32_vdivc_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::DivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VDIVC__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-velu.cc b/test/f32-velu.cc
index d07f284..931940d 100644
--- a/test/f32-velu.cc
+++ b/test/f32-velu.cc
@@ -10143,7 +10143,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_LUT16_P3_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -10215,10 +10215,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_LUT16_P3_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -10290,10 +10290,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_LUT16_P3_X12, batch_eq_12) {
VUnaryMicrokernelTester()
.batch_size(12)
@@ -10365,10 +10365,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_LUT16_P3_X16, batch_eq_16) {
VUnaryMicrokernelTester()
.batch_size(16)
@@ -10440,10 +10440,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_LUT16_P3_X20, batch_eq_20) {
VUnaryMicrokernelTester()
.batch_size(20)
@@ -10515,10 +10515,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_LUT16_P3_X24, batch_eq_24) {
VUnaryMicrokernelTester()
.batch_size(24)
@@ -10590,10 +10590,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_LUT16_P3_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -10665,10 +10665,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_LUT16_P3_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -10740,10 +10740,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_LUT16_P3_X12, batch_eq_12) {
VUnaryMicrokernelTester()
.batch_size(12)
@@ -10815,10 +10815,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_LUT16_P3_X16, batch_eq_16) {
VUnaryMicrokernelTester()
.batch_size(16)
@@ -10890,10 +10890,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_LUT16_P3_X20, batch_eq_20) {
VUnaryMicrokernelTester()
.batch_size(20)
@@ -10965,10 +10965,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_LUT16_P3_X24, batch_eq_24) {
VUnaryMicrokernelTester()
.batch_size(24)
@@ -11040,10 +11040,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_P6_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -11115,10 +11115,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_P6_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -11190,10 +11190,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_P6_X12, batch_eq_12) {
VUnaryMicrokernelTester()
.batch_size(12)
@@ -11265,10 +11265,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_P6_X16, batch_eq_16) {
VUnaryMicrokernelTester()
.batch_size(16)
@@ -11340,10 +11340,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_P6_X20, batch_eq_20) {
VUnaryMicrokernelTester()
.batch_size(20)
@@ -11415,10 +11415,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_ARM_RR2_P6_X24, batch_eq_24) {
VUnaryMicrokernelTester()
.batch_size(24)
@@ -11490,10 +11490,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_P6_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -11565,10 +11565,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_P6_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -11640,10 +11640,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_P6_X12, batch_eq_12) {
VUnaryMicrokernelTester()
.batch_size(12)
@@ -11715,10 +11715,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_P6_X16, batch_eq_16) {
VUnaryMicrokernelTester()
.batch_size(16)
@@ -11790,10 +11790,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_P6_X20, batch_eq_20) {
VUnaryMicrokernelTester()
.batch_size(20)
@@ -11865,10 +11865,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASMSIMD_X86_RR2_P6_X24, batch_eq_24) {
VUnaryMicrokernelTester()
.batch_size(24)
@@ -11940,10 +11940,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_LUT16_P3_X1, batch_eq_1) {
VUnaryMicrokernelTester()
.batch_size(1)
@@ -11999,10 +11999,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_LUT16_P3_X2, batch_eq_2) {
VUnaryMicrokernelTester()
.batch_size(2)
@@ -12074,10 +12074,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_LUT16_P3_X3, batch_eq_3) {
VUnaryMicrokernelTester()
.batch_size(3)
@@ -12149,10 +12149,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_LUT16_P3_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -12224,10 +12224,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_LUT16_P3_X5, batch_eq_5) {
VUnaryMicrokernelTester()
.batch_size(5)
@@ -12299,10 +12299,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_LUT16_P3_X6, batch_eq_6) {
VUnaryMicrokernelTester()
.batch_size(6)
@@ -12374,10 +12374,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_P6_X1, batch_eq_1) {
VUnaryMicrokernelTester()
.batch_size(1)
@@ -12433,10 +12433,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_P6_X2, batch_eq_2) {
VUnaryMicrokernelTester()
.batch_size(2)
@@ -12508,10 +12508,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_P6_X3, batch_eq_3) {
VUnaryMicrokernelTester()
.batch_size(3)
@@ -12583,10 +12583,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_P6_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -12658,10 +12658,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_P6_X5, batch_eq_5) {
VUnaryMicrokernelTester()
.batch_size(5)
@@ -12733,10 +12733,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__WASM_RR2_P6_X6, batch_eq_6) {
VUnaryMicrokernelTester()
.batch_size(6)
@@ -12808,7 +12808,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VELU__SCALAR_RR2_LUT16_P3_X1, batch_eq_1) {
diff --git a/test/f32-vhswish.cc b/test/f32-vhswish.cc
index b7c78e6..fb787cb 100644
--- a/test/f32-vhswish.cc
+++ b/test/f32-vhswish.cc
@@ -534,7 +534,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VHSWISH__WASMSIMD_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -573,10 +573,10 @@
.Test(xnn_f32_vhswish_ukernel__wasmsimd_x4, VUnaryMicrokernelTester::OpType::HardSwish);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VHSWISH__WASMSIMD_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -615,10 +615,10 @@
.Test(xnn_f32_vhswish_ukernel__wasmsimd_x8, VUnaryMicrokernelTester::OpType::HardSwish);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VHSWISH__WASMSIMD_X16, batch_eq_16) {
VUnaryMicrokernelTester()
.batch_size(16)
@@ -657,10 +657,10 @@
.Test(xnn_f32_vhswish_ukernel__wasmsimd_x16, VUnaryMicrokernelTester::OpType::HardSwish);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VHSWISH__WASM_X1, batch_eq_1) {
VUnaryMicrokernelTester()
.batch_size(1)
@@ -683,10 +683,10 @@
.Test(xnn_f32_vhswish_ukernel__wasm_x1, VUnaryMicrokernelTester::OpType::HardSwish);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VHSWISH__WASM_X2, batch_eq_2) {
VUnaryMicrokernelTester()
.batch_size(2)
@@ -725,10 +725,10 @@
.Test(xnn_f32_vhswish_ukernel__wasm_x2, VUnaryMicrokernelTester::OpType::HardSwish);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VHSWISH__WASM_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -767,7 +767,7 @@
.Test(xnn_f32_vhswish_ukernel__wasm_x4, VUnaryMicrokernelTester::OpType::HardSwish);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VHSWISH__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vlrelu.cc b/test/f32-vlrelu.cc
index d09b98f..8f34e4d 100644
--- a/test/f32-vlrelu.cc
+++ b/test/f32-vlrelu.cc
@@ -725,7 +725,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VLRELU__WASMSIMD_BITSELECT_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -775,10 +775,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VLRELU__WASMSIMD_BITSELECT_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -828,10 +828,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VLRELU__WASMSIMD_MINMAX_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -881,10 +881,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VLRELU__WASMSIMD_MINMAX_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -934,10 +934,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VLRELU__WASM_X1, batch_eq_1) {
VUnaryMicrokernelTester()
.batch_size(1)
@@ -971,10 +971,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VLRELU__WASM_X2, batch_eq_2) {
VUnaryMicrokernelTester()
.batch_size(2)
@@ -1024,10 +1024,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VLRELU__WASM_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -1077,7 +1077,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VLRELU__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vmax.cc b/test/f32-vmax.cc
index f9a9774..a0799db 100644
--- a/test/f32-vmax.cc
+++ b/test/f32-vmax.cc
@@ -562,7 +562,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAX__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -620,10 +620,10 @@
.Test(xnn_f32_vmax_ukernel__wasmsimd_arm_x4, VBinaryMicrokernelTester::OpType::Max);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAX__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -681,10 +681,10 @@
.Test(xnn_f32_vmax_ukernel__wasmsimd_arm_x8, VBinaryMicrokernelTester::OpType::Max);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAX__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -742,10 +742,10 @@
.Test(xnn_f32_vmax_ukernel__wasmsimd_arm_x16, VBinaryMicrokernelTester::OpType::Max);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAX__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -803,10 +803,10 @@
.Test(xnn_f32_vmax_ukernel__wasmsimd_x86_x4, VBinaryMicrokernelTester::OpType::Max);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAX__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -864,10 +864,10 @@
.Test(xnn_f32_vmax_ukernel__wasmsimd_x86_x8, VBinaryMicrokernelTester::OpType::Max);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAX__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -925,10 +925,10 @@
.Test(xnn_f32_vmax_ukernel__wasmsimd_x86_x16, VBinaryMicrokernelTester::OpType::Max);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAX__WASM_X1, batch_eq_1) {
VBinaryMicrokernelTester()
.batch_size(1)
@@ -970,10 +970,10 @@
.Test(xnn_f32_vmax_ukernel__wasm_x1, VBinaryMicrokernelTester::OpType::Max);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAX__WASM_X2, batch_eq_2) {
VBinaryMicrokernelTester()
.batch_size(2)
@@ -1031,10 +1031,10 @@
.Test(xnn_f32_vmax_ukernel__wasm_x2, VBinaryMicrokernelTester::OpType::Max);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAX__WASM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -1092,10 +1092,10 @@
.Test(xnn_f32_vmax_ukernel__wasm_x4, VBinaryMicrokernelTester::OpType::Max);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAX__WASM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -1153,7 +1153,7 @@
.Test(xnn_f32_vmax_ukernel__wasm_x8, VBinaryMicrokernelTester::OpType::Max);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vmaxc.cc b/test/f32-vmaxc.cc
index 1b71d59..cd4da88 100644
--- a/test/f32-vmaxc.cc
+++ b/test/f32-vmaxc.cc
@@ -394,7 +394,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAXC__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -433,10 +433,10 @@
.Test(xnn_f32_vmaxc_ukernel__wasmsimd_arm_x4, VBinaryCMicrokernelTester::OpType::MaxC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAXC__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -475,10 +475,10 @@
.Test(xnn_f32_vmaxc_ukernel__wasmsimd_arm_x8, VBinaryCMicrokernelTester::OpType::MaxC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAXC__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -517,10 +517,10 @@
.Test(xnn_f32_vmaxc_ukernel__wasmsimd_arm_x16, VBinaryCMicrokernelTester::OpType::MaxC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAXC__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -559,10 +559,10 @@
.Test(xnn_f32_vmaxc_ukernel__wasmsimd_x86_x4, VBinaryCMicrokernelTester::OpType::MaxC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAXC__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -601,10 +601,10 @@
.Test(xnn_f32_vmaxc_ukernel__wasmsimd_x86_x8, VBinaryCMicrokernelTester::OpType::MaxC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAXC__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -643,10 +643,10 @@
.Test(xnn_f32_vmaxc_ukernel__wasmsimd_x86_x16, VBinaryCMicrokernelTester::OpType::MaxC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAXC__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -669,10 +669,10 @@
.Test(xnn_f32_vmaxc_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::MaxC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAXC__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -711,10 +711,10 @@
.Test(xnn_f32_vmaxc_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::MaxC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAXC__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -753,10 +753,10 @@
.Test(xnn_f32_vmaxc_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::MaxC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAXC__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -795,7 +795,7 @@
.Test(xnn_f32_vmaxc_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::MaxC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMAXC__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vmin.cc b/test/f32-vmin.cc
index 03e6989..f97a759 100644
--- a/test/f32-vmin.cc
+++ b/test/f32-vmin.cc
@@ -562,7 +562,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMIN__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -620,10 +620,10 @@
.Test(xnn_f32_vmin_ukernel__wasmsimd_arm_x4, VBinaryMicrokernelTester::OpType::Min);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMIN__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -681,10 +681,10 @@
.Test(xnn_f32_vmin_ukernel__wasmsimd_arm_x8, VBinaryMicrokernelTester::OpType::Min);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMIN__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -742,10 +742,10 @@
.Test(xnn_f32_vmin_ukernel__wasmsimd_arm_x16, VBinaryMicrokernelTester::OpType::Min);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMIN__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -803,10 +803,10 @@
.Test(xnn_f32_vmin_ukernel__wasmsimd_x86_x4, VBinaryMicrokernelTester::OpType::Min);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMIN__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -864,10 +864,10 @@
.Test(xnn_f32_vmin_ukernel__wasmsimd_x86_x8, VBinaryMicrokernelTester::OpType::Min);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMIN__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -925,10 +925,10 @@
.Test(xnn_f32_vmin_ukernel__wasmsimd_x86_x16, VBinaryMicrokernelTester::OpType::Min);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMIN__WASM_X1, batch_eq_1) {
VBinaryMicrokernelTester()
.batch_size(1)
@@ -970,10 +970,10 @@
.Test(xnn_f32_vmin_ukernel__wasm_x1, VBinaryMicrokernelTester::OpType::Min);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMIN__WASM_X2, batch_eq_2) {
VBinaryMicrokernelTester()
.batch_size(2)
@@ -1031,10 +1031,10 @@
.Test(xnn_f32_vmin_ukernel__wasm_x2, VBinaryMicrokernelTester::OpType::Min);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMIN__WASM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -1092,10 +1092,10 @@
.Test(xnn_f32_vmin_ukernel__wasm_x4, VBinaryMicrokernelTester::OpType::Min);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMIN__WASM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -1153,7 +1153,7 @@
.Test(xnn_f32_vmin_ukernel__wasm_x8, VBinaryMicrokernelTester::OpType::Min);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMIN__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vminc.cc b/test/f32-vminc.cc
index c613351..1ec7554 100644
--- a/test/f32-vminc.cc
+++ b/test/f32-vminc.cc
@@ -394,7 +394,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMINC__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -433,10 +433,10 @@
.Test(xnn_f32_vminc_ukernel__wasmsimd_arm_x4, VBinaryCMicrokernelTester::OpType::MinC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMINC__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -475,10 +475,10 @@
.Test(xnn_f32_vminc_ukernel__wasmsimd_arm_x8, VBinaryCMicrokernelTester::OpType::MinC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMINC__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -517,10 +517,10 @@
.Test(xnn_f32_vminc_ukernel__wasmsimd_arm_x16, VBinaryCMicrokernelTester::OpType::MinC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMINC__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -559,10 +559,10 @@
.Test(xnn_f32_vminc_ukernel__wasmsimd_x86_x4, VBinaryCMicrokernelTester::OpType::MinC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMINC__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -601,10 +601,10 @@
.Test(xnn_f32_vminc_ukernel__wasmsimd_x86_x8, VBinaryCMicrokernelTester::OpType::MinC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMINC__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -643,10 +643,10 @@
.Test(xnn_f32_vminc_ukernel__wasmsimd_x86_x16, VBinaryCMicrokernelTester::OpType::MinC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMINC__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -669,10 +669,10 @@
.Test(xnn_f32_vminc_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::MinC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMINC__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -711,10 +711,10 @@
.Test(xnn_f32_vminc_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::MinC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMINC__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -753,10 +753,10 @@
.Test(xnn_f32_vminc_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::MinC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMINC__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -795,7 +795,7 @@
.Test(xnn_f32_vminc_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::MinC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMINC__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vmul-minmax.cc b/test/f32-vmul-minmax.cc
index 109d129..d8d79ef 100644
--- a/test/f32-vmul-minmax.cc
+++ b/test/f32-vmul-minmax.cc
@@ -722,7 +722,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_MINMAX__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -798,10 +798,10 @@
.Test(xnn_f32_vmul_minmax_ukernel__wasmsimd_arm_x4, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_MINMAX__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -877,10 +877,10 @@
.Test(xnn_f32_vmul_minmax_ukernel__wasmsimd_arm_x8, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_MINMAX__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -956,10 +956,10 @@
.Test(xnn_f32_vmul_minmax_ukernel__wasmsimd_arm_x16, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_MINMAX__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -1035,10 +1035,10 @@
.Test(xnn_f32_vmul_minmax_ukernel__wasmsimd_x86_x4, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_MINMAX__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -1114,10 +1114,10 @@
.Test(xnn_f32_vmul_minmax_ukernel__wasmsimd_x86_x8, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_MINMAX__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -1193,10 +1193,10 @@
.Test(xnn_f32_vmul_minmax_ukernel__wasmsimd_x86_x16, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_MINMAX__WASM_X1, batch_eq_1) {
VBinaryMicrokernelTester()
.batch_size(1)
@@ -1256,10 +1256,10 @@
.Test(xnn_f32_vmul_minmax_ukernel__wasm_x1, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_MINMAX__WASM_X2, batch_eq_2) {
VBinaryMicrokernelTester()
.batch_size(2)
@@ -1335,10 +1335,10 @@
.Test(xnn_f32_vmul_minmax_ukernel__wasm_x2, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_MINMAX__WASM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -1414,10 +1414,10 @@
.Test(xnn_f32_vmul_minmax_ukernel__wasm_x4, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_MINMAX__WASM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -1493,7 +1493,7 @@
.Test(xnn_f32_vmul_minmax_ukernel__wasm_x8, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vmul-relu.cc b/test/f32-vmul-relu.cc
index 560b3b8..70b65e3 100644
--- a/test/f32-vmul-relu.cc
+++ b/test/f32-vmul-relu.cc
@@ -18,7 +18,7 @@
#include "vbinary-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_RELU__WASMSIMD_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -76,10 +76,10 @@
.Test(xnn_f32_vmul_relu_ukernel__wasmsimd_x4, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_RELU__WASMSIMD_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -137,10 +137,10 @@
.Test(xnn_f32_vmul_relu_ukernel__wasmsimd_x8, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_RELU__WASMSIMD_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -198,10 +198,10 @@
.Test(xnn_f32_vmul_relu_ukernel__wasmsimd_x16, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_RELU__WASM_X1, batch_eq_1) {
VBinaryMicrokernelTester()
.batch_size(1)
@@ -243,10 +243,10 @@
.Test(xnn_f32_vmul_relu_ukernel__wasm_x1, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_RELU__WASM_X2, batch_eq_2) {
VBinaryMicrokernelTester()
.batch_size(2)
@@ -304,10 +304,10 @@
.Test(xnn_f32_vmul_relu_ukernel__wasm_x2, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_RELU__WASM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -365,10 +365,10 @@
.Test(xnn_f32_vmul_relu_ukernel__wasm_x4, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_RELU__WASM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -426,7 +426,7 @@
.Test(xnn_f32_vmul_relu_ukernel__wasm_x8, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL_RELU__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vmul.cc b/test/f32-vmul.cc
index da8928a..8e740fe 100644
--- a/test/f32-vmul.cc
+++ b/test/f32-vmul.cc
@@ -18,7 +18,7 @@
#include "vbinary-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL__WASMSIMD_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -76,10 +76,10 @@
.Test(xnn_f32_vmul_ukernel__wasmsimd_x4, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL__WASMSIMD_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -137,10 +137,10 @@
.Test(xnn_f32_vmul_ukernel__wasmsimd_x8, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL__WASMSIMD_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -198,7 +198,7 @@
.Test(xnn_f32_vmul_ukernel__wasmsimd_x16, VBinaryMicrokernelTester::OpType::Mul);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMUL__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vmulc-minmax.cc b/test/f32-vmulc-minmax.cc
index af13030..d5bc378 100644
--- a/test/f32-vmulc-minmax.cc
+++ b/test/f32-vmulc-minmax.cc
@@ -554,7 +554,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_MINMAX__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -611,10 +611,10 @@
.Test(xnn_f32_vmulc_minmax_ukernel__wasmsimd_arm_x4, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_MINMAX__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -671,10 +671,10 @@
.Test(xnn_f32_vmulc_minmax_ukernel__wasmsimd_arm_x8, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_MINMAX__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -731,10 +731,10 @@
.Test(xnn_f32_vmulc_minmax_ukernel__wasmsimd_arm_x16, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_MINMAX__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -791,10 +791,10 @@
.Test(xnn_f32_vmulc_minmax_ukernel__wasmsimd_x86_x4, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_MINMAX__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -851,10 +851,10 @@
.Test(xnn_f32_vmulc_minmax_ukernel__wasmsimd_x86_x8, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_MINMAX__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -911,10 +911,10 @@
.Test(xnn_f32_vmulc_minmax_ukernel__wasmsimd_x86_x16, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_MINMAX__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -955,10 +955,10 @@
.Test(xnn_f32_vmulc_minmax_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_MINMAX__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -1015,10 +1015,10 @@
.Test(xnn_f32_vmulc_minmax_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_MINMAX__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -1075,10 +1075,10 @@
.Test(xnn_f32_vmulc_minmax_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_MINMAX__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -1135,7 +1135,7 @@
.Test(xnn_f32_vmulc_minmax_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vmulc-relu.cc b/test/f32-vmulc-relu.cc
index 0e117f1..2f5c801 100644
--- a/test/f32-vmulc-relu.cc
+++ b/test/f32-vmulc-relu.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_RELU__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vmulc_relu_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_RELU__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vmulc_relu_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_RELU__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,10 +141,10 @@
.Test(xnn_f32_vmulc_relu_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_RELU__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -167,10 +167,10 @@
.Test(xnn_f32_vmulc_relu_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_RELU__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -209,10 +209,10 @@
.Test(xnn_f32_vmulc_relu_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_RELU__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -251,10 +251,10 @@
.Test(xnn_f32_vmulc_relu_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_RELU__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -293,7 +293,7 @@
.Test(xnn_f32_vmulc_relu_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC_RELU__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vmulc.cc b/test/f32-vmulc.cc
index 2384d9a..598bfd0 100644
--- a/test/f32-vmulc.cc
+++ b/test/f32-vmulc.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vmulc_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vmulc_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,7 +141,7 @@
.Test(xnn_f32_vmulc_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::MulC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULC__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vmulcaddc-minmax.cc b/test/f32-vmulcaddc-minmax.cc
index dd9f8f2..3554d9d 100644
--- a/test/f32-vmulcaddc-minmax.cc
+++ b/test/f32-vmulcaddc-minmax.cc
@@ -941,7 +941,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_ARM_2X, channels_eq_4) {
VMulCAddCMicrokernelTester()
.channel_tile(4)
@@ -1080,10 +1080,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_ARM_2X, channels_eq_8) {
VMulCAddCMicrokernelTester()
.channel_tile(8)
@@ -1222,10 +1222,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULCADDC_MINMAX_C4__WASMSIMD_X86_2X, channels_eq_4) {
VMulCAddCMicrokernelTester()
.channel_tile(4)
@@ -1364,10 +1364,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULCADDC_MINMAX_C8__WASMSIMD_X86_2X, channels_eq_8) {
VMulCAddCMicrokernelTester()
.channel_tile(8)
@@ -1506,10 +1506,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULCADDC_MINMAX_C1__WASM_2X, channels_eq_1) {
VMulCAddCMicrokernelTester()
.channel_tile(1)
@@ -1628,10 +1628,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULCADDC_MINMAX_C2__WASM_2X, channels_eq_2) {
VMulCAddCMicrokernelTester()
.channel_tile(2)
@@ -1770,10 +1770,10 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULCADDC_MINMAX_C4__WASM_2X, channels_eq_4) {
VMulCAddCMicrokernelTester()
.channel_tile(4)
@@ -1912,7 +1912,7 @@
}
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VMULCADDC_MINMAX_C1__SCALAR_2X, channels_eq_1) {
diff --git a/test/f32-vneg.cc b/test/f32-vneg.cc
index eb5b680..729821b 100644
--- a/test/f32-vneg.cc
+++ b/test/f32-vneg.cc
@@ -393,7 +393,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VNEG__WASMSIMD_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -432,10 +432,10 @@
.Test(xnn_f32_vneg_ukernel__wasmsimd_x4, VUnaryMicrokernelTester::OpType::Negate);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VNEG__WASMSIMD_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -474,7 +474,7 @@
.Test(xnn_f32_vneg_ukernel__wasmsimd_x8, VUnaryMicrokernelTester::OpType::Negate);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VNEG__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vrdivc-minmax.cc b/test/f32-vrdivc-minmax.cc
index 4978ef4..b7a732e 100644
--- a/test/f32-vrdivc-minmax.cc
+++ b/test/f32-vrdivc-minmax.cc
@@ -554,7 +554,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_MINMAX__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -611,10 +611,10 @@
.Test(xnn_f32_vrdivc_minmax_ukernel__wasmsimd_arm_x4, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_MINMAX__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -671,10 +671,10 @@
.Test(xnn_f32_vrdivc_minmax_ukernel__wasmsimd_arm_x8, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_MINMAX__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -731,10 +731,10 @@
.Test(xnn_f32_vrdivc_minmax_ukernel__wasmsimd_arm_x16, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_MINMAX__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -791,10 +791,10 @@
.Test(xnn_f32_vrdivc_minmax_ukernel__wasmsimd_x86_x4, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_MINMAX__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -851,10 +851,10 @@
.Test(xnn_f32_vrdivc_minmax_ukernel__wasmsimd_x86_x8, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_MINMAX__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -911,10 +911,10 @@
.Test(xnn_f32_vrdivc_minmax_ukernel__wasmsimd_x86_x16, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_MINMAX__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -955,10 +955,10 @@
.Test(xnn_f32_vrdivc_minmax_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_MINMAX__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -1015,10 +1015,10 @@
.Test(xnn_f32_vrdivc_minmax_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_MINMAX__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -1075,10 +1075,10 @@
.Test(xnn_f32_vrdivc_minmax_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_MINMAX__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -1135,7 +1135,7 @@
.Test(xnn_f32_vrdivc_minmax_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vrdivc-relu.cc b/test/f32-vrdivc-relu.cc
index b139e7b..0388340 100644
--- a/test/f32-vrdivc-relu.cc
+++ b/test/f32-vrdivc-relu.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_RELU__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vrdivc_relu_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_RELU__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vrdivc_relu_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_RELU__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,10 +141,10 @@
.Test(xnn_f32_vrdivc_relu_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_RELU__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -167,10 +167,10 @@
.Test(xnn_f32_vrdivc_relu_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_RELU__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -209,10 +209,10 @@
.Test(xnn_f32_vrdivc_relu_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_RELU__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -251,10 +251,10 @@
.Test(xnn_f32_vrdivc_relu_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_RELU__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -293,7 +293,7 @@
.Test(xnn_f32_vrdivc_relu_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC_RELU__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vrdivc.cc b/test/f32-vrdivc.cc
index 2e85c8d..ffac0c4 100644
--- a/test/f32-vrdivc.cc
+++ b/test/f32-vrdivc.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vrdivc_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vrdivc_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,7 +141,7 @@
.Test(xnn_f32_vrdivc_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::RDivC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRDIVC__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vrelu.cc b/test/f32-vrelu.cc
index 21296eb..7ee7dcf 100644
--- a/test/f32-vrelu.cc
+++ b/test/f32-vrelu.cc
@@ -537,7 +537,7 @@
}
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRELU__WASM_X1, batch_eq_1) {
VUnaryMicrokernelTester()
.batch_size(1)
@@ -560,10 +560,10 @@
.Test(xnn_f32_vrelu_ukernel__wasm_x1, VUnaryMicrokernelTester::OpType::ReLU);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRELU__WASM_X2, batch_eq_2) {
VUnaryMicrokernelTester()
.batch_size(2)
@@ -602,10 +602,10 @@
.Test(xnn_f32_vrelu_ukernel__wasm_x2, VUnaryMicrokernelTester::OpType::ReLU);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRELU__WASM_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -644,10 +644,10 @@
.Test(xnn_f32_vrelu_ukernel__wasm_x4, VUnaryMicrokernelTester::OpType::ReLU);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRELU__WASM_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -686,10 +686,10 @@
.Test(xnn_f32_vrelu_ukernel__wasm_x8, VUnaryMicrokernelTester::OpType::ReLU);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRELU__WASMSIMD_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -728,10 +728,10 @@
.Test(xnn_f32_vrelu_ukernel__wasmsimd_x4, VUnaryMicrokernelTester::OpType::ReLU);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRELU__WASMSIMD_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -770,10 +770,10 @@
.Test(xnn_f32_vrelu_ukernel__wasmsimd_x8, VUnaryMicrokernelTester::OpType::ReLU);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRELU__WASMSIMD_X16, batch_eq_16) {
VUnaryMicrokernelTester()
.batch_size(16)
@@ -812,7 +812,7 @@
.Test(xnn_f32_vrelu_ukernel__wasmsimd_x16, VUnaryMicrokernelTester::OpType::ReLU);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
diff --git a/test/f32-vrndd.cc b/test/f32-vrndd.cc
index 662756b..66dcd2c 100644
--- a/test/f32-vrndd.cc
+++ b/test/f32-vrndd.cc
@@ -581,7 +581,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDD__WASMSIMD_ADDSUB_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -620,10 +620,10 @@
.Test(xnn_f32_vrndd_ukernel__wasmsimd_addsub_x4, VUnaryMicrokernelTester::OpType::RoundDown);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDD__WASMSIMD_ADDSUB_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -662,10 +662,10 @@
.Test(xnn_f32_vrndd_ukernel__wasmsimd_addsub_x8, VUnaryMicrokernelTester::OpType::RoundDown);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDD__WASMSIMD_CVT_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -704,10 +704,10 @@
.Test(xnn_f32_vrndd_ukernel__wasmsimd_cvt_x4, VUnaryMicrokernelTester::OpType::RoundDown);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDD__WASMSIMD_CVT_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -746,10 +746,10 @@
.Test(xnn_f32_vrndd_ukernel__wasmsimd_cvt_x8, VUnaryMicrokernelTester::OpType::RoundDown);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDD__WASMSIMD_NATIVE_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -788,10 +788,10 @@
.Test(xnn_f32_vrndd_ukernel__wasmsimd_native_x4, VUnaryMicrokernelTester::OpType::RoundDown);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDD__WASMSIMD_NATIVE_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -830,7 +830,7 @@
.Test(xnn_f32_vrndd_ukernel__wasmsimd_native_x8, VUnaryMicrokernelTester::OpType::RoundDown);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDD__SCALAR_LIBM_X1, batch_eq_1) {
diff --git a/test/f32-vrndne.cc b/test/f32-vrndne.cc
index c4bb1e7..3e173b1 100644
--- a/test/f32-vrndne.cc
+++ b/test/f32-vrndne.cc
@@ -581,7 +581,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDNE__WASMSIMD_ADDSUB_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -620,10 +620,10 @@
.Test(xnn_f32_vrndne_ukernel__wasmsimd_addsub_x4, VUnaryMicrokernelTester::OpType::RoundToNearestEven);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDNE__WASMSIMD_ADDSUB_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -662,10 +662,10 @@
.Test(xnn_f32_vrndne_ukernel__wasmsimd_addsub_x8, VUnaryMicrokernelTester::OpType::RoundToNearestEven);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDNE__WASMSIMD_NATIVE_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -704,10 +704,10 @@
.Test(xnn_f32_vrndne_ukernel__wasmsimd_native_x4, VUnaryMicrokernelTester::OpType::RoundToNearestEven);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDNE__WASMSIMD_NATIVE_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -746,7 +746,7 @@
.Test(xnn_f32_vrndne_ukernel__wasmsimd_native_x8, VUnaryMicrokernelTester::OpType::RoundToNearestEven);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDNE__SCALAR_LIBM_X1, batch_eq_1) {
diff --git a/test/f32-vrndu.cc b/test/f32-vrndu.cc
index 674335a..2b9dc5b 100644
--- a/test/f32-vrndu.cc
+++ b/test/f32-vrndu.cc
@@ -581,7 +581,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDU__WASMSIMD_ADDSUB_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -620,10 +620,10 @@
.Test(xnn_f32_vrndu_ukernel__wasmsimd_addsub_x4, VUnaryMicrokernelTester::OpType::RoundUp);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDU__WASMSIMD_ADDSUB_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -662,10 +662,10 @@
.Test(xnn_f32_vrndu_ukernel__wasmsimd_addsub_x8, VUnaryMicrokernelTester::OpType::RoundUp);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDU__WASMSIMD_CVT_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -704,10 +704,10 @@
.Test(xnn_f32_vrndu_ukernel__wasmsimd_cvt_x4, VUnaryMicrokernelTester::OpType::RoundUp);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDU__WASMSIMD_CVT_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -746,10 +746,10 @@
.Test(xnn_f32_vrndu_ukernel__wasmsimd_cvt_x8, VUnaryMicrokernelTester::OpType::RoundUp);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDU__WASMSIMD_NATIVE_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -788,10 +788,10 @@
.Test(xnn_f32_vrndu_ukernel__wasmsimd_native_x4, VUnaryMicrokernelTester::OpType::RoundUp);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDU__WASMSIMD_NATIVE_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -830,7 +830,7 @@
.Test(xnn_f32_vrndu_ukernel__wasmsimd_native_x8, VUnaryMicrokernelTester::OpType::RoundUp);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDU__SCALAR_LIBM_X1, batch_eq_1) {
diff --git a/test/f32-vrndz.cc b/test/f32-vrndz.cc
index 4c4d815..ab3b571 100644
--- a/test/f32-vrndz.cc
+++ b/test/f32-vrndz.cc
@@ -581,7 +581,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDZ__WASMSIMD_ADDSUB_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -620,10 +620,10 @@
.Test(xnn_f32_vrndz_ukernel__wasmsimd_addsub_x4, VUnaryMicrokernelTester::OpType::RoundTowardsZero);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDZ__WASMSIMD_ADDSUB_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -662,10 +662,10 @@
.Test(xnn_f32_vrndz_ukernel__wasmsimd_addsub_x8, VUnaryMicrokernelTester::OpType::RoundTowardsZero);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDZ__WASMSIMD_CVT_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -704,10 +704,10 @@
.Test(xnn_f32_vrndz_ukernel__wasmsimd_cvt_x4, VUnaryMicrokernelTester::OpType::RoundTowardsZero);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDZ__WASMSIMD_CVT_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -746,10 +746,10 @@
.Test(xnn_f32_vrndz_ukernel__wasmsimd_cvt_x8, VUnaryMicrokernelTester::OpType::RoundTowardsZero);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDZ__WASMSIMD_NATIVE_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -788,10 +788,10 @@
.Test(xnn_f32_vrndz_ukernel__wasmsimd_native_x4, VUnaryMicrokernelTester::OpType::RoundTowardsZero);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDZ__WASMSIMD_NATIVE_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -830,7 +830,7 @@
.Test(xnn_f32_vrndz_ukernel__wasmsimd_native_x8, VUnaryMicrokernelTester::OpType::RoundTowardsZero);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRNDZ__SCALAR_LIBM_X1, batch_eq_1) {
diff --git a/test/f32-vrsubc-minmax.cc b/test/f32-vrsubc-minmax.cc
index b11cbc3..2e70b08 100644
--- a/test/f32-vrsubc-minmax.cc
+++ b/test/f32-vrsubc-minmax.cc
@@ -554,7 +554,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_MINMAX__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -611,10 +611,10 @@
.Test(xnn_f32_vrsubc_minmax_ukernel__wasmsimd_arm_x4, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_MINMAX__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -671,10 +671,10 @@
.Test(xnn_f32_vrsubc_minmax_ukernel__wasmsimd_arm_x8, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_MINMAX__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -731,10 +731,10 @@
.Test(xnn_f32_vrsubc_minmax_ukernel__wasmsimd_arm_x16, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_MINMAX__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -791,10 +791,10 @@
.Test(xnn_f32_vrsubc_minmax_ukernel__wasmsimd_x86_x4, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_MINMAX__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -851,10 +851,10 @@
.Test(xnn_f32_vrsubc_minmax_ukernel__wasmsimd_x86_x8, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_MINMAX__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -911,10 +911,10 @@
.Test(xnn_f32_vrsubc_minmax_ukernel__wasmsimd_x86_x16, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_MINMAX__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -955,10 +955,10 @@
.Test(xnn_f32_vrsubc_minmax_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_MINMAX__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -1015,10 +1015,10 @@
.Test(xnn_f32_vrsubc_minmax_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_MINMAX__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -1075,10 +1075,10 @@
.Test(xnn_f32_vrsubc_minmax_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_MINMAX__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -1135,7 +1135,7 @@
.Test(xnn_f32_vrsubc_minmax_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vrsubc-relu.cc b/test/f32-vrsubc-relu.cc
index 6cadb14..e57ce91 100644
--- a/test/f32-vrsubc-relu.cc
+++ b/test/f32-vrsubc-relu.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_RELU__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vrsubc_relu_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_RELU__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vrsubc_relu_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_RELU__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,10 +141,10 @@
.Test(xnn_f32_vrsubc_relu_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_RELU__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -167,10 +167,10 @@
.Test(xnn_f32_vrsubc_relu_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_RELU__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -209,10 +209,10 @@
.Test(xnn_f32_vrsubc_relu_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_RELU__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -251,10 +251,10 @@
.Test(xnn_f32_vrsubc_relu_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_RELU__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -293,7 +293,7 @@
.Test(xnn_f32_vrsubc_relu_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC_RELU__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vrsubc.cc b/test/f32-vrsubc.cc
index 92a12a4..64fb08a 100644
--- a/test/f32-vrsubc.cc
+++ b/test/f32-vrsubc.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vrsubc_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vrsubc_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,7 +141,7 @@
.Test(xnn_f32_vrsubc_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::RSubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VRSUBC__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vsigmoid.cc b/test/f32-vsigmoid.cc
index 790976d..0cba51b 100644
--- a/test/f32-vsigmoid.cc
+++ b/test/f32-vsigmoid.cc
@@ -9981,7 +9981,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_P5_DIV_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -10020,10 +10020,10 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_p5_div_x4, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_P5_DIV_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -10062,10 +10062,10 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_p5_div_x8, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_P5_DIV_X12, batch_eq_12) {
VUnaryMicrokernelTester()
.batch_size(12)
@@ -10104,10 +10104,10 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_p5_div_x12, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_P5_DIV_X16, batch_eq_16) {
VUnaryMicrokernelTester()
.batch_size(16)
@@ -10146,10 +10146,10 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_p5_div_x16, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_P5_DIV_X20, batch_eq_20) {
VUnaryMicrokernelTester()
.batch_size(20)
@@ -10188,10 +10188,10 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_p5_div_x20, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_P5_DIV_X24, batch_eq_24) {
VUnaryMicrokernelTester()
.batch_size(24)
@@ -10230,10 +10230,10 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_p5_div_x24, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_LUT64_P2_DIV_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -10272,10 +10272,10 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_lut64_p2_div_x4, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_LUT64_P2_DIV_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -10314,10 +10314,10 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_lut64_p2_div_x8, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_LUT64_P2_DIV_X12, batch_eq_12) {
VUnaryMicrokernelTester()
.batch_size(12)
@@ -10356,10 +10356,10 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_lut64_p2_div_x12, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_LUT64_P2_DIV_X16, batch_eq_16) {
VUnaryMicrokernelTester()
.batch_size(16)
@@ -10398,10 +10398,10 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_lut64_p2_div_x16, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_LUT64_P2_DIV_X20, batch_eq_20) {
VUnaryMicrokernelTester()
.batch_size(20)
@@ -10440,10 +10440,10 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_lut64_p2_div_x20, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__WASMSIMD_LUT64_P2_DIV_X24, batch_eq_24) {
VUnaryMicrokernelTester()
.batch_size(24)
@@ -10482,7 +10482,7 @@
.Test(xnn_f32_vsigmoid_ukernel__wasmsimd_lut64_p2_div_x24, VUnaryMicrokernelTester::OpType::Sigmoid);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSIGMOID__SCALAR_LUT2048_P1_DIV_X1, batch_eq_1) {
diff --git a/test/f32-vsqr.cc b/test/f32-vsqr.cc
index 5ed0864..168a2e7 100644
--- a/test/f32-vsqr.cc
+++ b/test/f32-vsqr.cc
@@ -393,7 +393,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQR__WASMSIMD_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -432,10 +432,10 @@
.Test(xnn_f32_vsqr_ukernel__wasmsimd_x4, VUnaryMicrokernelTester::OpType::Square);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQR__WASMSIMD_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -474,7 +474,7 @@
.Test(xnn_f32_vsqr_ukernel__wasmsimd_x8, VUnaryMicrokernelTester::OpType::Square);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQR__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vsqrdiff.cc b/test/f32-vsqrdiff.cc
index d3b979f..39e681e 100644
--- a/test/f32-vsqrdiff.cc
+++ b/test/f32-vsqrdiff.cc
@@ -562,7 +562,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQRDIFF__WASMSIMD_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -620,10 +620,10 @@
.Test(xnn_f32_vsqrdiff_ukernel__wasmsimd_x4, VBinaryMicrokernelTester::OpType::SqrDiff);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQRDIFF__WASMSIMD_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -681,10 +681,10 @@
.Test(xnn_f32_vsqrdiff_ukernel__wasmsimd_x8, VBinaryMicrokernelTester::OpType::SqrDiff);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQRDIFF__WASMSIMD_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -742,7 +742,7 @@
.Test(xnn_f32_vsqrdiff_ukernel__wasmsimd_x16, VBinaryMicrokernelTester::OpType::SqrDiff);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQRDIFF__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vsqrdiffc.cc b/test/f32-vsqrdiffc.cc
index bfc06e3..96d0aca 100644
--- a/test/f32-vsqrdiffc.cc
+++ b/test/f32-vsqrdiffc.cc
@@ -394,7 +394,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQRDIFFC__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -433,10 +433,10 @@
.Test(xnn_f32_vsqrdiffc_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::SqrDiffC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQRDIFFC__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -475,10 +475,10 @@
.Test(xnn_f32_vsqrdiffc_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::SqrDiffC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQRDIFFC__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -517,7 +517,7 @@
.Test(xnn_f32_vsqrdiffc_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::SqrDiffC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQRDIFFC__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vsqrt.cc b/test/f32-vsqrt.cc
index ae9ef8e..b581759 100644
--- a/test/f32-vsqrt.cc
+++ b/test/f32-vsqrt.cc
@@ -1991,7 +1991,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQRT__WASMSIMD_SQRT_X4, batch_eq_4) {
VUnaryMicrokernelTester()
.batch_size(4)
@@ -2030,10 +2030,10 @@
.Test(xnn_f32_vsqrt_ukernel__wasmsimd_sqrt_x4, VUnaryMicrokernelTester::OpType::SquareRoot);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQRT__WASMSIMD_SQRT_X8, batch_eq_8) {
VUnaryMicrokernelTester()
.batch_size(8)
@@ -2072,7 +2072,7 @@
.Test(xnn_f32_vsqrt_ukernel__wasmsimd_sqrt_x8, VUnaryMicrokernelTester::OpType::SquareRoot);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSQRT__SCALAR_SQRT_X1, batch_eq_1) {
diff --git a/test/f32-vsub-minmax.cc b/test/f32-vsub-minmax.cc
index 5e632e4..e4103d4 100644
--- a/test/f32-vsub-minmax.cc
+++ b/test/f32-vsub-minmax.cc
@@ -722,7 +722,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_MINMAX__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -798,10 +798,10 @@
.Test(xnn_f32_vsub_minmax_ukernel__wasmsimd_arm_x4, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_MINMAX__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -877,10 +877,10 @@
.Test(xnn_f32_vsub_minmax_ukernel__wasmsimd_arm_x8, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_MINMAX__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -956,10 +956,10 @@
.Test(xnn_f32_vsub_minmax_ukernel__wasmsimd_arm_x16, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_MINMAX__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -1035,10 +1035,10 @@
.Test(xnn_f32_vsub_minmax_ukernel__wasmsimd_x86_x4, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_MINMAX__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -1114,10 +1114,10 @@
.Test(xnn_f32_vsub_minmax_ukernel__wasmsimd_x86_x8, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_MINMAX__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -1193,10 +1193,10 @@
.Test(xnn_f32_vsub_minmax_ukernel__wasmsimd_x86_x16, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_MINMAX__WASM_X1, batch_eq_1) {
VBinaryMicrokernelTester()
.batch_size(1)
@@ -1256,10 +1256,10 @@
.Test(xnn_f32_vsub_minmax_ukernel__wasm_x1, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_MINMAX__WASM_X2, batch_eq_2) {
VBinaryMicrokernelTester()
.batch_size(2)
@@ -1335,10 +1335,10 @@
.Test(xnn_f32_vsub_minmax_ukernel__wasm_x2, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_MINMAX__WASM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -1414,10 +1414,10 @@
.Test(xnn_f32_vsub_minmax_ukernel__wasm_x4, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_MINMAX__WASM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -1493,7 +1493,7 @@
.Test(xnn_f32_vsub_minmax_ukernel__wasm_x8, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vsub-relu.cc b/test/f32-vsub-relu.cc
index 2ff41e4..ace7582 100644
--- a/test/f32-vsub-relu.cc
+++ b/test/f32-vsub-relu.cc
@@ -18,7 +18,7 @@
#include "vbinary-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_RELU__WASMSIMD_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -76,10 +76,10 @@
.Test(xnn_f32_vsub_relu_ukernel__wasmsimd_x4, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_RELU__WASMSIMD_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -137,10 +137,10 @@
.Test(xnn_f32_vsub_relu_ukernel__wasmsimd_x8, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_RELU__WASMSIMD_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -198,10 +198,10 @@
.Test(xnn_f32_vsub_relu_ukernel__wasmsimd_x16, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_RELU__WASM_X1, batch_eq_1) {
VBinaryMicrokernelTester()
.batch_size(1)
@@ -243,10 +243,10 @@
.Test(xnn_f32_vsub_relu_ukernel__wasm_x1, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_RELU__WASM_X2, batch_eq_2) {
VBinaryMicrokernelTester()
.batch_size(2)
@@ -304,10 +304,10 @@
.Test(xnn_f32_vsub_relu_ukernel__wasm_x2, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_RELU__WASM_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -365,10 +365,10 @@
.Test(xnn_f32_vsub_relu_ukernel__wasm_x4, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_RELU__WASM_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -426,7 +426,7 @@
.Test(xnn_f32_vsub_relu_ukernel__wasm_x8, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB_RELU__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vsub.cc b/test/f32-vsub.cc
index ef37861..62ea638 100644
--- a/test/f32-vsub.cc
+++ b/test/f32-vsub.cc
@@ -18,7 +18,7 @@
#include "vbinary-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB__WASMSIMD_X4, batch_eq_4) {
VBinaryMicrokernelTester()
.batch_size(4)
@@ -76,10 +76,10 @@
.Test(xnn_f32_vsub_ukernel__wasmsimd_x4, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB__WASMSIMD_X8, batch_eq_8) {
VBinaryMicrokernelTester()
.batch_size(8)
@@ -137,10 +137,10 @@
.Test(xnn_f32_vsub_ukernel__wasmsimd_x8, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB__WASMSIMD_X16, batch_eq_16) {
VBinaryMicrokernelTester()
.batch_size(16)
@@ -198,7 +198,7 @@
.Test(xnn_f32_vsub_ukernel__wasmsimd_x16, VBinaryMicrokernelTester::OpType::Sub);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUB__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vsubc-minmax.cc b/test/f32-vsubc-minmax.cc
index ab6f12e..35edcaf 100644
--- a/test/f32-vsubc-minmax.cc
+++ b/test/f32-vsubc-minmax.cc
@@ -554,7 +554,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_MINMAX__WASMSIMD_ARM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -611,10 +611,10 @@
.Test(xnn_f32_vsubc_minmax_ukernel__wasmsimd_arm_x4, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_MINMAX__WASMSIMD_ARM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -671,10 +671,10 @@
.Test(xnn_f32_vsubc_minmax_ukernel__wasmsimd_arm_x8, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_MINMAX__WASMSIMD_ARM_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -731,10 +731,10 @@
.Test(xnn_f32_vsubc_minmax_ukernel__wasmsimd_arm_x16, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_MINMAX__WASMSIMD_X86_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -791,10 +791,10 @@
.Test(xnn_f32_vsubc_minmax_ukernel__wasmsimd_x86_x4, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_MINMAX__WASMSIMD_X86_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -851,10 +851,10 @@
.Test(xnn_f32_vsubc_minmax_ukernel__wasmsimd_x86_x8, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_MINMAX__WASMSIMD_X86_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -911,10 +911,10 @@
.Test(xnn_f32_vsubc_minmax_ukernel__wasmsimd_x86_x16, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_MINMAX__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -955,10 +955,10 @@
.Test(xnn_f32_vsubc_minmax_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_MINMAX__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -1015,10 +1015,10 @@
.Test(xnn_f32_vsubc_minmax_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_MINMAX__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -1075,10 +1075,10 @@
.Test(xnn_f32_vsubc_minmax_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_MINMAX__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -1135,7 +1135,7 @@
.Test(xnn_f32_vsubc_minmax_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vsubc-relu.cc b/test/f32-vsubc-relu.cc
index b0a2186..4599cba 100644
--- a/test/f32-vsubc-relu.cc
+++ b/test/f32-vsubc-relu.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_RELU__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vsubc_relu_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_RELU__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vsubc_relu_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_RELU__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,10 +141,10 @@
.Test(xnn_f32_vsubc_relu_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_RELU__WASM_X1, batch_eq_1) {
VBinaryCMicrokernelTester()
.batch_size(1)
@@ -167,10 +167,10 @@
.Test(xnn_f32_vsubc_relu_ukernel__wasm_x1, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_RELU__WASM_X2, batch_eq_2) {
VBinaryCMicrokernelTester()
.batch_size(2)
@@ -209,10 +209,10 @@
.Test(xnn_f32_vsubc_relu_ukernel__wasm_x2, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_RELU__WASM_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -251,10 +251,10 @@
.Test(xnn_f32_vsubc_relu_ukernel__wasm_x4, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_RELU__WASM_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -293,7 +293,7 @@
.Test(xnn_f32_vsubc_relu_ukernel__wasm_x8, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC_RELU__SCALAR_X1, batch_eq_1) {
diff --git a/test/f32-vsubc.cc b/test/f32-vsubc.cc
index 0938c5a..0c2d6bc 100644
--- a/test/f32-vsubc.cc
+++ b/test/f32-vsubc.cc
@@ -18,7 +18,7 @@
#include "vbinaryc-microkernel-tester.h"
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC__WASMSIMD_X4, batch_eq_4) {
VBinaryCMicrokernelTester()
.batch_size(4)
@@ -57,10 +57,10 @@
.Test(xnn_f32_vsubc_ukernel__wasmsimd_x4, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC__WASMSIMD_X8, batch_eq_8) {
VBinaryCMicrokernelTester()
.batch_size(8)
@@ -99,10 +99,10 @@
.Test(xnn_f32_vsubc_ukernel__wasmsimd_x8, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC__WASMSIMD_X16, batch_eq_16) {
VBinaryCMicrokernelTester()
.batch_size(16)
@@ -141,7 +141,7 @@
.Test(xnn_f32_vsubc_ukernel__wasmsimd_x16, VBinaryCMicrokernelTester::OpType::SubC);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(F32_VSUBC__SCALAR_X1, batch_eq_1) {
diff --git a/test/qc8-dwconv-minmax-fp32.cc b/test/qc8-dwconv-minmax-fp32.cc
index 289c65d..ef7d442 100644
--- a/test/qc8-dwconv-minmax-fp32.cc
+++ b/test/qc8-dwconv-minmax-fp32.cc
@@ -10808,7 +10808,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP8X9__WASMSIMD_MUL16, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -10976,10 +10976,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP16X9__WASMSIMD_MUL16, c_eq_16) {
DWConvMicrokernelTester()
.cr(16)
@@ -11147,10 +11147,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP24X9__WASMSIMD_MUL16, c_eq_24) {
DWConvMicrokernelTester()
.cr(24)
@@ -11318,10 +11318,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP8X9__WASMSIMD_MUL16_ADD16, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -11489,10 +11489,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP16X9__WASMSIMD_MUL16_ADD16, c_eq_16) {
DWConvMicrokernelTester()
.cr(16)
@@ -11660,10 +11660,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP24X9__WASMSIMD_MUL16_ADD16, c_eq_24) {
DWConvMicrokernelTester()
.cr(24)
@@ -11831,7 +11831,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP1X9__SCALAR_LRINT, c_eq_1) {
@@ -23546,7 +23546,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP8X25__WASMSIMD_MUL16, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -23714,10 +23714,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP16X25__WASMSIMD_MUL16, c_eq_16) {
DWConvMicrokernelTester()
.cr(16)
@@ -23885,10 +23885,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP24X25__WASMSIMD_MUL16, c_eq_24) {
DWConvMicrokernelTester()
.cr(24)
@@ -24056,10 +24056,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP8X25__WASMSIMD_MUL16_ADD16, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -24227,10 +24227,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP16X25__WASMSIMD_MUL16_ADD16, c_eq_16) {
DWConvMicrokernelTester()
.cr(16)
@@ -24398,10 +24398,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP24X25__WASMSIMD_MUL16_ADD16, c_eq_24) {
DWConvMicrokernelTester()
.cr(24)
@@ -24569,7 +24569,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_DWCONV_MINMAX_FP32_UP1X25__SCALAR_LRINT, c_eq_1) {
diff --git a/test/qc8-gemm-minmax-fp32.cc b/test/qc8-gemm-minmax-fp32.cc
index 3932822..093388b 100644
--- a/test/qc8-gemm-minmax-fp32.cc
+++ b/test/qc8-gemm-minmax-fp32.cc
@@ -62941,7 +62941,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -63367,10 +63367,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -63796,10 +63796,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -64225,10 +64225,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -64654,10 +64654,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -65083,10 +65083,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -65512,10 +65512,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -65941,10 +65941,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -66370,10 +66370,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_1X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -66799,10 +66799,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_1x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_2X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -67228,10 +67228,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_2x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_3X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -67657,10 +67657,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_3x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_4X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -68086,10 +68086,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_4x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_1X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -68515,10 +68515,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_1x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_2X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -68944,10 +68944,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_2x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_3X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -69373,10 +69373,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_3x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_4X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -69802,10 +69802,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_4x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -70231,10 +70231,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -70660,10 +70660,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -71089,10 +71089,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -71518,10 +71518,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -71947,10 +71947,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -72376,10 +72376,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -72805,10 +72805,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -73234,10 +73234,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -73663,10 +73663,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -74092,10 +74092,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -74521,10 +74521,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -74950,10 +74950,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -75379,10 +75379,10 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -75808,7 +75808,7 @@
.cm_stride(7)
.Test(xnn_qc8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_GEMM_MINMAX_FP32_1X2__SCALAR_LRINT, k_eq_1) {
diff --git a/test/qc8-igemm-minmax-fp32.cc b/test/qc8-igemm-minmax-fp32.cc
index 3cd9824..7052ea1 100644
--- a/test/qc8-igemm-minmax-fp32.cc
+++ b/test/qc8-igemm-minmax-fp32.cc
@@ -60394,7 +60394,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -60832,10 +60832,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -61273,10 +61273,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -61714,10 +61714,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -62155,10 +62155,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -62596,10 +62596,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -63037,10 +63037,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -63478,10 +63478,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -63919,10 +63919,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_1X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -64360,10 +64360,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_1x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_2X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -64801,10 +64801,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_2x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_3X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -65242,10 +65242,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_3x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_4X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -65683,10 +65683,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_4x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_1X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -66124,10 +66124,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_1x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_2X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -66565,10 +66565,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_2x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_3X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -67006,10 +67006,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_3x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_4X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -67447,10 +67447,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_4x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -67888,10 +67888,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -68329,10 +68329,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -68770,10 +68770,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -69211,10 +69211,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -69652,10 +69652,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -70093,10 +70093,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -70534,10 +70534,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -70975,10 +70975,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -71416,10 +71416,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -71857,10 +71857,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -72298,10 +72298,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -72739,10 +72739,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -73180,10 +73180,10 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -73621,7 +73621,7 @@
.cm_stride(7)
.Test(xnn_qc8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_minmax_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QC8_IGEMM_MINMAX_FP32_1X2__SCALAR_LRINT, k_eq_1) {
diff --git a/test/qs8-dwconv-minmax-fp32.cc b/test/qs8-dwconv-minmax-fp32.cc
index 10c88d3..a7307fb 100644
--- a/test/qs8-dwconv-minmax-fp32.cc
+++ b/test/qs8-dwconv-minmax-fp32.cc
@@ -8576,7 +8576,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP8X9__WASMSIMD_MUL16, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -8744,10 +8744,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP16X9__WASMSIMD_MUL16, c_eq_16) {
DWConvMicrokernelTester()
.cr(16)
@@ -8915,10 +8915,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP24X9__WASMSIMD_MUL16, c_eq_24) {
DWConvMicrokernelTester()
.cr(24)
@@ -9086,10 +9086,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP8X9__WASMSIMD_MUL16_ADD16, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -9257,10 +9257,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP16X9__WASMSIMD_MUL16_ADD16, c_eq_16) {
DWConvMicrokernelTester()
.cr(16)
@@ -9428,10 +9428,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP24X9__WASMSIMD_MUL16_ADD16, c_eq_24) {
DWConvMicrokernelTester()
.cr(24)
@@ -9599,7 +9599,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP1X9__SCALAR_LRINT, c_eq_1) {
@@ -19082,7 +19082,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP8X25__WASMSIMD_MUL16, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -19250,10 +19250,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP16X25__WASMSIMD_MUL16, c_eq_16) {
DWConvMicrokernelTester()
.cr(16)
@@ -19421,10 +19421,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP24X25__WASMSIMD_MUL16, c_eq_24) {
DWConvMicrokernelTester()
.cr(24)
@@ -19592,10 +19592,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP8X25__WASMSIMD_MUL16_ADD16, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -19763,10 +19763,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP16X25__WASMSIMD_MUL16_ADD16, c_eq_16) {
DWConvMicrokernelTester()
.cr(16)
@@ -19934,10 +19934,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP24X25__WASMSIMD_MUL16_ADD16, c_eq_24) {
DWConvMicrokernelTester()
.cr(24)
@@ -20105,7 +20105,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_DWCONV_MINMAX_FP32_UP1X25__SCALAR_LRINT, c_eq_1) {
diff --git a/test/qs8-f32-vcvt.cc b/test/qs8-f32-vcvt.cc
index 6cb814f..dffb0a2 100644
--- a/test/qs8-f32-vcvt.cc
+++ b/test/qs8-f32-vcvt.cc
@@ -1197,7 +1197,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_F32_VCVT__WASMSIMD_X8, batch_eq_8) {
VCvtMicrokernelTester()
.batch_size(8)
@@ -1247,10 +1247,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_F32_VCVT__WASMSIMD_X16, batch_eq_16) {
VCvtMicrokernelTester()
.batch_size(16)
@@ -1300,10 +1300,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_F32_VCVT__WASMSIMD_X24, batch_eq_24) {
VCvtMicrokernelTester()
.batch_size(24)
@@ -1353,10 +1353,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_F32_VCVT__WASMSIMD_X32, batch_eq_32) {
VCvtMicrokernelTester()
.batch_size(32)
@@ -1406,7 +1406,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_F32_VCVT__SCALAR_X1, batch_eq_1) {
diff --git a/test/qs8-gavgpool-minmax.cc b/test/qs8-gavgpool-minmax.cc
index ba3741b..aa761ed 100644
--- a/test/qs8-gavgpool-minmax.cc
+++ b/test/qs8-gavgpool-minmax.cc
@@ -5519,7 +5519,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GAVGPOOL_MINMAX_7X__WASMSIMD_C8_ACC2, channels_eq_8_fulltile) {
GAvgPoolMicrokernelTester()
.rows(7)
@@ -5659,10 +5659,10 @@
.Test(xnn_qs8_gavgpool_minmax_ukernel_7x__wasmsimd_c8_acc2);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GAVGPOOL_MINMAX_7X__WASMSIMD_C16_ACC2, channels_eq_16_fulltile) {
GAvgPoolMicrokernelTester()
.rows(7)
@@ -5802,10 +5802,10 @@
.Test(xnn_qs8_gavgpool_minmax_ukernel_7x__wasmsimd_c16_acc2);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GAVGPOOL_MINMAX_7X__WASMSIMD_C24_ACC2, channels_eq_24_fulltile) {
GAvgPoolMicrokernelTester()
.rows(7)
@@ -5945,10 +5945,10 @@
.Test(xnn_qs8_gavgpool_minmax_ukernel_7x__wasmsimd_c24_acc2);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GAVGPOOL_MINMAX_7P7X__WASMSIMD_C8_ACC2, channels_eq_8_2pass_fulltile) {
GAvgPoolMicrokernelTester()
.rows(14)
@@ -6186,10 +6186,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GAVGPOOL_MINMAX_7P7X__WASMSIMD_C16_ACC2, channels_eq_16_2pass_fulltile) {
GAvgPoolMicrokernelTester()
.rows(14)
@@ -6427,10 +6427,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GAVGPOOL_MINMAX_7P7X__WASMSIMD_C24_ACC2, channels_eq_24_2pass_fulltile) {
GAvgPoolMicrokernelTester()
.rows(14)
@@ -6668,7 +6668,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GAVGPOOL_MINMAX_7X__SCALAR_C1, channels_eq_1_fulltile) {
diff --git a/test/qs8-gemm-minmax-fp32.cc b/test/qs8-gemm-minmax-fp32.cc
index 6e506e9..008d507 100644
--- a/test/qs8-gemm-minmax-fp32.cc
+++ b/test/qs8-gemm-minmax-fp32.cc
@@ -76528,7 +76528,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -76954,10 +76954,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -77383,10 +77383,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -77812,10 +77812,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -78241,10 +78241,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -78670,10 +78670,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -79099,10 +79099,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -79528,10 +79528,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -79957,10 +79957,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_XW_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2, k_eq_8) {
GemmMicrokernelTester()
.extended_weights(true)
@@ -80385,10 +80385,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_xw_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_XW_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2, k_eq_8) {
GemmMicrokernelTester()
.extended_weights(true)
@@ -80813,10 +80813,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_xw_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_XW_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2, k_eq_8) {
GemmMicrokernelTester()
.extended_weights(true)
@@ -81241,10 +81241,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_xw_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_XW_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2, k_eq_8) {
GemmMicrokernelTester()
.extended_weights(true)
@@ -81669,10 +81669,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_xw_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_1X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -82098,10 +82098,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_1x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_2X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -82527,10 +82527,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_2x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_3X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -82956,10 +82956,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_3x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_4X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -83385,10 +83385,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_4x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_1X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -83814,10 +83814,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_1x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_2X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -84243,10 +84243,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_2x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_3X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -84672,10 +84672,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_3x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_4X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -85101,10 +85101,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_4x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -85530,10 +85530,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -85959,10 +85959,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -86388,10 +86388,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -86817,10 +86817,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -87246,10 +87246,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -87675,10 +87675,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -88104,10 +88104,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -88533,10 +88533,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_XW_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2, k_eq_8) {
GemmMicrokernelTester()
.extended_weights(true)
@@ -88961,10 +88961,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_xw_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_XW_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2, k_eq_8) {
GemmMicrokernelTester()
.extended_weights(true)
@@ -89389,10 +89389,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_xw_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_XW_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2, k_eq_8) {
GemmMicrokernelTester()
.extended_weights(true)
@@ -89817,10 +89817,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_xw_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_XW_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2, k_eq_8) {
GemmMicrokernelTester()
.extended_weights(true)
@@ -90245,10 +90245,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_xw_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -90674,10 +90674,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -91103,10 +91103,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -91532,10 +91532,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -91961,10 +91961,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -92390,10 +92390,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -92819,10 +92819,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_XW_MINMAX_FP32_1X4C8__WASMSIMD_MUL16, k_eq_8) {
GemmMicrokernelTester()
.extended_weights(true)
@@ -93247,10 +93247,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_xw_minmax_fp32_ukernel_1x4c8__wasmsimd_mul16, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_XW_MINMAX_FP32_2X4C8__WASMSIMD_MUL16, k_eq_8) {
GemmMicrokernelTester()
.extended_weights(true)
@@ -93675,10 +93675,10 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_xw_minmax_fp32_ukernel_2x4c8__wasmsimd_mul16, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_XW_MINMAX_FP32_3X4C8__WASMSIMD_MUL16, k_eq_8) {
GemmMicrokernelTester()
.extended_weights(true)
@@ -94103,7 +94103,7 @@
.cm_stride(7)
.Test(xnn_qs8_gemm_xw_minmax_fp32_ukernel_3x4c8__wasmsimd_mul16, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_GEMM_MINMAX_FP32_1X2__SCALAR_LRINT, k_eq_1) {
diff --git a/test/qs8-igemm-minmax-fp32.cc b/test/qs8-igemm-minmax-fp32.cc
index 390c438..d3f9940 100644
--- a/test/qs8-igemm-minmax-fp32.cc
+++ b/test/qs8-igemm-minmax-fp32.cc
@@ -60862,7 +60862,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -61300,10 +61300,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -61741,10 +61741,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -62182,10 +62182,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -62623,10 +62623,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -63064,10 +63064,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -63505,10 +63505,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -63946,10 +63946,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -64387,10 +64387,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_1X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -64828,10 +64828,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_1x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_2X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -65269,10 +65269,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_2x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_3X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -65710,10 +65710,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_3x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_4X4C2S4__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -66151,10 +66151,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_4x4c2s4__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_1X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -66592,10 +66592,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_1x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_2X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -67033,10 +67033,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_2x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_3X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -67474,10 +67474,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_3x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_4X4C2S4__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -67915,10 +67915,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_4x4c2s4__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -68356,10 +68356,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -68797,10 +68797,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -69238,10 +69238,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -69679,10 +69679,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -70120,10 +70120,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -70561,10 +70561,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -71002,10 +71002,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -71443,10 +71443,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -71884,10 +71884,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -72325,10 +72325,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL16_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -72766,10 +72766,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul16_ld64, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -73207,10 +73207,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -73648,10 +73648,10 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL16_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -74089,7 +74089,7 @@
.cm_stride(7)
.Test(xnn_qs8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul16_ld128, xnn_init_qs8_conv_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_IGEMM_MINMAX_FP32_1X2__SCALAR_LRINT, k_eq_1) {
diff --git a/test/qs8-vadd-minmax.cc b/test/qs8-vadd-minmax.cc
index d197800..0b4351a 100644
--- a/test/qs8-vadd-minmax.cc
+++ b/test/qs8-vadd-minmax.cc
@@ -5778,7 +5778,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VADD_MINMAX__WASMSIMD_X8, batch_eq_8) {
VAddMicrokernelTester()
.batch_size(8)
@@ -5920,10 +5920,10 @@
.Test(xnn_qs8_vadd_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VADD_MINMAX__WASMSIMD_X16, batch_eq_16) {
VAddMicrokernelTester()
.batch_size(16)
@@ -6065,10 +6065,10 @@
.Test(xnn_qs8_vadd_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VADD_MINMAX__WASMSIMD_X24, batch_eq_24) {
VAddMicrokernelTester()
.batch_size(24)
@@ -6210,10 +6210,10 @@
.Test(xnn_qs8_vadd_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VADD_MINMAX__WASMSIMD_X32, batch_eq_32) {
VAddMicrokernelTester()
.batch_size(32)
@@ -6355,7 +6355,7 @@
.Test(xnn_qs8_vadd_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VADD_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/qs8-vaddc-minmax.cc b/test/qs8-vaddc-minmax.cc
index d3f1290..b4fe90b 100644
--- a/test/qs8-vaddc-minmax.cc
+++ b/test/qs8-vaddc-minmax.cc
@@ -5022,7 +5022,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VADDC_MINMAX__WASMSIMD_X8, batch_eq_8) {
VAddCMicrokernelTester()
.batch_size(8)
@@ -5145,10 +5145,10 @@
.Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qs8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VADDC_MINMAX__WASMSIMD_X16, batch_eq_16) {
VAddCMicrokernelTester()
.batch_size(16)
@@ -5271,10 +5271,10 @@
.Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qs8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VADDC_MINMAX__WASMSIMD_X24, batch_eq_24) {
VAddCMicrokernelTester()
.batch_size(24)
@@ -5397,10 +5397,10 @@
.Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x24, xnn_init_qs8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VADDC_MINMAX__WASMSIMD_X32, batch_eq_32) {
VAddCMicrokernelTester()
.batch_size(32)
@@ -5523,7 +5523,7 @@
.Test(xnn_qs8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qs8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VADDC_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/qs8-vmul-minmax-fp32.cc b/test/qs8-vmul-minmax-fp32.cc
index 69b975b..fd2c907 100644
--- a/test/qs8-vmul-minmax-fp32.cc
+++ b/test/qs8-vmul-minmax-fp32.cc
@@ -1938,7 +1938,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VMUL_MINMAX_FP32__WASMSIMD_MUL32_LD64_X8, batch_eq_8) {
VMulMicrokernelTester()
.batch_size(8)
@@ -2080,10 +2080,10 @@
.Test(xnn_qs8_vmul_minmax_fp32_ukernel__wasmsimd_mul32_ld64_x8, xnn_init_qs8_mul_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VMUL_MINMAX_FP32__WASMSIMD_MUL32_LD64_X16, batch_eq_16) {
VMulMicrokernelTester()
.batch_size(16)
@@ -2225,7 +2225,7 @@
.Test(xnn_qs8_vmul_minmax_fp32_ukernel__wasmsimd_mul32_ld64_x16, xnn_init_qs8_mul_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VMUL_MINMAX_FP32__SCALAR_X1, batch_eq_1) {
diff --git a/test/qs8-vmulc-minmax-fp32.cc b/test/qs8-vmulc-minmax-fp32.cc
index d746c5a..ec6dcac 100644
--- a/test/qs8-vmulc-minmax-fp32.cc
+++ b/test/qs8-vmulc-minmax-fp32.cc
@@ -1686,7 +1686,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VMULC_MINMAX_FP32__WASMSIMD_MUL32_LD64_X8, batch_eq_8) {
VMulCMicrokernelTester()
.batch_size(8)
@@ -1809,10 +1809,10 @@
.Test(xnn_qs8_vmulc_minmax_fp32_ukernel__wasmsimd_mul32_ld64_x8, xnn_init_qs8_mul_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VMULC_MINMAX_FP32__WASMSIMD_MUL32_LD64_X16, batch_eq_16) {
VMulCMicrokernelTester()
.batch_size(16)
@@ -1935,7 +1935,7 @@
.Test(xnn_qs8_vmulc_minmax_fp32_ukernel__wasmsimd_mul32_ld64_x16, xnn_init_qs8_mul_minmax_fp32_wasmsimd_params, xnn_init_qs8_requantization_fp32_params, xnn_qs8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QS8_VMULC_MINMAX_FP32__SCALAR_X1, batch_eq_1) {
diff --git a/test/qu8-dwconv-minmax-fp32.cc b/test/qu8-dwconv-minmax-fp32.cc
index 0dffbd2..80a30da 100644
--- a/test/qu8-dwconv-minmax-fp32.cc
+++ b/test/qu8-dwconv-minmax-fp32.cc
@@ -5370,7 +5370,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_DWCONV_MINMAX_FP32_UP8X9__WASMSIMD_MUL16, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -5564,10 +5564,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__WASMSIMD_MUL16, c_eq_16) {
DWConvMicrokernelTester()
.cr(16)
@@ -5761,10 +5761,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_DWCONV_MINMAX_FP32_UP24X9__WASMSIMD_MUL16, c_eq_24) {
DWConvMicrokernelTester()
.cr(24)
@@ -5958,7 +5958,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_DWCONV_MINMAX_FP32_UP1X9__SCALAR_LRINT, c_eq_1) {
@@ -12391,7 +12391,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_DWCONV_MINMAX_FP32_UP8X25__WASMSIMD_MUL16, c_eq_8) {
DWConvMicrokernelTester()
.cr(8)
@@ -12585,10 +12585,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__WASMSIMD_MUL16, c_eq_16) {
DWConvMicrokernelTester()
.cr(16)
@@ -12782,10 +12782,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_DWCONV_MINMAX_FP32_UP24X25__WASMSIMD_MUL16, c_eq_24) {
DWConvMicrokernelTester()
.cr(24)
@@ -12979,7 +12979,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_DWCONV_MINMAX_FP32_UP1X25__SCALAR_LRINT, c_eq_1) {
diff --git a/test/qu8-f32-vcvt.cc b/test/qu8-f32-vcvt.cc
index 058f687..64398a4 100644
--- a/test/qu8-f32-vcvt.cc
+++ b/test/qu8-f32-vcvt.cc
@@ -1197,7 +1197,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_F32_VCVT__WASMSIMD_X8, batch_eq_8) {
VCvtMicrokernelTester()
.batch_size(8)
@@ -1247,10 +1247,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_F32_VCVT__WASMSIMD_X16, batch_eq_16) {
VCvtMicrokernelTester()
.batch_size(16)
@@ -1300,10 +1300,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_F32_VCVT__WASMSIMD_X24, batch_eq_24) {
VCvtMicrokernelTester()
.batch_size(24)
@@ -1353,10 +1353,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_F32_VCVT__WASMSIMD_X32, batch_eq_32) {
VCvtMicrokernelTester()
.batch_size(32)
@@ -1406,7 +1406,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_F32_VCVT__SCALAR_X1, batch_eq_1) {
diff --git a/test/qu8-gemm-minmax-fp32.cc b/test/qu8-gemm-minmax-fp32.cc
index b69bbd2..cc5c89b 100644
--- a/test/qu8-gemm-minmax-fp32.cc
+++ b/test/qu8-gemm-minmax-fp32.cc
@@ -37392,7 +37392,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -37864,10 +37864,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -38339,10 +38339,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -38814,10 +38814,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -39289,10 +39289,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -39764,10 +39764,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -40239,10 +40239,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -40714,10 +40714,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -41189,10 +41189,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -41664,10 +41664,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -42139,10 +42139,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -42614,10 +42614,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -43089,10 +43089,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -43564,10 +43564,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -44039,10 +44039,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -44514,10 +44514,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -44989,10 +44989,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL32_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -45464,10 +45464,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul32_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL32_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -45939,10 +45939,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul32_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL32_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -46414,10 +46414,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul32_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL32_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -46889,10 +46889,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul32_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL32_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -47364,10 +47364,10 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul32_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL32_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -47839,7 +47839,7 @@
.Test(xnn_qu8_gemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul32_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_GEMM_MINMAX_FP32_1X2__SCALAR_LRINT, k_eq_1) {
diff --git a/test/qu8-igemm-minmax-fp32.cc b/test/qu8-igemm-minmax-fp32.cc
index 2ddfd9e..cec2dfa 100644
--- a/test/qu8-igemm-minmax-fp32.cc
+++ b/test/qu8-igemm-minmax-fp32.cc
@@ -38280,7 +38280,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -38764,10 +38764,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -39251,10 +39251,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -39738,10 +39738,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -40225,10 +40225,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -40712,10 +40712,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_1x4c2__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -41199,10 +41199,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_2x4c2__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -41686,10 +41686,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_3x4c2__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -42173,10 +42173,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_4x4c2__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -42660,10 +42660,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -43147,10 +43147,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -43634,10 +43634,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -44121,10 +44121,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -44608,10 +44608,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -45095,10 +45095,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -45582,10 +45582,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(4)
@@ -46069,10 +46069,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_4x4c8__wasmsimd_dot16x2_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL32_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -46556,10 +46556,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul32_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL32_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -47043,10 +47043,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul32_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL32_LD64, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -47530,10 +47530,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul32_ld64, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_MUL32_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(1)
@@ -48017,10 +48017,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_1x4c8__wasmsimd_mul32_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_MUL32_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(2)
@@ -48504,10 +48504,10 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_2x4c8__wasmsimd_mul32_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_MUL32_LD128, k_eq_8) {
GemmMicrokernelTester()
.mr(3)
@@ -48991,7 +48991,7 @@
.Test(xnn_qu8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul32_ld128, xnn_init_qu8_conv_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_IGEMM_MINMAX_FP32_1X2__SCALAR_LRINT, k_eq_1) {
diff --git a/test/qu8-vadd-minmax.cc b/test/qu8-vadd-minmax.cc
index 855ba34..4bb038c 100644
--- a/test/qu8-vadd-minmax.cc
+++ b/test/qu8-vadd-minmax.cc
@@ -3218,7 +3218,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VADD_MINMAX__WASMSIMD_X8, batch_eq_8) {
VAddMicrokernelTester()
.batch_size(8)
@@ -3360,10 +3360,10 @@
.Test(xnn_qu8_vadd_minmax_ukernel__wasmsimd_x8, xnn_init_qu8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VADD_MINMAX__WASMSIMD_X16, batch_eq_16) {
VAddMicrokernelTester()
.batch_size(16)
@@ -3505,10 +3505,10 @@
.Test(xnn_qu8_vadd_minmax_ukernel__wasmsimd_x16, xnn_init_qu8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VADD_MINMAX__WASMSIMD_X32, batch_eq_32) {
VAddMicrokernelTester()
.batch_size(32)
@@ -3650,7 +3650,7 @@
.Test(xnn_qu8_vadd_minmax_ukernel__wasmsimd_x32, xnn_init_qu8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VADD_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/qu8-vaddc-minmax.cc b/test/qu8-vaddc-minmax.cc
index 7451e6d..2916206 100644
--- a/test/qu8-vaddc-minmax.cc
+++ b/test/qu8-vaddc-minmax.cc
@@ -2798,7 +2798,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VADDC_MINMAX__WASMSIMD_X8, batch_eq_8) {
VAddCMicrokernelTester()
.batch_size(8)
@@ -2921,10 +2921,10 @@
.Test(xnn_qu8_vaddc_minmax_ukernel__wasmsimd_x8, xnn_init_qu8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VADDC_MINMAX__WASMSIMD_X16, batch_eq_16) {
VAddCMicrokernelTester()
.batch_size(16)
@@ -3047,10 +3047,10 @@
.Test(xnn_qu8_vaddc_minmax_ukernel__wasmsimd_x16, xnn_init_qu8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VADDC_MINMAX__WASMSIMD_X32, batch_eq_32) {
VAddCMicrokernelTester()
.batch_size(32)
@@ -3173,7 +3173,7 @@
.Test(xnn_qu8_vaddc_minmax_ukernel__wasmsimd_x32, xnn_init_qu8_add_minmax_wasmsimd_params);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VADDC_MINMAX__SCALAR_X1, batch_eq_1) {
diff --git a/test/qu8-vmul-minmax-fp32.cc b/test/qu8-vmul-minmax-fp32.cc
index 41e7c8a..66badfe 100644
--- a/test/qu8-vmul-minmax-fp32.cc
+++ b/test/qu8-vmul-minmax-fp32.cc
@@ -1938,7 +1938,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VMUL_MINMAX_FP32__WASMSIMD_MUL32_LD64_X8, batch_eq_8) {
VMulMicrokernelTester()
.batch_size(8)
@@ -2080,10 +2080,10 @@
.Test(xnn_qu8_vmul_minmax_fp32_ukernel__wasmsimd_mul32_ld64_x8, xnn_init_qu8_mul_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VMUL_MINMAX_FP32__WASMSIMD_MUL32_LD64_X16, batch_eq_16) {
VMulMicrokernelTester()
.batch_size(16)
@@ -2225,7 +2225,7 @@
.Test(xnn_qu8_vmul_minmax_fp32_ukernel__wasmsimd_mul32_ld64_x16, xnn_init_qu8_mul_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VMUL_MINMAX_FP32__SCALAR_X1, batch_eq_1) {
diff --git a/test/qu8-vmulc-minmax-fp32.cc b/test/qu8-vmulc-minmax-fp32.cc
index cd46fb8..79c4063 100644
--- a/test/qu8-vmulc-minmax-fp32.cc
+++ b/test/qu8-vmulc-minmax-fp32.cc
@@ -1686,7 +1686,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VMULC_MINMAX_FP32__WASMSIMD_MUL32_LD64_X8, batch_eq_8) {
VMulCMicrokernelTester()
.batch_size(8)
@@ -1809,10 +1809,10 @@
.Test(xnn_qu8_vmulc_minmax_fp32_ukernel__wasmsimd_mul32_ld64_x8, xnn_init_qu8_mul_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VMULC_MINMAX_FP32__WASMSIMD_MUL32_LD64_X16, batch_eq_16) {
VMulCMicrokernelTester()
.batch_size(16)
@@ -1935,7 +1935,7 @@
.Test(xnn_qu8_vmulc_minmax_fp32_ukernel__wasmsimd_mul32_ld64_x16, xnn_init_qu8_mul_minmax_fp32_wasmsimd_params, xnn_init_qu8_requantization_fp32_params, xnn_qu8_requantize_fp32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(QU8_VMULC_MINMAX_FP32__SCALAR_X1, batch_eq_1) {
diff --git a/test/s8-ibilinear.cc b/test/s8-ibilinear.cc
index bfc1d7a..c69d4b1 100644
--- a/test/s8-ibilinear.cc
+++ b/test/s8-ibilinear.cc
@@ -680,7 +680,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(S8_IBILINEAR__WASMSIMD_DOT16X2_C8, channels_eq_8) {
IBilinearMicrokernelTester()
.pixels(1)
@@ -749,10 +749,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(S8_IBILINEAR__WASMSIMD_DOT16X2_C16, channels_eq_16) {
IBilinearMicrokernelTester()
.pixels(1)
@@ -821,10 +821,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(S8_IBILINEAR__WASMSIMD_MUL32_C8, channels_eq_8) {
IBilinearMicrokernelTester()
.pixels(1)
@@ -893,10 +893,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(S8_IBILINEAR__WASMSIMD_MUL32_C16, channels_eq_16) {
IBilinearMicrokernelTester()
.pixels(1)
@@ -965,4 +965,4 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
diff --git a/test/s8-maxpool-minmax.cc b/test/s8-maxpool-minmax.cc
index b588dc6..db1e018 100644
--- a/test/s8-maxpool-minmax.cc
+++ b/test/s8-maxpool-minmax.cc
@@ -2681,7 +2681,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(S8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_unipass_fulltile) {
MaxPoolMicrokernelTester()
.pooling_elements(9)
@@ -3495,7 +3495,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(S8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_fulltile) {
diff --git a/test/s8-vclamp.cc b/test/s8-vclamp.cc
index e2f4254..7784a98 100644
--- a/test/s8-vclamp.cc
+++ b/test/s8-vclamp.cc
@@ -230,7 +230,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(S8_VCLAMP__WASMSIMD_X64, batch_eq_64) {
VUnaryMicrokernelTester()
.batch_size(64)
@@ -291,7 +291,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(S8_VCLAMP__SCALAR_X4, batch_eq_4) {
diff --git a/test/u8-ibilinear.cc b/test/u8-ibilinear.cc
index 45891dc..045ef24 100644
--- a/test/u8-ibilinear.cc
+++ b/test/u8-ibilinear.cc
@@ -680,7 +680,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(U8_IBILINEAR__WASMSIMD_DOT16X2_C8, channels_eq_8) {
IBilinearMicrokernelTester()
.pixels(1)
@@ -749,10 +749,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(U8_IBILINEAR__WASMSIMD_DOT16X2_C16, channels_eq_16) {
IBilinearMicrokernelTester()
.pixels(1)
@@ -821,10 +821,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(U8_IBILINEAR__WASMSIMD_MUL32_C8, channels_eq_8) {
IBilinearMicrokernelTester()
.pixels(1)
@@ -893,10 +893,10 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(U8_IBILINEAR__WASMSIMD_MUL32_C16, channels_eq_16) {
IBilinearMicrokernelTester()
.pixels(1)
@@ -965,4 +965,4 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
diff --git a/test/u8-maxpool-minmax.cc b/test/u8-maxpool-minmax.cc
index eb9bfb3..f177693 100644
--- a/test/u8-maxpool-minmax.cc
+++ b/test/u8-maxpool-minmax.cc
@@ -1794,7 +1794,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(U8_MAXPOOL_MINMAX_9P8X__WASMSIMD_C16, channels_eq_16_unipass_fulltile) {
MaxPoolMicrokernelTester()
.pooling_elements(9)
@@ -2608,7 +2608,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(U8_MAXPOOL_MINMAX_9P8X__SCALAR_C1, channels_eq_1_unipass_fulltile) {
diff --git a/test/u8-vclamp.cc b/test/u8-vclamp.cc
index 2717f32..e624b5e 100644
--- a/test/u8-vclamp.cc
+++ b/test/u8-vclamp.cc
@@ -159,7 +159,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(U8_VCLAMP__WASMSIMD_X64, batch_eq_64) {
VUnaryMicrokernelTester()
.batch_size(64)
@@ -220,7 +220,7 @@
}
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(U8_VCLAMP__SCALAR_X4, batch_eq_4) {
diff --git a/test/x32-packx.cc b/test/x32-packx.cc
index 44927a7..15b73b2 100644
--- a/test/x32-packx.cc
+++ b/test/x32-packx.cc
@@ -231,7 +231,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(X32_PACKX_4X__WASMSIMD, k_eq_4) {
PackMicrokernelTester()
.mr(4)
@@ -326,7 +326,7 @@
.Test(xnn_x32_packx_ukernel_4x__wasmsimd);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(X32_PACKX_2X__SCALAR, k_eq_1) {
diff --git a/test/x8-lut.cc b/test/x8-lut.cc
index 4af54e2..017667b 100644
--- a/test/x8-lut.cc
+++ b/test/x8-lut.cc
@@ -1042,7 +1042,7 @@
#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(X8_LUT__WASMSIMD_X16, batch_eq_16) {
LUTMicrokernelTester()
.batch_size(16)
@@ -1081,10 +1081,10 @@
.Test(xnn_x8_lut_ukernel__wasmsimd_x16);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(X8_LUT__WASMSIMD_X32, batch_eq_32) {
LUTMicrokernelTester()
.batch_size(32)
@@ -1123,10 +1123,10 @@
.Test(xnn_x8_lut_ukernel__wasmsimd_x32);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(X8_LUT__WASMSIMD_X48, batch_eq_48) {
LUTMicrokernelTester()
.batch_size(48)
@@ -1165,10 +1165,10 @@
.Test(xnn_x8_lut_ukernel__wasmsimd_x48);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
-#if XNN_ARCH_WASMSIMD
+#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
TEST(X8_LUT__WASMSIMD_X64, batch_eq_64) {
LUTMicrokernelTester()
.batch_size(64)
@@ -1207,4 +1207,4 @@
.Test(xnn_x8_lut_ukernel__wasmsimd_x64);
}
}
-#endif // XNN_ARCH_WASMSIMD
+#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD