commit 60bb7ecd74ba3c68617bfee8c6f742780ad811d4
author Marat Dukhan <maratek@google.com> Wed Jul 28 18:51:28 2021 -0700
committer XNNPACK Team <xnnpack-github-robot@google.com> Wed Jul 28 18:52:18 2021 -0700
tree 04258be3a2a0c86645c5640c9cd3efe0d814c803
parent 793c8da1796eb5acd442a255e387e1e2eedc990e

Accumulate in 16 bits once in AVX2 MUL16 VPUNPCK QS8/QC8 DWCONV before extending to 32 bits

PiperOrigin-RevId: 387486822

CMakeLists.txt

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 61f3659..177b98d 100755
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -4017,17 +4017,21 @@
   src/qc8-dwconv/gen/up8x25-minmax-fp32-avx2-mul32.c
   src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpmovsx.c
   src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpunpck.c
+  src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-add16-vpunpck.c
   src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c
   src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpmovsx.c
   src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpunpck.c
+  src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-add16-vpunpck.c
   src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c
   src/qc8-dwconv/gen/up24x9-minmax-fp32-avx2-mul32.c
   src/qc8-dwconv/gen/up24x25-minmax-fp32-avx2-mul32.c
   src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpmovsx.c
   src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpunpck.c
+  src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-add16-vpunpck.c
   src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul32.c
   src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpmovsx.c
   src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpunpck.c
+  src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-add16-vpunpck.c
   src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul32.c
   src/qc8-gemm/gen/1x8c8-minmax-fp32-avx2.c
   src/qc8-gemm/gen/1x8c8-xw-minmax-fp32-avx2.c
@@ -4044,11 +4048,13 @@
   src/qs8-dwconv/gen/up8x25-minmax-gemmlowp-avx2-mul32.c
   src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpmovsx.c
   src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpunpck.c
+  src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-add16-vpunpck.c
   src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c
   src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-avx2-mul16-vpmovsx.c
   src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-avx2-mul32.c
   src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpmovsx.c
   src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpunpck.c
+  src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-add16-vpunpck.c
   src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c
   src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-avx2-mul16-vpmovsx.c
   src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-avx2-mul32.c
@@ -4058,11 +4064,13 @@
   src/qs8-dwconv/gen/up24x25-minmax-gemmlowp-avx2-mul32.c
   src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpmovsx.c
   src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpunpck.c
+  src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-add16-vpunpck.c
   src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul32.c
   src/qs8-dwconv/gen/up32x9-minmax-gemmlowp-avx2-mul16-vpmovsx.c
   src/qs8-dwconv/gen/up32x9-minmax-gemmlowp-avx2-mul32.c
   src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpmovsx.c
   src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpunpck.c
+  src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-add16-vpunpck.c
   src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul32.c
   src/qs8-dwconv/gen/up32x25-minmax-gemmlowp-avx2-mul16-vpmovsx.c
   src/qs8-dwconv/gen/up32x25-minmax-gemmlowp-avx2-mul32.c