commit 7519eb1eb685d921a24bcc5bc40b804edfbecd4a
author Marat Dukhan <maratek@google.com> Tue Nov 23 19:08:29 2021 -0800
committer XNNPACK Team <xnnpack-github-robot@google.com> Tue Nov 23 19:09:21 2021 -0800
tree 694ab6149af93533e111637d0df7b759e52c59e7
parent 66210588dcca8d0d94edd355125d834102560d2d

SSE2 & SSE4.1 versions of S8/U8 IBILINEAR microkernels

PiperOrigin-RevId: 411943750

BUILD.bazel

diff --git a/BUILD.bazel b/BUILD.bazel
index 700c065..808d561 100644
--- a/BUILD.bazel
+++ b/BUILD.bazel
@@ -4448,8 +4448,12 @@
     "src/qu8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
     "src/qu8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
     "src/qu8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
+    "src/s8-ibilinear/gen/sse2-c8.c",
+    "src/s8-ibilinear/gen/sse2-c16.c",
     "src/s8-maxpool/9p8x-minmax-sse2-c16.c",
     "src/s8-vclamp/sse2-x64.c",
+    "src/u8-ibilinear/gen/sse2-c8.c",
+    "src/u8-ibilinear/gen/sse2-c16.c",
     "src/u8-maxpool/9p8x-minmax-sse2-c16.c",
     "src/u8-rmax/sse2.c",
     "src/u8-vclamp/sse2-x64.c",
@@ -4821,8 +4825,12 @@
     "src/qu8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
     "src/qu8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
     "src/qu8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
+    "src/s8-ibilinear/gen/sse41-c8.c",
+    "src/s8-ibilinear/gen/sse41-c16.c",
     "src/s8-maxpool/9p8x-minmax-sse41-c16.c",
     "src/s8-vclamp/sse41-x64.c",
+    "src/u8-ibilinear/gen/sse41-c8.c",
+    "src/u8-ibilinear/gen/sse41-c16.c",
 ]
 
 PROD_AVX_MICROKERNEL_SRCS = [