commit 7c478e31bbc7a1b61199222110efd190fd1b9d13
author Marat Dukhan <maratek@google.com> Fri Sep 10 09:48:13 2021 -0700
committer XNNPACK Team <xnnpack-github-robot@google.com> Fri Sep 10 09:49:17 2021 -0700
tree 3b86b1d0cc5ffee1fc61718e8a58b4b50268c9fa
parent 5de7bc0a0c18f04e0183966d970bcafcb3d18d60

SSSE3, AVX, and AVX2 X8 LUT microkernels

PiperOrigin-RevId: 395948284

BUILD.bazel

diff --git a/BUILD.bazel b/BUILD.bazel
index 3cfe853..b54c9ac 100644
--- a/BUILD.bazel
+++ b/BUILD.bazel
@@ -3970,6 +3970,8 @@
     "src/qu8-igemm/gen/4x4c2-minmax-gemmlowp-ssse3-ld64.c",
     "src/qu8-requantization/gemmlowp-ssse3.c",
     "src/qu8-requantization/rndna-ssse3.c",
+    "src/x8-lut/gen/lut-ssse3-x16.c",
+    "src/x8-lut/gen/lut-ssse3-x32.c",
 ]
 
 PROD_SSE41_MICROKERNEL_SRCS = [
@@ -4640,6 +4642,10 @@
     "src/qu8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
     "src/qu8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x8.c",
     "src/qu8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
+    "src/x8-lut/gen/lut-avx-x16.c",
+    "src/x8-lut/gen/lut-avx-x32.c",
+    "src/x8-lut/gen/lut-avx-x48.c",
+    "src/x8-lut/gen/lut-avx-x64.c",
 ]
 
 PROD_XOP_MICROKERNEL_SRCS = [
@@ -5174,6 +5180,10 @@
     "src/qu8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
     "src/qu8-vaddc/gen/minmax-avx2-mul32-ld64-x8.c",
     "src/qu8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
+    "src/x8-lut/gen/lut-avx2-x32.c",
+    "src/x8-lut/gen/lut-avx2-x64.c",
+    "src/x8-lut/gen/lut-avx2-x96.c",
+    "src/x8-lut/gen/lut-avx2-x128.c",
 ]
 
 PROD_AVX512F_MICROKERNEL_SRCS = [