commit 9c7308f6c76076a922fbdf5ac7f1a5d1c25141fb
author Frank Barchard <fbarchard@google.com> Mon Aug 31 17:03:01 2020 -0700
committer XNNPACK Team <xnnpack-github-robot@google.com> Mon Aug 31 17:03:38 2020 -0700
tree 428f99ac1e59ad48be4de15f1bf5ef7b91a62a0e
parent a635a293588a2ad17e5712eb7029cb53be65b296

vbinary microkernels unrolled to x8 for scalar and web assembly and x16 web assembly simd

PiperOrigin-RevId: 329407843

test/f32-vrdivc-relu.cc

diff --git a/test/f32-vrdivc-relu.cc b/test/f32-vrdivc-relu.cc
index 0eb043d..a2efc96 100644
--- a/test/f32-vrdivc-relu.cc
+++ b/test/f32-vrdivc-relu.cc
@@ -101,6 +101,48 @@
 #endif  // XNN_ARCH_WASMSIMD
 
 
+#if XNN_ARCH_WASMSIMD
+  TEST(F32_VRDIVC_RELU__WASMSIMD_X16, batch_eq_16) {
+    VBinOpCMicrokernelTester()
+      .batch_size(16)
+      .Test(xnn_f32_vrdivc_relu_ukernel__wasmsimd_x16, VBinOpCMicrokernelTester::OpType::RDivC);
+  }
+
+  TEST(F32_VRDIVC_RELU__WASMSIMD_X16, batch_div_16) {
+    for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
+      VBinOpCMicrokernelTester()
+        .batch_size(batch_size)
+        .Test(xnn_f32_vrdivc_relu_ukernel__wasmsimd_x16, VBinOpCMicrokernelTester::OpType::RDivC);
+    }
+  }
+
+  TEST(F32_VRDIVC_RELU__WASMSIMD_X16, batch_lt_16) {
+    for (size_t batch_size = 1; batch_size < 16; batch_size++) {
+      VBinOpCMicrokernelTester()
+        .batch_size(batch_size)
+        .Test(xnn_f32_vrdivc_relu_ukernel__wasmsimd_x16, VBinOpCMicrokernelTester::OpType::RDivC);
+    }
+  }
+
+  TEST(F32_VRDIVC_RELU__WASMSIMD_X16, batch_gt_16) {
+    for (size_t batch_size = 17; batch_size < 32; batch_size++) {
+      VBinOpCMicrokernelTester()
+        .batch_size(batch_size)
+        .Test(xnn_f32_vrdivc_relu_ukernel__wasmsimd_x16, VBinOpCMicrokernelTester::OpType::RDivC);
+    }
+  }
+
+  TEST(F32_VRDIVC_RELU__WASMSIMD_X16, inplace) {
+    for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
+      VBinOpCMicrokernelTester()
+        .batch_size(batch_size)
+        .inplace(true)
+        .Test(xnn_f32_vrdivc_relu_ukernel__wasmsimd_x16, VBinOpCMicrokernelTester::OpType::RDivC);
+    }
+  }
+#endif  // XNN_ARCH_WASMSIMD
+
+
 #if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_VRDIVC_RELU__WASM_X1, batch_eq_1) {
     VBinOpCMicrokernelTester()
@@ -211,6 +253,48 @@
 #endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+  TEST(F32_VRDIVC_RELU__WASM_X8, batch_eq_8) {
+    VBinOpCMicrokernelTester()
+      .batch_size(8)
+      .Test(xnn_f32_vrdivc_relu_ukernel__wasm_x8, VBinOpCMicrokernelTester::OpType::RDivC);
+  }
+
+  TEST(F32_VRDIVC_RELU__WASM_X8, batch_div_8) {
+    for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
+      VBinOpCMicrokernelTester()
+        .batch_size(batch_size)
+        .Test(xnn_f32_vrdivc_relu_ukernel__wasm_x8, VBinOpCMicrokernelTester::OpType::RDivC);
+    }
+  }
+
+  TEST(F32_VRDIVC_RELU__WASM_X8, batch_lt_8) {
+    for (size_t batch_size = 1; batch_size < 8; batch_size++) {
+      VBinOpCMicrokernelTester()
+        .batch_size(batch_size)
+        .Test(xnn_f32_vrdivc_relu_ukernel__wasm_x8, VBinOpCMicrokernelTester::OpType::RDivC);
+    }
+  }
+
+  TEST(F32_VRDIVC_RELU__WASM_X8, batch_gt_8) {
+    for (size_t batch_size = 9; batch_size < 16; batch_size++) {
+      VBinOpCMicrokernelTester()
+        .batch_size(batch_size)
+        .Test(xnn_f32_vrdivc_relu_ukernel__wasm_x8, VBinOpCMicrokernelTester::OpType::RDivC);
+    }
+  }
+
+  TEST(F32_VRDIVC_RELU__WASM_X8, inplace) {
+    for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
+      VBinOpCMicrokernelTester()
+        .batch_size(batch_size)
+        .inplace(true)
+        .Test(xnn_f32_vrdivc_relu_ukernel__wasm_x8, VBinOpCMicrokernelTester::OpType::RDivC);
+    }
+  }
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
+
+
 TEST(F32_VRDIVC_RELU__SCALAR_X1, batch_eq_1) {
   VBinOpCMicrokernelTester()
     .batch_size(1)
@@ -313,3 +397,43 @@
       .Test(xnn_f32_vrdivc_relu_ukernel__scalar_x4, VBinOpCMicrokernelTester::OpType::RDivC, VBinOpCMicrokernelTester::Variant::Scalar);
   }
 }
+
+
+TEST(F32_VRDIVC_RELU__SCALAR_X8, batch_eq_8) {
+  VBinOpCMicrokernelTester()
+    .batch_size(8)
+    .Test(xnn_f32_vrdivc_relu_ukernel__scalar_x8, VBinOpCMicrokernelTester::OpType::RDivC, VBinOpCMicrokernelTester::Variant::Scalar);
+}
+
+TEST(F32_VRDIVC_RELU__SCALAR_X8, batch_div_8) {
+  for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
+    VBinOpCMicrokernelTester()
+      .batch_size(batch_size)
+      .Test(xnn_f32_vrdivc_relu_ukernel__scalar_x8, VBinOpCMicrokernelTester::OpType::RDivC, VBinOpCMicrokernelTester::Variant::Scalar);
+  }
+}
+
+TEST(F32_VRDIVC_RELU__SCALAR_X8, batch_lt_8) {
+  for (size_t batch_size = 1; batch_size < 8; batch_size++) {
+    VBinOpCMicrokernelTester()
+      .batch_size(batch_size)
+      .Test(xnn_f32_vrdivc_relu_ukernel__scalar_x8, VBinOpCMicrokernelTester::OpType::RDivC, VBinOpCMicrokernelTester::Variant::Scalar);
+  }
+}
+
+TEST(F32_VRDIVC_RELU__SCALAR_X8, batch_gt_8) {
+  for (size_t batch_size = 9; batch_size < 16; batch_size++) {
+    VBinOpCMicrokernelTester()
+      .batch_size(batch_size)
+      .Test(xnn_f32_vrdivc_relu_ukernel__scalar_x8, VBinOpCMicrokernelTester::OpType::RDivC, VBinOpCMicrokernelTester::Variant::Scalar);
+  }
+}
+
+TEST(F32_VRDIVC_RELU__SCALAR_X8, inplace) {
+  for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
+    VBinOpCMicrokernelTester()
+      .batch_size(batch_size)
+      .inplace(true)
+      .Test(xnn_f32_vrdivc_relu_ukernel__scalar_x8, VBinOpCMicrokernelTester::OpType::RDivC, VBinOpCMicrokernelTester::Variant::Scalar);
+  }
+}