Remove wb from JIT aarch32 instructions, use mem operand and ++ instead
Was: vldm(r9, {d0-d1}, false) or vldm(r9, {d0-d1}, true)
Now: vldm(mem[r9], {d0-d1}) or vldm(mem[r9]++, {d0-d1})
PiperOrigin-RevId: 424717109
diff --git a/scripts/convert-assembly-to-jit.py b/scripts/convert-assembly-to-jit.py
index 51e19f5..60b244a 100755
--- a/scripts/convert-assembly-to-jit.py
+++ b/scripts/convert-assembly-to-jit.py
@@ -366,17 +366,17 @@
m = re.fullmatch(INSTR_REG_REGLIST_CONSECT, line)
if m:
instructions.append(
- f'{fix_instr_name(m[1])}({m[2]}, {{{m[3]}-{m[4]}}}, false){sc} {m[5]}')
+ f'{fix_instr_name(m[1])}(mem[{m[2]}], {{{m[3]}-{m[4]}}}){sc} {m[5]}')
continue
m = re.fullmatch(INSTR_REG_REGLIST_CONSECT_WB, line)
if m:
instructions.append(
- f'{fix_instr_name(m[1])}({m[2]}, {{{m[3]}-{m[4]}}}, true){sc} {m[5]}')
+ f'{fix_instr_name(m[1])}(mem[{m[2]}]++, {{{m[3]}-{m[4]}}}){sc} {m[5]}')
continue
m = re.fullmatch(INSTR_REG_REGLIST_INDIV_WB, line)
if m:
instructions.append(
- f'{fix_instr_name(m[1])}({m[2]}, {{{m[3]}}}, true){sc} {m[4]}')
+ f'{fix_instr_name(m[1])}(mem[{m[2]}]++, {{{m[3]}}}){sc} {m[4]}')
continue
m = re.fullmatch(INSTR_B_IMM, line)
if m: