commit cd4089fa593ea3d94d59a3c6327a419fd59c7a56
author Marat Dukhan <maratek@google.com> Tue Dec 14 23:53:33 2021 -0800
committer XNNPACK Team <xnnpack-github-robot@google.com> Tue Dec 14 23:54:43 2021 -0800
tree 0da3458c40fc27146f7351722cb6331c35e72cf3
parent 2edf863108848301420dc2712a7d3d29a6ed1151

AVX QS8->F32 and QU8->F32 VCVT microkernels

PiperOrigin-RevId: 416481843

BUILD.bazel

diff --git a/BUILD.bazel b/BUILD.bazel
index 84548cc..d2a62cb 100644
--- a/BUILD.bazel
+++ b/BUILD.bazel
@@ -5007,6 +5007,7 @@
     "src/qc8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
     "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
     "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
+    "src/qs8-f32-vcvt/gen/vcvt-avx-x32.c",
     "src/qs8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
     "src/qs8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
     "src/qs8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
@@ -5017,6 +5018,7 @@
     "src/qs8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
     "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
     "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
+    "src/qu8-f32-vcvt/gen/vcvt-avx-x32.c",
     "src/qu8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
     "src/qu8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
     "src/qu8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
@@ -5258,6 +5260,10 @@
     "src/qs8-dwconv/gen/up24x9-minmax-fp32-avx-mul32.c",
     "src/qs8-dwconv/gen/up24x25-minmax-fp32-avx-mul16.c",
     "src/qs8-dwconv/gen/up24x25-minmax-fp32-avx-mul32.c",
+    "src/qs8-f32-vcvt/gen/vcvt-avx-x8.c",
+    "src/qs8-f32-vcvt/gen/vcvt-avx-x16.c",
+    "src/qs8-f32-vcvt/gen/vcvt-avx-x24.c",
+    "src/qs8-f32-vcvt/gen/vcvt-avx-x32.c",
     "src/qs8-gemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
     "src/qs8-gemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
     "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-avx.c",
@@ -5321,6 +5327,10 @@
     "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx-mul32.c",
     "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
     "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul32.c",
+    "src/qu8-f32-vcvt/gen/vcvt-avx-x8.c",
+    "src/qu8-f32-vcvt/gen/vcvt-avx-x16.c",
+    "src/qu8-f32-vcvt/gen/vcvt-avx-x24.c",
+    "src/qu8-f32-vcvt/gen/vcvt-avx-x32.c",
     "src/qu8-gemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
     "src/qu8-gemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
     "src/qu8-gemm/gen/1x4c8-minmax-fp32-avx-ld64.c",