commit e7223eebf21f6da24dbce01a6d11edebcf24e5c9
author Frank Barchard <fbarchard@google.com> Fri Dec 04 19:04:01 2020 -0800
committer XNNPACK Team <xnnpack-github-robot@google.com> Fri Dec 04 19:04:49 2020 -0800
tree b165ad3f8818ddc81ec1a00ffa1ab148383dd9ee
parent 4e8958736690e337169fe19d156564e16720bf0f

WASMSIMD dwconv2d 5x5s2 tests and benchmark
- sort BUILD and CMake filenames alpha numerically

PiperOrigin-RevId: 345800193

BUILD.bazel

diff --git a/BUILD.bazel b/BUILD.bazel
index c121a17..4844f39 100644
--- a/BUILD.bazel
+++ b/BUILD.bazel
@@ -1226,18 +1226,18 @@
     "src/f32-velu/gen/velu-wasmsimd-arm-rr2-lut16-p3-x16.c",
     "src/f32-velu/gen/velu-wasmsimd-arm-rr2-lut16-p3-x20.c",
     "src/f32-velu/gen/velu-wasmsimd-arm-rr2-lut16-p3-x24.c",
-    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x4.c",
-    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x8.c",
-    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x12.c",
-    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x16.c",
-    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x20.c",
-    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x24.c",
     "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x4.c",
     "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x8.c",
     "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x12.c",
     "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x16.c",
     "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x20.c",
     "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x24.c",
+    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x4.c",
+    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x8.c",
+    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x12.c",
+    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x16.c",
+    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x20.c",
+    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x24.c",
     "src/f32-velu/gen/velu-wasmsimd-x86-rr2-p6-x4.c",
     "src/f32-velu/gen/velu-wasmsimd-x86-rr2-p6-x8.c",
     "src/f32-velu/gen/velu-wasmsimd-x86-rr2-p6-x12.c",
@@ -1819,11 +1819,11 @@
     "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x40.c",
     "src/math/exp-neonfma-rr2-lut64-p2.c",
     "src/math/exp-neonfma-rr2-p5.c",
+    "src/math/expm1minus-neonfma-rr1-lut16-p3.c",
+    "src/math/expm1minus-neonfma-rr1-p6.c",
     "src/math/expminus-neonfma-rr2-lut64-p2.c",
     "src/math/expminus-neonfma-rr2-lut2048-p1.c",
     "src/math/expminus-neonfma-rr2-p5.c",
-    "src/math/expm1minus-neonfma-rr1-lut16-p3.c",
-    "src/math/expm1minus-neonfma-rr1-p6.c",
     "src/math/sigmoid-neonfma-rr1-lut64-p2-nr1recps1fma.c",
     "src/math/sigmoid-neonfma-rr1-lut64-p2-nr2fma.c",
     "src/math/sigmoid-neonfma-rr1-lut64-p2-nr2recps.c",
@@ -2931,11 +2931,11 @@
     "src/math/exp-avx2-rr2-lut8-p3-perm.c",
     "src/math/exp-avx2-rr2-lut8-p4-perm.c",
     "src/math/exp-avx2-rr2-p5.c",
-    "src/math/expminus-avx2-rr2-p5.c",
     "src/math/expm1minus-avx2-rr1-lut4-p4-perm.c",
     "src/math/expm1minus-avx2-rr1-lut8-p4-perm.c",
     "src/math/expm1minus-avx2-rr1-lut16-p3-gather.c",
     "src/math/expm1minus-avx2-rr1-p6.c",
+    "src/math/expminus-avx2-rr2-p5.c",
     "src/math/extexp-avx2-p5.c",
     "src/math/sigmoid-avx2-rr1-lut64-p2-gather-div.c",
     "src/math/sigmoid-avx2-rr1-lut64-p2-gather-nr1fma.c",