Vector ELU microkernels
PiperOrigin-RevId: 345108685
diff --git a/src/f32-velu/wasmsimd-rr2-p6.c.in b/src/f32-velu/wasmsimd-rr2-p6.c.in
new file mode 100644
index 0000000..31c3343
--- /dev/null
+++ b/src/f32-velu/wasmsimd-rr2-p6.c.in
@@ -0,0 +1,190 @@
+// Copyright 2020 Google LLC
+//
+// This source code is licensed under the BSD-style license found in the
+// LICENSE file in the root directory of this source tree.
+
+$assert BATCH_TILE % 4 == 0
+$assert BATCH_TILE >= 4
+$ABC = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"
+#include <assert.h>
+
+#include <wasm_simd128.h>
+
+#include <xnnpack/vunary.h>
+#include <xnnpack/common.h>
+
+
+void xnn_f32_velu_ukernel__wasmsimd_${"x86" if X86 else "arm"}_rr2_p6_x${BATCH_TILE}(
+ size_t n,
+ const float* x,
+ float* y,
+ const union xnn_f32_elu_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_DISABLE_TSAN
+{
+ assert(n != 0);
+ assert(n % sizeof(float) == 0);
+ assert(x != NULL);
+ assert(y != NULL);
+
+ const v128_t vprescale = wasm_v32x4_load_splat(¶ms->scalar.prescale);
+ const v128_t valpha = wasm_v32x4_load_splat(¶ms->scalar.alpha);
+ const v128_t vbeta = wasm_v32x4_load_splat(¶ms->scalar.beta);
+
+ const v128_t vsat_cutoff = wasm_f32x4_splat(-0x1.154246p+4f);
+ const v128_t vmagic_bias = wasm_f32x4_splat(0x1.8000FEp23f);
+ const v128_t vlog2e = wasm_f32x4_splat(0x1.715476p+0f);
+ const v128_t vminus_ln2_hi = wasm_f32x4_splat(-0x1.62E440p-1f);
+ const v128_t vminus_ln2_lo = wasm_f32x4_splat(0x1.0105C6p-21f);
+ const v128_t vc6 = wasm_f32x4_splat(0x1.6b7338p-10f);
+ const v128_t vc5 = wasm_f32x4_splat(0x1.12278Ep-7f);
+ const v128_t vc4 = wasm_f32x4_splat(0x1.555716p-5f);
+ const v128_t vc3 = wasm_f32x4_splat(0x1.5554B0p-3f);
+ const v128_t vc2 = wasm_f32x4_splat(0x1.FFFFFEp-2f);
+ const v128_t vone = wasm_f32x4_splat(1.0f);
+
+ $if BATCH_TILE > 4:
+ for (; n >= ${BATCH_TILE} * sizeof(float); n -= ${BATCH_TILE} * sizeof(float)) {
+ v128_t vx${ABC[0:4]} = wasm_v128_load(x);
+ $for N in range(4, BATCH_TILE, 4):
+ v128_t vx${ABC[N:N+4]} = wasm_v128_load(x + ${N});
+ x += ${BATCH_TILE};
+
+ $for N in range(0, BATCH_TILE, 4):
+ $if X86:
+ const v128_t vz${ABC[N:N+4]} = wasm_f32x4_mul(vx${ABC[N:N+4]}, vprescale);
+ $else:
+ const v128_t vz${ABC[N:N+4]} = wasm_f32x4_max(wasm_f32x4_mul(vx${ABC[N:N+4]}, vprescale), vsat_cutoff);
+
+ $for N in range(0, BATCH_TILE, 4):
+ v128_t vn${ABC[N:N+4]} = wasm_f32x4_add(wasm_f32x4_mul(vz${ABC[N:N+4]}, vlog2e), vmagic_bias);
+
+ $for N in range(0, BATCH_TILE, 4):
+ v128_t vs${ABC[N:N+4]} = wasm_i32x4_shl(vn${ABC[N:N+4]}, 23);
+
+ $for N in range(0, BATCH_TILE, 4):
+ vn${ABC[N:N+4]} = wasm_f32x4_sub(vn${ABC[N:N+4]}, vmagic_bias);
+
+ $if X86:
+ $for N in range(0, BATCH_TILE, 4):
+ vs${ABC[N:N+4]} = wasm_v128_andnot(vs${ABC[N:N+4]}, wasm_f32x4_le(vz${ABC[N:N+4]}, vsat_cutoff));
+
+ $for N in range(0, BATCH_TILE, 4):
+ v128_t vt${ABC[N:N+4]} = wasm_f32x4_add(wasm_f32x4_mul(vn${ABC[N:N+4]}, vminus_ln2_hi), vz${ABC[N:N+4]});
+
+ $for N in range(0, BATCH_TILE, 4):
+ vt${ABC[N:N+4]} = wasm_f32x4_add(wasm_f32x4_mul(vn${ABC[N:N+4]}, vminus_ln2_lo), vt${ABC[N:N+4]});
+
+ $for N in range(0, BATCH_TILE, 4):
+ v128_t vp${ABC[N:N+4]} = wasm_f32x4_add(wasm_f32x4_mul(vc6, vt${ABC[N:N+4]}), vc5);
+
+ $for N in range(0, BATCH_TILE, 4):
+ vp${ABC[N:N+4]} = wasm_f32x4_add(wasm_f32x4_mul(vp${ABC[N:N+4]}, vt${ABC[N:N+4]}), vc4);
+
+ $for N in range(0, BATCH_TILE, 4):
+ vp${ABC[N:N+4]} = wasm_f32x4_add(wasm_f32x4_mul(vp${ABC[N:N+4]}, vt${ABC[N:N+4]}), vc3);
+
+ $for N in range(0, BATCH_TILE, 4):
+ vp${ABC[N:N+4]} = wasm_f32x4_add(wasm_f32x4_mul(vp${ABC[N:N+4]}, vt${ABC[N:N+4]}), vc2);
+
+ $for N in range(0, BATCH_TILE, 4):
+ vp${ABC[N:N+4]} = wasm_f32x4_mul(vp${ABC[N:N+4]}, vt${ABC[N:N+4]});
+
+ $for N in range(0, BATCH_TILE, 4):
+ vt${ABC[N:N+4]} = wasm_f32x4_mul(vt${ABC[N:N+4]}, vs${ABC[N:N+4]});
+ vs${ABC[N:N+4]} = wasm_f32x4_sub(vs${ABC[N:N+4]}, vone);
+
+ $for N in range(0, BATCH_TILE, 4):
+ vp${ABC[N:N+4]} = wasm_f32x4_add(wasm_f32x4_mul(vp${ABC[N:N+4]}, vt${ABC[N:N+4]}), vt${ABC[N:N+4]});
+
+ $for N in range(0, BATCH_TILE, 4):
+ const v128_t ve${ABC[N:N+4]} = wasm_f32x4_mul(wasm_f32x4_add(vp${ABC[N:N+4]}, vs${ABC[N:N+4]}), valpha);
+
+ $for N in range(0, BATCH_TILE, 4):
+ const v128_t vm${ABC[N:N+4]} = wasm_i32x4_shr(vx${ABC[N:N+4]}, 31);
+ vx${ABC[N:N+4]} = wasm_f32x4_mul(vx${ABC[N:N+4]}, vbeta);
+
+ $for N in range(0, BATCH_TILE, 4):
+ const v128_t vy${ABC[N:N+4]} = wasm_v128_bitselect(ve${ABC[N:N+4]}, vx${ABC[N:N+4]}, vm${ABC[N:N+4]});
+
+ wasm_v128_store(y, vy${ABC[0:4]});
+ $for N in range(4, BATCH_TILE, 4):
+ wasm_v128_store(y + ${N}, vy${ABC[N:N+4]});
+ y += ${BATCH_TILE};
+ }
+ for (; n >= 4 * sizeof(float); n -= 4 * sizeof(float)) {
+ v128_t vx = wasm_v128_load(x);
+ x += 4;
+
+ $if X86:
+ const v128_t vz = wasm_f32x4_mul(vx, vprescale);
+ $else:
+ const v128_t vz = wasm_f32x4_max(wasm_f32x4_mul(vx, vprescale), vsat_cutoff);
+
+ v128_t vn = wasm_f32x4_add(wasm_f32x4_mul(vz, vlog2e), vmagic_bias);
+ v128_t vs = wasm_i32x4_shl(vn, 23);
+ vn = wasm_f32x4_sub(vn, vmagic_bias);
+ $if X86:
+ vs = wasm_v128_andnot(vs, wasm_f32x4_le(vz, vsat_cutoff));
+
+ v128_t vt = wasm_f32x4_add(wasm_f32x4_mul(vn, vminus_ln2_hi), vz);
+ vt = wasm_f32x4_add(wasm_f32x4_mul(vn, vminus_ln2_lo), vt);
+
+ v128_t vp = wasm_f32x4_add(wasm_f32x4_mul(vc6, vt), vc5);
+ vp = wasm_f32x4_add(wasm_f32x4_mul(vp, vt), vc4);
+ vp = wasm_f32x4_add(wasm_f32x4_mul(vp, vt), vc3);
+ vp = wasm_f32x4_add(wasm_f32x4_mul(vp, vt), vc2);
+ vp = wasm_f32x4_mul(vp, vt);
+
+ vt = wasm_f32x4_mul(vt, vs);
+ vs = wasm_f32x4_sub(vs, vone);
+ vp = wasm_f32x4_add(wasm_f32x4_mul(vp, vt), vt);
+ const v128_t ve = wasm_f32x4_mul(wasm_f32x4_add(vp, vs), valpha);
+
+ const v128_t vm = wasm_i32x4_shr(vx, 31);
+ vx = wasm_f32x4_mul(vx, vbeta);
+ const v128_t vy = wasm_v128_bitselect(ve, vx, vm);
+
+ wasm_v128_store(y, vy);
+ y += 4;
+ }
+ if XNN_UNLIKELY(n != 0) {
+ v128_t vx = wasm_v128_load(x);
+
+ $if X86:
+ const v128_t vz = wasm_f32x4_mul(vx, vprescale);
+ $else:
+ const v128_t vz = wasm_f32x4_max(wasm_f32x4_mul(vx, vprescale), vsat_cutoff);
+
+ v128_t vn = wasm_f32x4_add(wasm_f32x4_mul(vz, vlog2e), vmagic_bias);
+ v128_t vs = wasm_i32x4_shl(vn, 23);
+ vn = wasm_f32x4_sub(vn, vmagic_bias);
+ $if X86:
+ vs = wasm_v128_andnot(vs, wasm_f32x4_le(vz, vsat_cutoff));
+
+ v128_t vt = wasm_f32x4_add(wasm_f32x4_mul(vn, vminus_ln2_hi), vz);
+ vt = wasm_f32x4_add(wasm_f32x4_mul(vn, vminus_ln2_lo), vt);
+
+ v128_t vp = wasm_f32x4_add(wasm_f32x4_mul(vc6, vt), vc5);
+ vp = wasm_f32x4_add(wasm_f32x4_mul(vp, vt), vc4);
+ vp = wasm_f32x4_add(wasm_f32x4_mul(vp, vt), vc3);
+ vp = wasm_f32x4_add(wasm_f32x4_mul(vp, vt), vc2);
+ vp = wasm_f32x4_mul(vp, vt);
+
+ vt = wasm_f32x4_mul(vt, vs);
+ vs = wasm_f32x4_sub(vs, vone);
+ vp = wasm_f32x4_add(wasm_f32x4_mul(vp, vt), vt);
+ const v128_t ve = wasm_f32x4_mul(wasm_f32x4_add(vp, vs), valpha);
+
+ const v128_t vm = wasm_i32x4_shr(vx, 31);
+ vx = wasm_f32x4_mul(vx, vbeta);
+ v128_t vy = wasm_v128_bitselect(ve, vx, vm);
+
+ if (n & (2 * sizeof(float))) {
+ *((double*) y) = wasm_f64x2_extract_lane(vy, 0);
+ vy = wasm_v32x4_shuffle(vy, vy, 2, 3, 2, 3);
+ y += 2;
+ }
+ if (n & (1 * sizeof(float))) {
+ *y = wasm_f32x4_extract_lane(vy, 0);
+ }
+ }
+}