commit fb5b20ac9979ffbde3322bc54dd02f179d6ce0d8
author Marat Dukhan <maratek@google.com> Fri Jun 26 13:14:50 2020 -0700
committer XNNPACK Team <xnnpack-github-robot@google.com> Fri Jun 26 13:15:29 2020 -0700
tree 56edb88e5021fb71fb79cd9da4f2f67c9df071e3
parent 93d1ba1db190e266e666910227b67df4f24be73d

Enable WAsm MVP tests in WAsm SIMD builds

PiperOrigin-RevId: 318530711

test/f32-dwconv.cc

diff --git a/test/f32-dwconv.cc b/test/f32-dwconv.cc
index 7ad4e77..49306c4 100644
--- a/test/f32-dwconv.cc
+++ b/test/f32-dwconv.cc
@@ -638,7 +638,7 @@
 #endif  // XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP1X4__WASM, c_eq_1) {
     DWConvMicrokernelTester()
       .cr(1)
@@ -718,10 +718,10 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP1X4__WASM_ACC2, c_eq_1) {
     DWConvMicrokernelTester()
       .cr(1)
@@ -801,10 +801,10 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP2X4__WASM, c_eq_2) {
     DWConvMicrokernelTester()
       .cr(2)
@@ -904,10 +904,10 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP2X4__WASM_ACC2, c_eq_2) {
     DWConvMicrokernelTester()
       .cr(2)
@@ -1007,10 +1007,10 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP1X9__WASM, c_eq_1) {
     DWConvMicrokernelTester()
       .cr(1)
@@ -1090,10 +1090,10 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP1X9__WASM_ACC2, c_eq_1) {
     DWConvMicrokernelTester()
       .cr(1)
@@ -1173,10 +1173,10 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP2X9__WASM, c_eq_2) {
     DWConvMicrokernelTester()
       .cr(2)
@@ -1276,10 +1276,10 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP2X9__WASM_ACC2, c_eq_2) {
     DWConvMicrokernelTester()
       .cr(2)
@@ -1379,10 +1379,10 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP1X25__WASM, c_eq_1) {
     DWConvMicrokernelTester()
       .cr(1)
@@ -1462,10 +1462,10 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP1X25__WASM_ACC2, c_eq_1) {
     DWConvMicrokernelTester()
       .cr(1)
@@ -1545,10 +1545,10 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP2X25__WASM, c_eq_2) {
     DWConvMicrokernelTester()
       .cr(2)
@@ -1648,10 +1648,10 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
-#if XNN_ARCH_WASM
+#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
   TEST(F32_DWCONV_UP2X25__WASM_ACC2, c_eq_2) {
     DWConvMicrokernelTester()
       .cr(2)
@@ -1751,7 +1751,7 @@
       }
     }
   }
-#endif  // XNN_ARCH_WASM
+#endif  // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD
 
 
 TEST(F32_DWCONV_UP1X4__SCALAR, c_eq_1) {