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XNNPACK Teamb455b122019-09-27 18:10:33 -07001// Copyright (c) Facebook, Inc. and its affiliates.
2// All rights reserved.
3//
4// Copyright 2019 Google LLC
5//
6// This source code is licensed under the BSD-style license found in the
7// LICENSE file in the root directory of this source tree.
8
9#pragma once
10
11#include <stddef.h>
12#include <stdint.h>
13
14#include <pthreadpool.h>
15
Zhi An Ngf9fc9ec2022-02-01 13:19:31 -080016#include <xnnpack/allocator.h>
Marat Dukhaneeaa7bd2019-10-25 17:31:25 -070017#include <xnnpack/params.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070018#include <xnnpack/compute.h>
19
20
21enum xnn_ukernel_type {
Marat Dukhanbef9a4d2020-11-19 13:29:28 -080022 xnn_ukernel_type_default = 0,
XNNPACK Teamb455b122019-09-27 18:10:33 -070023 xnn_ukernel_type_average_pooling,
Marat Dukhan1f29b802020-05-15 23:46:39 -070024 xnn_ukernel_type_conv2d_hwc2chw,
XNNPACK Teamb455b122019-09-27 18:10:33 -070025 xnn_ukernel_type_dwconv,
26 xnn_ukernel_type_gemm,
Marat Dukhan346a9e52019-11-15 09:06:30 -080027 xnn_ukernel_type_igemm,
XNNPACK Teamb455b122019-09-27 18:10:33 -070028 xnn_ukernel_type_pixelwise_average_pooling,
XNNPACK Teamb455b122019-09-27 18:10:33 -070029 xnn_ukernel_type_spmm,
30 xnn_ukernel_type_subconv2d,
XNNPACK Teamb455b122019-09-27 18:10:33 -070031 xnn_ukernel_type_vmulcaddc,
32};
33
34enum xnn_operator_type {
Marat Dukhan3b59de22020-06-03 20:15:19 -070035 xnn_operator_type_invalid = 0,
Marat Dukhan5020b962020-06-08 13:30:10 -070036 xnn_operator_type_abs_nc_f32,
Frank Barchard01898c02020-06-23 21:49:50 -070037 xnn_operator_type_add_nd_f16,
Marat Dukhanb1a0fc32019-12-02 19:32:02 -080038 xnn_operator_type_add_nd_f32,
Marat Dukhanff209482020-09-03 14:26:53 -070039 xnn_operator_type_add_nd_qs8,
Marat Dukhandb007cd2021-07-20 23:42:39 -070040 xnn_operator_type_add_nd_qu8,
Marat Dukhanefc47b82019-11-18 09:25:38 -080041 xnn_operator_type_argmax_pooling_nhwc_f32,
42 xnn_operator_type_average_pooling_nhwc_f32,
Marat Dukhan08b7a972020-07-14 18:17:29 -070043 xnn_operator_type_average_pooling_nhwc_qu8,
Marat Dukhan64e52512020-06-09 13:41:16 -070044 xnn_operator_type_bankers_rounding_nc_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080045 xnn_operator_type_channel_shuffle_nc_x8,
Marat Dukhan139e9612021-08-09 09:03:07 -070046 xnn_operator_type_channel_shuffle_nc_x32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080047 xnn_operator_type_clamp_nc_f32,
Marat Dukhan61c0c9e2021-08-16 23:16:14 -070048 xnn_operator_type_clamp_nc_s8,
Marat Dukhanefc47b82019-11-18 09:25:38 -080049 xnn_operator_type_clamp_nc_u8,
Marat Dukhan64e52512020-06-09 13:41:16 -070050 xnn_operator_type_ceiling_nc_f32,
Marat Dukhan139e9612021-08-09 09:03:07 -070051 xnn_operator_type_constant_pad_nd_x8,
Marat Dukhan065b11e2020-05-22 09:49:41 -070052 xnn_operator_type_constant_pad_nd_x32,
Marat Dukhanaf2ba002021-10-24 14:21:41 -070053 xnn_operator_type_convert_nc_f16_f32,
Marat Dukhana0c61682021-11-10 19:23:41 -080054 xnn_operator_type_convert_nc_f32_f16,
Marat Dukhaned2d7762021-12-03 23:51:19 -080055 xnn_operator_type_convert_nc_f32_qs8,
56 xnn_operator_type_convert_nc_f32_qu8,
Marat Dukhanf92206b2021-12-10 17:02:07 -080057 xnn_operator_type_convert_nc_qs8_f32,
58 xnn_operator_type_convert_nc_qu8_f32,
Marat Dukhan4e21b272020-06-04 18:45:01 -070059 xnn_operator_type_convolution_nchw_f32,
Frank Barchard49b4dcc2020-06-26 14:07:19 -070060 xnn_operator_type_convolution_nhwc_f16,
Marat Dukhanefc47b82019-11-18 09:25:38 -080061 xnn_operator_type_convolution_nhwc_f32,
Marat Dukhan97262462021-06-18 16:14:17 -070062 xnn_operator_type_convolution_nhwc_qc8,
Marat Dukhan16f1e1a2020-08-04 16:38:22 -070063 xnn_operator_type_convolution_nhwc_qs8,
Marat Dukhan08b7a972020-07-14 18:17:29 -070064 xnn_operator_type_convolution_nhwc_qu8,
Marat Dukhan4e21b272020-06-04 18:45:01 -070065 xnn_operator_type_copy_nc_x32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080066 xnn_operator_type_deconvolution_nhwc_f32,
Marat Dukhanbea849a2021-07-30 16:25:30 -070067 xnn_operator_type_deconvolution_nhwc_qs8,
Marat Dukhan08b7a972020-07-14 18:17:29 -070068 xnn_operator_type_deconvolution_nhwc_qu8,
Artsiom Ablavatskibbe85062020-11-05 14:07:37 -080069 xnn_operator_type_depth_to_space_nchw2nhwc_x32,
Marat Dukhan0e521172020-11-25 13:10:04 -080070 xnn_operator_type_depth_to_space_nhwc_x32,
Marat Dukhan69180502019-12-06 15:00:31 -080071 xnn_operator_type_divide_nd_f32,
Marat Dukhanb6bd4bc2020-12-01 17:01:40 -080072 xnn_operator_type_elu_nc_f32,
Marat Dukhaneec00522021-09-15 00:01:41 -070073 xnn_operator_type_elu_nc_qs8,
Marat Dukhanddb3d162021-10-25 17:05:51 -070074 xnn_operator_type_fully_connected_nc_f16,
Marat Dukhanefc47b82019-11-18 09:25:38 -080075 xnn_operator_type_fully_connected_nc_f32,
Marat Dukhand23cb6e2021-04-01 01:18:58 -070076 xnn_operator_type_fully_connected_nc_qs8,
Marat Dukhan08b7a972020-07-14 18:17:29 -070077 xnn_operator_type_fully_connected_nc_qu8,
Marat Dukhan64e52512020-06-09 13:41:16 -070078 xnn_operator_type_floor_nc_f32,
Frank Barchard7e2cbb02020-06-12 01:22:13 -070079 xnn_operator_type_global_average_pooling_nwc_f16,
Marat Dukhanefc47b82019-11-18 09:25:38 -080080 xnn_operator_type_global_average_pooling_nwc_f32,
Marat Dukhan9e0b5392020-08-07 02:29:34 -070081 xnn_operator_type_global_average_pooling_nwc_qs8,
Marat Dukhan08b7a972020-07-14 18:17:29 -070082 xnn_operator_type_global_average_pooling_nwc_qu8,
Marat Dukhanefc47b82019-11-18 09:25:38 -080083 xnn_operator_type_global_average_pooling_ncw_f32,
Frank Barcharda96948e2020-09-11 15:34:18 -070084 xnn_operator_type_hardswish_nc_f16,
Marat Dukhanefc47b82019-11-18 09:25:38 -080085 xnn_operator_type_hardswish_nc_f32,
Marat Dukhan28813332020-06-10 18:05:38 -070086 xnn_operator_type_leaky_relu_nc_f32,
Marat Dukhan08b7a972020-07-14 18:17:29 -070087 xnn_operator_type_leaky_relu_nc_qu8,
Marat Dukhanefc47b82019-11-18 09:25:38 -080088 xnn_operator_type_max_pooling_nhwc_f32,
Marat Dukhandc5c1482021-08-16 09:03:15 -070089 xnn_operator_type_max_pooling_nhwc_s8,
Marat Dukhanefc47b82019-11-18 09:25:38 -080090 xnn_operator_type_max_pooling_nhwc_u8,
Marat Dukhan79e7f842019-12-05 14:35:50 -080091 xnn_operator_type_maximum_nd_f32,
92 xnn_operator_type_minimum_nd_f32,
Frank Barchard0ea6a772020-09-09 15:26:31 -070093 xnn_operator_type_multiply_nd_f16,
Marat Dukhanefc47b82019-11-18 09:25:38 -080094 xnn_operator_type_multiply_nd_f32,
Marat Dukhan0853b8a2021-08-03 01:01:53 -070095 xnn_operator_type_multiply_nd_qs8,
96 xnn_operator_type_multiply_nd_qu8,
Marat Dukhan5020b962020-06-08 13:30:10 -070097 xnn_operator_type_negate_nc_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080098 xnn_operator_type_prelu_nc_f32,
Artsiom Ablavatski97918102020-10-27 15:52:59 -070099 xnn_operator_type_resize_bilinear_nchw_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -0800100 xnn_operator_type_resize_bilinear_nhwc_f32,
Marat Dukhan0ab75532021-11-24 16:50:30 -0800101 xnn_operator_type_resize_bilinear_nhwc_s8,
102 xnn_operator_type_resize_bilinear_nhwc_u8,
Marat Dukhanefc47b82019-11-18 09:25:38 -0800103 xnn_operator_type_sigmoid_nc_f32,
Marat Dukhan71a9bb12021-09-09 08:54:18 -0700104 xnn_operator_type_sigmoid_nc_qs8,
Marat Dukhan08b7a972020-07-14 18:17:29 -0700105 xnn_operator_type_sigmoid_nc_qu8,
Marat Dukhanfd8e6892020-01-27 15:25:25 -0800106 xnn_operator_type_softmax_nc_f32,
Marat Dukhan08b7a972020-07-14 18:17:29 -0700107 xnn_operator_type_softmax_nc_qu8,
Marat Dukhan5020b962020-06-08 13:30:10 -0700108 xnn_operator_type_square_nc_f32,
Marat Dukhan6804bbd2020-06-30 19:26:11 -0700109 xnn_operator_type_square_root_nc_f32,
Marat Dukhanf7399262020-06-05 10:58:44 -0700110 xnn_operator_type_squared_difference_nd_f32,
Marat Dukhan05f3f6d2019-12-03 15:13:53 -0800111 xnn_operator_type_subtract_nd_f32,
Marat Dukhan8e2fd202021-09-07 18:42:01 -0700112 xnn_operator_type_subtract_nd_qs8,
113 xnn_operator_type_subtract_nd_qu8,
Marat Dukhan5de7bc02021-09-09 19:04:01 -0700114 xnn_operator_type_tanh_nc_qs8,
115 xnn_operator_type_tanh_nc_qu8,
Marat Dukhan64e52512020-06-09 13:41:16 -0700116 xnn_operator_type_truncation_nc_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -0800117 xnn_operator_type_unpooling_nhwc_x32,
XNNPACK Teamb455b122019-09-27 18:10:33 -0700118};
119
Marat Dukhan1f29b802020-05-15 23:46:39 -0700120struct xnn_ukernel_conv2d {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700121 union {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700122 xnn_conv_hwc2chw_ukernel_function hwc2chw_function;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700123 xnn_conv_hwc_ukernel_function hwc_function;
124 };
125 uint8_t output_height_tile;
126 uint8_t output_channel_tile;
127};
128
129struct xnn_ukernel_dwconv {
130 union {
Marat Dukhanaefaef32020-04-09 07:09:34 -0700131 xnn_dwconv_unipass_ukernel_function unipass_function;
132 xnn_dwconv_multipass_ukernel_function multipass_function;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700133 };
Marat Dukhanaefaef32020-04-09 07:09:34 -0700134 uint8_t primary_tile;
135 uint8_t incremental_tile;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700136};
137
138// Direct 2D Depthwise Convolution
139struct xnn_ukernel_dwconv2d {
140 union {
Marat Dukhanbf715f92020-10-23 20:17:00 -0700141 xnn_dwconv2d_chw_ukernel_function chw_function;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700142 };
XNNPACK Teamb455b122019-09-27 18:10:33 -0700143 uint8_t output_width_tile;
144};
145
146struct xnn_ukernel_gemm {
Marat Dukhan05702cf2020-03-26 15:41:33 -0700147 struct xnn_hmp_gemm_ukernel general_case;
148 struct xnn_hmp_gemm_ukernel mr1_case;
Zhi An Ng3deae1d2022-02-01 14:33:29 -0800149#if XNN_PLATFORM_JIT
Zhi An Ngf9fc9ec2022-02-01 13:19:31 -0800150 struct xnn_code_buffer general_code_buffer;
151 struct xnn_code_buffer mr1_code_buffer;
Zhi An Ng3deae1d2022-02-01 14:33:29 -0800152#endif // XNN_PLATFORM_JIT
XNNPACK Teamb455b122019-09-27 18:10:33 -0700153 uint8_t mr;
154 uint8_t nr;
155 uint8_t kr;
Marat Dukhanfbd67a72022-01-31 18:03:50 -0800156 uint8_t sr;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700157};
158
159struct xnn_ukernel_igemm {
Marat Dukhan05702cf2020-03-26 15:41:33 -0700160 struct xnn_hmp_igemm_ukernel general_case;
161 struct xnn_hmp_igemm_ukernel mr1_case;
162 struct xnn_hmp_gemm_ukernel gemm_case;
Zhi An Ng3deae1d2022-02-01 14:33:29 -0800163#if XNN_PLATFORM_JIT
Zhi An Ngf9fc9ec2022-02-01 13:19:31 -0800164 struct xnn_code_buffer general_code_buffer;
165 struct xnn_code_buffer mr1_code_buffer;
Zhi An Ng3deae1d2022-02-01 14:33:29 -0800166#endif // XNN_PLATFORM_JIT
XNNPACK Teamb455b122019-09-27 18:10:33 -0700167 uint8_t mr;
168 uint8_t nr;
169 uint8_t kr;
Marat Dukhanfbd67a72022-01-31 18:03:50 -0800170 uint8_t sr;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700171};
172
173struct xnn_ukernel_spmm {
174 xnn_spmm_ukernel_function function;
175 uint8_t mr;
176};
177
178struct xnn_ukernel_vmulcaddc {
179 xnn_vmulcaddc_ukernel_function function;
180 uint8_t mr;
181};
182
Frank Barchardc67dd7f2020-07-06 11:23:57 -0700183struct xnn_ukernel_vbinary {
Frank Barchard65beb1a2020-07-20 16:40:02 -0700184 xnn_vbinary_ukernel_function op_function;
185 xnn_vbinary_ukernel_function opc_function;
186 xnn_vbinary_ukernel_function ropc_function;
Frank Barchardc67dd7f2020-07-06 11:23:57 -0700187};
188
Frank Barchard62c5e232020-07-21 17:42:19 -0700189struct xnn_ukernel_vunary {
190 xnn_vunary_ukernel_function function;
191};
192
XNNPACK Teamb455b122019-09-27 18:10:33 -0700193struct xnn_ukernel {
194 enum xnn_ukernel_type type;
195 union {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700196 struct xnn_ukernel_conv2d conv2d;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700197 struct xnn_ukernel_dwconv dwconv;
198 struct xnn_ukernel_dwconv2d dwconv2d;
199 struct xnn_ukernel_gemm gemm;
200 struct xnn_ukernel_igemm igemm;
201 struct xnn_ukernel_spmm spmm;
202 struct xnn_ukernel_vmulcaddc vmulcaddc;
Frank Barchardc67dd7f2020-07-06 11:23:57 -0700203 struct xnn_ukernel_vbinary vbinary;
Frank Barchard62c5e232020-07-21 17:42:19 -0700204 struct xnn_ukernel_vunary vunary;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700205 };
206};
207
208enum xnn_run_state {
209 xnn_run_state_invalid = 0,
210 xnn_run_state_ready,
211 xnn_run_state_skip,
212};
213
214struct subconvolution_params {
215 void* weights;
216 size_t w_stride;
217 const void** indirection_buffer;
218 void* output;
219 size_t slice_width;
220 size_t slice_height;
221 size_t indirection_y_stride;
222 size_t indirection_x_stride;
Marat Dukhan80fc9322019-09-29 21:06:36 -0700223 // scaled_kernel_size := kernel_size * mr * sizeof(void*).
XNNPACK Teamb455b122019-09-27 18:10:33 -0700224 size_t scaled_kernel_size;
225};
226
227struct xnn_operator {
228 size_t batch_size;
229 uint32_t padding_top;
230 uint32_t padding_right;
231 uint32_t padding_bottom;
232 uint32_t padding_left;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700233 uint32_t kernel_height;
234 uint32_t kernel_width;
235 uint32_t stride_height;
236 uint32_t stride_width;
237 uint32_t dilation_height;
238 uint32_t dilation_width;
239 uint32_t groups;
240 size_t group_channels;
241 size_t group_input_channels;
242 size_t group_output_channels;
243 size_t channels;
244
245 size_t pad_before_channels;
246 size_t pad_after_channels;
247 uint32_t pad_value;
248
249 size_t input_height;
250 size_t input_width;
251 size_t input_pixel_stride;
252 const void* input;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700253 const void* input2;
Marat Dukhan322b21e2020-11-24 21:30:38 -0800254 const void** indirection_buffer;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700255
256 size_t output_height;
257 size_t output_width;
258 size_t output_pixel_stride;
259 void* output;
260
261 void* packed_weights;
262 // Total number of non-zero kernel elements when weights use sparse representation.
263 size_t num_nonzero_values;
264 // Total number of non-zero kernel blocks when weights use sparse representation.
265 size_t num_nonzero_blocks;
266 // Total number of output channel blocks when weights use sparse representation.
267 size_t num_output_channel_blocks;
268 // Input channel corresponding to the first non-zero kernel element.
269 size_t first_input_channel;
270
271 float input_scale;
272 float output_scale;
Marat Dukhan54e95a02020-08-06 23:55:13 -0700273 int32_t input_zero_point;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700274 uint8_t output_zero_point;
275 uint8_t output_min;
276 uint8_t output_max;
277
278 size_t valid_batch_size;
279 size_t last_input_height;
280 size_t last_input_width;
281 const void* last_input;
Marat Dukhan69722492019-11-11 19:55:50 -0800282 size_t last_output_height;
283 size_t last_output_width;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700284 void* last_output;
285
Artsiom Ablavatskibbe85062020-11-05 14:07:37 -0800286 uint32_t block_size;
287
XNNPACK Teamb455b122019-09-27 18:10:33 -0700288 void* zero_buffer;
289 void* lookup_table;
290 void* pixelwise_buffer;
291 struct subconvolution_params* subconvolution_buffer;
Marat Dukhan8440fde2019-10-24 12:46:13 -0700292 uint32_t flags;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700293
294 union {
Marat Dukhan134f9842021-12-29 19:57:31 -0800295 union xnn_f16_f32_cvt_params f16_f32_cvt;
Marat Dukhan14dd8d02022-01-06 16:03:31 -0800296 union xnn_f16_hswish_params f16_hswish;
Marat Dukhan5020b962020-06-08 13:30:10 -0700297 union xnn_f32_abs_params f32_abs;
Marat Dukhane5efb162021-12-31 10:26:13 -0800298 union xnn_f32_default_params f32_default;
Marat Dukhanb6bd4bc2020-12-01 17:01:40 -0800299 union xnn_f32_elu_params f32_elu;
Marat Dukhan28813332020-06-10 18:05:38 -0700300 union xnn_f32_lrelu_params f32_lrelu;
Marat Dukhan5020b962020-06-08 13:30:10 -0700301 union xnn_f32_neg_params f32_neg;
Marat Dukhan64e52512020-06-09 13:41:16 -0700302 union xnn_f32_rnd_params f32_rnd;
Marat Dukhance834ad2022-01-03 00:22:01 -0800303 union xnn_f32_sigmoid_params f32_sigmoid;
Marat Dukhane72b2822021-12-30 14:46:58 -0800304 union xnn_f32_sqrt_params f32_sqrt;
Marat Dukhan5868d802020-03-19 17:18:45 -0700305 // Parameters for Global Average Pooling in CHW layout
Marat Dukhanc3065f52020-06-04 13:33:32 -0700306 union xnn_f32_gavgpool_params f32_gavgpool;
307 union xnn_f32_hswish_params f32_hswish;
Marat Dukhan14dd8d02022-01-06 16:03:31 -0800308 union xnn_f16_minmax_params f16_minmax;
309 union xnn_f16_scaleminmax_params f16_scaleminmax;
Marat Dukhan8452ff52020-04-08 20:44:58 -0700310 // Pixelwise Average Pooling normally use f32_minmax_params, but also initialize
311 // f32_scaleminmax_params in case it needs to switch to Global Average Pooling operation.
Marat Dukhan5868d802020-03-19 17:18:45 -0700312 struct {
Marat Dukhanc3065f52020-06-04 13:33:32 -0700313 union xnn_f32_minmax_params f32_minmax;
314 union xnn_f32_scaleminmax_params f32_scaleminmax;
Marat Dukhan5868d802020-03-19 17:18:45 -0700315 };
Marat Dukhanc3065f52020-06-04 13:33:32 -0700316 union xnn_f32_chw_params f32_chw;
Marat Dukhanb7c1b712021-12-30 07:23:57 -0800317 union xnn_f32_f16_cvt_params f32_f16_cvt;
Marat Dukhaned2d7762021-12-03 23:51:19 -0800318 union xnn_f32_qs8_cvt_params f32_qs8_cvt;
319 union xnn_f32_qu8_cvt_params f32_qu8_cvt;
Marat Dukhanf92206b2021-12-10 17:02:07 -0800320 union xnn_qs8_f32_cvt_params qs8_f32_cvt;
321 union xnn_qu8_f32_cvt_params qu8_f32_cvt;
Marat Dukhane3d17bf2021-05-24 22:22:43 -0700322 union xnn_qs8_conv_minmax_params qs8_conv_minmax;
Marat Dukhan9e0b5392020-08-07 02:29:34 -0700323 // Average Pooling normally use qs8_avgpool_params, but also initialize qs8_gavgpool_params in case it needs to switch
324 // to Global Average Pooling operation.
325 struct {
Marat Dukhan5d456ce2022-01-07 16:07:54 -0800326 union xnn_qs8_avgpool_minmax_params qs8_avgpool;
327 union xnn_qs8_avgpool_minmax_params qs8_gavgpool;
Marat Dukhan9e0b5392020-08-07 02:29:34 -0700328 };
Marat Dukhanff209482020-09-03 14:26:53 -0700329 // Quantized Add parameters are sensitive to order of inputs, so we initialize an extra copy with the reversed order.
330 struct {
Marat Dukhan64287252021-09-07 16:20:03 -0700331 union xnn_qs8_addsub_minmax_params qs8_addsub;
332 union xnn_qs8_addsub_minmax_params qs8_raddsub;
Marat Dukhanff209482020-09-03 14:26:53 -0700333 };
Marat Dukhandb007cd2021-07-20 23:42:39 -0700334 struct {
Marat Dukhan0853b8a2021-08-03 01:01:53 -0700335 union xnn_qs8_mul_minmax_params qs8_mul;
336 union xnn_qs8_mul_minmax_params qs8_rmul;
337 };
338 struct {
Marat Dukhan64287252021-09-07 16:20:03 -0700339 union xnn_qu8_addsub_minmax_params qu8_addsub;
340 union xnn_qu8_addsub_minmax_params qu8_raddsub;
Marat Dukhandb007cd2021-07-20 23:42:39 -0700341 };
Marat Dukhan0853b8a2021-08-03 01:01:53 -0700342 struct {
343 union xnn_qu8_mul_minmax_params qu8_mul;
344 union xnn_qu8_mul_minmax_params qu8_rmul;
345 };
Marat Dukhane3d17bf2021-05-24 22:22:43 -0700346 union xnn_qu8_conv_minmax_params qu8_conv_minmax;
Marat Dukhan08b7a972020-07-14 18:17:29 -0700347 // Average Pooling normally use qu8_avgpool_params, but also initialize qu8_gavgpool_params in case it needs to switch
Marat Dukhan5868d802020-03-19 17:18:45 -0700348 // to Global Average Pooling operation.
349 struct {
Marat Dukhan5d456ce2022-01-07 16:07:54 -0800350 union xnn_qu8_avgpool_minmax_params qu8_avgpool;
351 union xnn_qu8_avgpool_minmax_params qu8_gavgpool;
Marat Dukhan5868d802020-03-19 17:18:45 -0700352 };
Marat Dukhandc5c1482021-08-16 09:03:15 -0700353 union xnn_s8_minmax_params s8_minmax;
Marat Dukhanc3065f52020-06-04 13:33:32 -0700354 union xnn_u8_minmax_params u8_minmax;
355 } params;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700356 enum xnn_operator_type type;
357 struct xnn_ukernel ukernel;
358
359 struct compute_parameters compute;
360 struct compute_parameters compute2;
361 union {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700362 struct argmax_pooling_context argmax_pooling;
363 struct average_pooling_context average_pooling;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700364 struct channel_shuffle_context channel_shuffle;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700365 struct conv2d_context conv2d;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700366 struct dwconv2d_context dwconv2d;
367 struct dwconv_context dwconv;
Marat Dukhanad71b9a2020-11-20 00:01:51 -0800368 struct depthtospace2d_chw2hwc_context depthtospace2d_chw;
Marat Dukhan0e521172020-11-25 13:10:04 -0800369 struct depthtospace2d_hwc_context depthtospace2d_hwc;
Marat Dukhanca2733c2019-11-15 23:21:17 -0800370 struct elementwise_binary_context elementwise_binary;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700371 struct gemm_context gemm;
Marat Dukhanefc47b82019-11-18 09:25:38 -0800372 struct global_average_pooling_nwc_context global_average_pooling_nwc;
373 struct global_average_pooling_ncw_context global_average_pooling_ncw;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700374 struct igemm_context igemm;
375 struct lut_contiguous_context lut_contiguous;
376 struct lut_strided_context lut_strided;
377 struct max_pooling_context max_pooling;
Marat Dukhan4662b192020-05-21 15:52:03 -0700378 struct pad_context pad;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700379 struct pixelwise_average_pooling_context pixelwise_average_pooling;
380 struct prelu_context prelu;
Marat Dukhan69722492019-11-11 19:55:50 -0800381 struct resize_bilinear_context resize_bilinear;
Artsiom Ablavatski97918102020-10-27 15:52:59 -0700382 struct resize_bilinear_chw_context resize_bilinear_chw;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700383 struct spmm_context spmm;
384 struct subconv_context subconv;
Marat Dukhan29954272020-02-13 17:56:11 -0800385 struct subgemm_context subgemm;
Marat Dukhanfd8e6892020-01-27 15:25:25 -0800386 struct f32_three_pass_softmax_context f32_three_pass_softmax;
387 struct u8_softmax_context u8_softmax;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700388 struct univector_contiguous_context univector_contiguous;
389 struct univector_strided_context univector_strided;
390 struct unpooling_context unpooling;
391 struct vmulcaddc_context vmulcaddc;
392 } context;
393
394 enum xnn_run_state state;
Marat Dukhan9cbaa632020-11-24 21:28:50 -0800395};