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XNNPACK Teamb455b122019-09-27 18:10:33 -07001// Copyright (c) Facebook, Inc. and its affiliates.
2// All rights reserved.
3//
4// Copyright 2019 Google LLC
5//
6// This source code is licensed under the BSD-style license found in the
7// LICENSE file in the root directory of this source tree.
8
9#pragma once
10
11#include <stddef.h>
12#include <stdint.h>
13
14#include <pthreadpool.h>
15
Marat Dukhaneeaa7bd2019-10-25 17:31:25 -070016#include <xnnpack/params.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070017#include <xnnpack/compute.h>
18
19
20enum xnn_ukernel_type {
21 xnn_ukernel_type_none = 0,
22 xnn_ukernel_type_add,
23 xnn_ukernel_type_argmax_pooling,
24 xnn_ukernel_type_average_pooling,
Marat Dukhanb1a0fc32019-12-02 19:32:02 -080025 xnn_ukernel_type_binary_elementwise,
XNNPACK Teamb455b122019-09-27 18:10:33 -070026 xnn_ukernel_type_channel_shuffle,
27 xnn_ukernel_type_clamp,
Marat Dukhan1f29b802020-05-15 23:46:39 -070028 xnn_ukernel_type_conv2d_hwc2chw,
XNNPACK Teamb455b122019-09-27 18:10:33 -070029 xnn_ukernel_type_dwconv,
30 xnn_ukernel_type_gemm,
31 xnn_ukernel_type_global_average_pooling,
32 xnn_ukernel_type_hswish,
Marat Dukhan346a9e52019-11-15 09:06:30 -080033 xnn_ukernel_type_igemm,
XNNPACK Teamb455b122019-09-27 18:10:33 -070034 xnn_ukernel_type_lut,
35 xnn_ukernel_type_max_pooling,
36 xnn_ukernel_type_pad,
37 xnn_ukernel_type_pixelwise_average_pooling,
38 xnn_ukernel_type_prelu,
Marat Dukhan346a9e52019-11-15 09:06:30 -080039 xnn_ukernel_type_sigmoid,
Marat Dukhanfd8e6892020-01-27 15:25:25 -080040 xnn_ukernel_type_softmax,
XNNPACK Teamb455b122019-09-27 18:10:33 -070041 xnn_ukernel_type_spmm,
42 xnn_ukernel_type_subconv2d,
43 xnn_ukernel_type_unpooling,
44 xnn_ukernel_type_vmulcaddc,
45};
46
47enum xnn_operator_type {
48 xnn_operator_type_none = 0,
Marat Dukhanefc47b82019-11-18 09:25:38 -080049 xnn_operator_type_add_nc_f32,
Marat Dukhanb1a0fc32019-12-02 19:32:02 -080050 xnn_operator_type_add_nd_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080051 xnn_operator_type_add_nc_q8,
52 xnn_operator_type_argmax_pooling_nhwc_f32,
53 xnn_operator_type_average_pooling_nhwc_f32,
54 xnn_operator_type_average_pooling_nhwc_q8,
55 xnn_operator_type_channel_pad_nc_x32,
56 xnn_operator_type_channel_shuffle_nc_x32,
57 xnn_operator_type_channel_shuffle_nc_x8,
58 xnn_operator_type_clamp_nc_f32,
59 xnn_operator_type_clamp_nc_u8,
60 xnn_operator_type_convolution_nhwc_f32,
61 xnn_operator_type_convolution_nhwc_q8,
62 xnn_operator_type_convolution_nchw_f32,
63 xnn_operator_type_deconvolution_nhwc_f32,
64 xnn_operator_type_deconvolution_nhwc_q8,
Marat Dukhan69180502019-12-06 15:00:31 -080065 xnn_operator_type_divide_nd_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080066 xnn_operator_type_fully_connected_nc_f32,
67 xnn_operator_type_fully_connected_nc_q8,
68 xnn_operator_type_global_average_pooling_nwc_f32,
69 xnn_operator_type_global_average_pooling_nwc_q8,
70 xnn_operator_type_global_average_pooling_ncw_f32,
71 xnn_operator_type_hardswish_nc_f32,
72 xnn_operator_type_leaky_relu_nc_q8,
73 xnn_operator_type_max_pooling_nhwc_f32,
74 xnn_operator_type_max_pooling_nhwc_u8,
Marat Dukhan79e7f842019-12-05 14:35:50 -080075 xnn_operator_type_maximum_nd_f32,
76 xnn_operator_type_minimum_nd_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080077 xnn_operator_type_multiply_nd_f32,
Marat Dukhan4662b192020-05-21 15:52:03 -070078 xnn_operator_type_pad_nd_x32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080079 xnn_operator_type_prelu_nc_f32,
80 xnn_operator_type_resize_bilinear_nhwc_f32,
81 xnn_operator_type_sigmoid_nc_f32,
82 xnn_operator_type_sigmoid_nc_q8,
Marat Dukhanfd8e6892020-01-27 15:25:25 -080083 xnn_operator_type_softmax_nc_f32,
84 xnn_operator_type_softmax_nc_q8,
Marat Dukhan05f3f6d2019-12-03 15:13:53 -080085 xnn_operator_type_subtract_nd_f32,
Marat Dukhanefc47b82019-11-18 09:25:38 -080086 xnn_operator_type_unpooling_nhwc_x32,
XNNPACK Teamb455b122019-09-27 18:10:33 -070087};
88
Marat Dukhan1f29b802020-05-15 23:46:39 -070089struct xnn_ukernel_conv2d {
XNNPACK Teamb455b122019-09-27 18:10:33 -070090 union {
Marat Dukhan1f29b802020-05-15 23:46:39 -070091 xnn_conv_hwc2chw_ukernel_function hwc2chw_function;
XNNPACK Teamb455b122019-09-27 18:10:33 -070092 xnn_conv_hwc_ukernel_function hwc_function;
93 };
94 uint8_t output_height_tile;
95 uint8_t output_channel_tile;
96};
97
98struct xnn_ukernel_dwconv {
99 union {
Marat Dukhanaefaef32020-04-09 07:09:34 -0700100 xnn_dwconv_unipass_ukernel_function unipass_function;
101 xnn_dwconv_multipass_ukernel_function multipass_function;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700102 };
Marat Dukhanaefaef32020-04-09 07:09:34 -0700103 uint8_t primary_tile;
104 uint8_t incremental_tile;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700105};
106
107// Direct 2D Depthwise Convolution
108struct xnn_ukernel_dwconv2d {
109 union {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700110 xnn_dwconv_chw_ukernel_function chw_function;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700111 };
112 uint8_t input_width_tile;
113 uint8_t output_width_tile;
114};
115
116struct xnn_ukernel_gemm {
Marat Dukhan05702cf2020-03-26 15:41:33 -0700117 struct xnn_hmp_gemm_ukernel general_case;
118 struct xnn_hmp_gemm_ukernel mr1_case;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700119 uint8_t mr;
120 uint8_t nr;
121 uint8_t kr;
122};
123
124struct xnn_ukernel_igemm {
Marat Dukhan05702cf2020-03-26 15:41:33 -0700125 struct xnn_hmp_igemm_ukernel general_case;
126 struct xnn_hmp_igemm_ukernel mr1_case;
127 struct xnn_hmp_gemm_ukernel gemm_case;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700128 uint8_t mr;
129 uint8_t nr;
130 uint8_t kr;
131};
132
133struct xnn_ukernel_spmm {
134 xnn_spmm_ukernel_function function;
135 uint8_t mr;
136};
137
138struct xnn_ukernel_vmulcaddc {
139 xnn_vmulcaddc_ukernel_function function;
140 uint8_t mr;
141};
142
143struct xnn_ukernel {
144 enum xnn_ukernel_type type;
145 union {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700146 struct xnn_ukernel_conv2d conv2d;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700147 struct xnn_ukernel_dwconv dwconv;
148 struct xnn_ukernel_dwconv2d dwconv2d;
149 struct xnn_ukernel_gemm gemm;
150 struct xnn_ukernel_igemm igemm;
151 struct xnn_ukernel_spmm spmm;
152 struct xnn_ukernel_vmulcaddc vmulcaddc;
153 };
154};
155
156enum xnn_run_state {
157 xnn_run_state_invalid = 0,
158 xnn_run_state_ready,
159 xnn_run_state_skip,
160};
161
162struct subconvolution_params {
163 void* weights;
164 size_t w_stride;
165 const void** indirection_buffer;
166 void* output;
167 size_t slice_width;
168 size_t slice_height;
169 size_t indirection_y_stride;
170 size_t indirection_x_stride;
Marat Dukhan80fc9322019-09-29 21:06:36 -0700171 // scaled_kernel_size := kernel_size * mr * sizeof(void*).
XNNPACK Teamb455b122019-09-27 18:10:33 -0700172 size_t scaled_kernel_size;
173};
174
175struct xnn_operator {
176 size_t batch_size;
177 uint32_t padding_top;
178 uint32_t padding_right;
179 uint32_t padding_bottom;
180 uint32_t padding_left;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700181 uint32_t kernel_height;
182 uint32_t kernel_width;
183 uint32_t stride_height;
184 uint32_t stride_width;
185 uint32_t dilation_height;
186 uint32_t dilation_width;
187 uint32_t groups;
188 size_t group_channels;
189 size_t group_input_channels;
190 size_t group_output_channels;
191 size_t channels;
192
193 size_t pad_before_channels;
194 size_t pad_after_channels;
195 uint32_t pad_value;
196
197 size_t input_height;
198 size_t input_width;
199 size_t input_pixel_stride;
200 const void* input;
201 const void** indirection_buffer;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700202
203 size_t input2_pixel_stride;
204 const void* input2;
205
206 size_t output_height;
207 size_t output_width;
208 size_t output_pixel_stride;
209 void* output;
210
211 void* packed_weights;
212 // Total number of non-zero kernel elements when weights use sparse representation.
213 size_t num_nonzero_values;
214 // Total number of non-zero kernel blocks when weights use sparse representation.
215 size_t num_nonzero_blocks;
216 // Total number of output channel blocks when weights use sparse representation.
217 size_t num_output_channel_blocks;
218 // Input channel corresponding to the first non-zero kernel element.
219 size_t first_input_channel;
220
221 float input_scale;
222 float output_scale;
223 uint8_t input_zero_point;
224 uint8_t kernel_zero_point;
225 uint8_t output_zero_point;
226 uint8_t output_min;
227 uint8_t output_max;
228
229 size_t valid_batch_size;
230 size_t last_input_height;
231 size_t last_input_width;
232 const void* last_input;
Marat Dukhan69722492019-11-11 19:55:50 -0800233 size_t last_output_height;
234 size_t last_output_width;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700235 void* last_output;
236
237 void* zero_buffer;
238 void* lookup_table;
239 void* pixelwise_buffer;
240 struct subconvolution_params* subconvolution_buffer;
Marat Dukhan8440fde2019-10-24 12:46:13 -0700241 uint32_t flags;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700242
243 union {
Marat Dukhan5868d802020-03-19 17:18:45 -0700244 // Parameters for Global Average Pooling in CHW layout
XNNPACK Teamb455b122019-09-27 18:10:33 -0700245 union xnn_f32_gavgpool_params f32_gavgpool_params;
246 union xnn_f32_hswish_params f32_hswish_params;
Marat Dukhan8452ff52020-04-08 20:44:58 -0700247 // Pixelwise Average Pooling normally use f32_minmax_params, but also initialize
248 // f32_scaleminmax_params in case it needs to switch to Global Average Pooling operation.
Marat Dukhan5868d802020-03-19 17:18:45 -0700249 struct {
Marat Dukhan8452ff52020-04-08 20:44:58 -0700250 union xnn_f32_scaleminmax_params f32_scaleminmax_params;
Marat Dukhaneb09a6b2020-04-08 17:34:32 -0700251 union xnn_f32_minmax_params f32_minmax_params;
Marat Dukhan5868d802020-03-19 17:18:45 -0700252 };
Marat Dukhan1f29b802020-05-15 23:46:39 -0700253 union xnn_f32_chw_params f32_chw_params;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700254 union xnn_q8_add_params q8_add_params;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700255 union xnn_q8_gemm_params q8_gemm_params;
Marat Dukhan5868d802020-03-19 17:18:45 -0700256 // Average Pooling normally use q8_avgpool_params, but also initialize q8_gavgpool_params in case it needs to switch
257 // to Global Average Pooling operation.
258 struct {
259 union xnn_q8_avgpool_params q8_avgpool_params;
260 union xnn_q8_avgpool_params q8_gavgpool_params;
261 };
Marat Dukhaneb09a6b2020-04-08 17:34:32 -0700262 union xnn_u8_minmax_params u8_minmax_params;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700263 };
264 enum xnn_operator_type type;
265 struct xnn_ukernel ukernel;
266
267 struct compute_parameters compute;
268 struct compute_parameters compute2;
269 union {
270 struct add_contiguous_context add_contiguous;
271 struct add_strided_context add_strided;
272 struct argmax_pooling_context argmax_pooling;
273 struct average_pooling_context average_pooling;
274 struct channel_pad_context channel_pad;
275 struct channel_shuffle_context channel_shuffle;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700276 struct conv2d_context conv2d;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700277 struct dwconv2d_context dwconv2d;
278 struct dwconv_context dwconv;
Marat Dukhanca2733c2019-11-15 23:21:17 -0800279 struct elementwise_binary_context elementwise_binary;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700280 struct gemm_context gemm;
Marat Dukhanefc47b82019-11-18 09:25:38 -0800281 struct global_average_pooling_nwc_context global_average_pooling_nwc;
282 struct global_average_pooling_ncw_context global_average_pooling_ncw;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700283 struct igemm_context igemm;
284 struct lut_contiguous_context lut_contiguous;
285 struct lut_strided_context lut_strided;
286 struct max_pooling_context max_pooling;
Marat Dukhan4662b192020-05-21 15:52:03 -0700287 struct pad_context pad;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700288 struct pixelwise_average_pooling_context pixelwise_average_pooling;
289 struct prelu_context prelu;
Marat Dukhan69722492019-11-11 19:55:50 -0800290 struct resize_bilinear_context resize_bilinear;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700291 struct spmm_context spmm;
292 struct subconv_context subconv;
Marat Dukhan29954272020-02-13 17:56:11 -0800293 struct subgemm_context subgemm;
Marat Dukhanfd8e6892020-01-27 15:25:25 -0800294 struct f32_three_pass_softmax_context f32_three_pass_softmax;
295 struct u8_softmax_context u8_softmax;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700296 struct univector_contiguous_context univector_contiguous;
297 struct univector_strided_context univector_strided;
298 struct unpooling_context unpooling;
299 struct vmulcaddc_context vmulcaddc;
300 } context;
301
302 enum xnn_run_state state;
303};