Marat Dukhan | 4a7b70f | 2021-08-02 18:18:10 -0700 | [diff] [blame^] | 1 | // Auto-generated file. Do not edit! |
| 2 | // Template: src/qs8-vmul/neon.c.in |
| 3 | // Generator: tools/xngen |
| 4 | // |
| 5 | // Copyright 2021 Google LLC |
| 6 | // |
| 7 | // This source code is licensed under the BSD-style license found in the |
| 8 | // LICENSE file in the root directory of this source tree. |
| 9 | |
| 10 | #include <assert.h> |
| 11 | |
| 12 | #include <arm_neon.h> |
| 13 | |
| 14 | #include <xnnpack/vadd.h> |
| 15 | |
| 16 | |
| 17 | void xnn_qu8_vmul_minmax_fp32_ukernel__neon_ld64_x8( |
| 18 | size_t n, |
| 19 | const uint8_t* input_a, |
| 20 | const uint8_t* input_b, |
| 21 | uint8_t* output, |
| 22 | const union xnn_qu8_mul_minmax_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_DISABLE_TSAN XNN_DISABLE_MSAN |
| 23 | { |
| 24 | const uint8x8_t va_zero_point = vld1_dup_u8(¶ms->fp32_neon.a_zero_point); |
| 25 | const uint8x8_t vb_zero_point = vld1_dup_u8(¶ms->fp32_neon.b_zero_point); |
| 26 | const float32x4_t vscale = vld1q_dup_f32(¶ms->fp32_neon.scale); |
| 27 | const float32x4_t voutput_min_less_zero_point = vld1q_dup_f32(¶ms->fp32_neon.output_min_less_zero_point); |
| 28 | const float32x4_t voutput_max_less_zero_point = vld1q_dup_f32(¶ms->fp32_neon.output_max_less_zero_point); |
| 29 | const float32x4_t vmagic_bias = vld1q_dup_f32(¶ms->fp32_neon.magic_bias); |
| 30 | const int32x4_t vmagic_bias_less_zero_point = vld1q_dup_s32(¶ms->fp32_neon.magic_bias_less_zero_point); |
| 31 | |
| 32 | for (; n >= 8 * sizeof(uint8_t); n -= 8 * sizeof(uint8_t)) { |
| 33 | const uint8x8_t va01234567 = vld1_u8(input_a); input_a += 8; |
| 34 | const uint8x8_t vb01234567 = vld1_u8(input_b); input_b += 8; |
| 35 | |
| 36 | const int16x8_t vxa01234567 = vreinterpretq_s16_u16(vsubl_u8(va01234567, va_zero_point)); |
| 37 | const int16x8_t vxb01234567 = vreinterpretq_s16_u16(vsubl_u8(vb01234567, vb_zero_point)); |
| 38 | |
| 39 | int32x4_t vacc0123 = vmull_s16(vget_low_s16(vxa01234567), vget_low_s16(vxb01234567)); |
| 40 | int32x4_t vacc4567 = vmull_s16(vget_high_s16(vxa01234567), vget_high_s16(vxb01234567)); |
| 41 | |
| 42 | float32x4_t vfpacc0123 = vcvtq_f32_s32(vacc0123); |
| 43 | float32x4_t vfpacc4567 = vcvtq_f32_s32(vacc4567); |
| 44 | |
| 45 | vfpacc0123 = vmulq_f32(vfpacc0123, vscale); |
| 46 | vfpacc4567 = vmulq_f32(vfpacc4567, vscale); |
| 47 | |
| 48 | vfpacc0123 = vmaxq_f32(vfpacc0123, voutput_min_less_zero_point); |
| 49 | vfpacc4567 = vmaxq_f32(vfpacc4567, voutput_min_less_zero_point); |
| 50 | |
| 51 | vfpacc0123 = vminq_f32(vfpacc0123, voutput_max_less_zero_point); |
| 52 | vfpacc4567 = vminq_f32(vfpacc4567, voutput_max_less_zero_point); |
| 53 | |
| 54 | vacc0123 = vreinterpretq_s32_f32(vaddq_f32(vfpacc0123, vmagic_bias)); |
| 55 | vacc4567 = vreinterpretq_s32_f32(vaddq_f32(vfpacc4567, vmagic_bias)); |
| 56 | |
| 57 | vacc0123 = vsubq_s32(vacc0123, vmagic_bias_less_zero_point); |
| 58 | vacc4567 = vsubq_s32(vacc4567, vmagic_bias_less_zero_point); |
| 59 | |
| 60 | #if XNN_ARCH_ARM64 |
| 61 | const int16x8_t vacc01234567 = vuzp1q_s16(vreinterpretq_s16_s32(vacc0123), vreinterpretq_s16_s32(vacc4567)); |
| 62 | |
| 63 | uint8x8_t vout01234567 = vreinterpret_u8_s8(vmovn_s16(vacc01234567)); |
| 64 | #else |
| 65 | const int16x8_t vacc01234567 = vcombine_s16(vmovn_s32(vacc0123), vmovn_s32(vacc4567)); |
| 66 | |
| 67 | uint8x8_t vout01234567 = vreinterpret_u8_s8(vmovn_s16(vacc01234567)); |
| 68 | #endif |
| 69 | |
| 70 | vst1_u8(output, vout01234567); output += 8; |
| 71 | } |
| 72 | if XNN_UNLIKELY(n != 0) { |
| 73 | { |
| 74 | const uint8x8_t va01234567 = vld1_u8(input_a); |
| 75 | const uint8x8_t vb01234567 = vld1_u8(input_b); |
| 76 | |
| 77 | const int16x8_t vxa01234567 = vreinterpretq_s16_u16(vsubl_u8(va01234567, va_zero_point)); |
| 78 | const int16x8_t vxb01234567 = vreinterpretq_s16_u16(vsubl_u8(vb01234567, vb_zero_point)); |
| 79 | |
| 80 | int32x4_t vacc0123 = vmull_s16(vget_low_s16(vxa01234567), vget_low_s16(vxb01234567)); |
| 81 | int32x4_t vacc4567 = vmull_s16(vget_high_s16(vxa01234567), vget_high_s16(vxb01234567)); |
| 82 | |
| 83 | float32x4_t vfpacc0123 = vcvtq_f32_s32(vacc0123); |
| 84 | float32x4_t vfpacc4567 = vcvtq_f32_s32(vacc4567); |
| 85 | |
| 86 | vfpacc0123 = vmulq_f32(vfpacc0123, vscale); |
| 87 | vfpacc4567 = vmulq_f32(vfpacc4567, vscale); |
| 88 | |
| 89 | vfpacc0123 = vmaxq_f32(vfpacc0123, voutput_min_less_zero_point); |
| 90 | vfpacc4567 = vmaxq_f32(vfpacc4567, voutput_min_less_zero_point); |
| 91 | |
| 92 | vfpacc0123 = vminq_f32(vfpacc0123, voutput_max_less_zero_point); |
| 93 | vfpacc4567 = vminq_f32(vfpacc4567, voutput_max_less_zero_point); |
| 94 | |
| 95 | vacc0123 = vreinterpretq_s32_f32(vaddq_f32(vfpacc0123, vmagic_bias)); |
| 96 | vacc4567 = vreinterpretq_s32_f32(vaddq_f32(vfpacc4567, vmagic_bias)); |
| 97 | |
| 98 | vacc0123 = vsubq_s32(vacc0123, vmagic_bias_less_zero_point); |
| 99 | vacc4567 = vsubq_s32(vacc4567, vmagic_bias_less_zero_point); |
| 100 | |
| 101 | #if XNN_ARCH_ARM64 |
| 102 | const int16x8_t vacc01234567 = vuzp1q_s16(vreinterpretq_s16_s32(vacc0123), vreinterpretq_s16_s32(vacc4567)); |
| 103 | uint8x8_t vout01234567 = vreinterpret_u8_s8(vmovn_s16(vacc01234567)); |
| 104 | #else |
| 105 | const int16x8_t vacc01234567 = vcombine_s16(vmovn_s32(vacc0123), vmovn_s32(vacc4567)); |
| 106 | uint8x8_t vout01234567 = vreinterpret_u8_s8(vmovn_s16(vacc01234567)); |
| 107 | #endif |
| 108 | |
| 109 | if (n & (4 * sizeof(uint8_t))) { |
| 110 | vst1_lane_u32(__builtin_assume_aligned(output, 1), vreinterpret_u32_u8(vout01234567), 0); output += 4; |
| 111 | vout01234567 = vext_u8(vout01234567, vout01234567, 4); |
| 112 | } |
| 113 | if (n & (2 * sizeof(uint8_t))) { |
| 114 | vst1_lane_u16(__builtin_assume_aligned(output, 1), vreinterpret_u16_u8(vout01234567), 0); output += 2; |
| 115 | vout01234567 = vext_u8(vout01234567, vout01234567, 2); |
| 116 | } |
| 117 | if (n & (1 * sizeof(uint8_t))) { |
| 118 | vst1_lane_u8(output, vout01234567, 0); |
| 119 | } |
| 120 | } |
| 121 | } |
| 122 | } |