XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1 | // Copyright (c) Facebook, Inc. and its affiliates. |
| 2 | // All rights reserved. |
| 3 | // |
| 4 | // Copyright 2019 Google LLC |
| 5 | // |
| 6 | // This source code is licensed under the BSD-style license found in the |
| 7 | // LICENSE file in the root directory of this source tree. |
| 8 | |
| 9 | #pragma once |
| 10 | |
| 11 | #include <stdbool.h> |
| 12 | #include <stddef.h> |
| 13 | #include <stdint.h> |
| 14 | |
| 15 | #include <pthreadpool.h> |
| 16 | |
| 17 | #ifdef __cplusplus |
| 18 | extern "C" { |
| 19 | #endif |
| 20 | |
Marat Dukhan | 5609a08 | 2019-10-07 10:56:58 -0700 | [diff] [blame] | 21 | /// The number of bytes XNNPACK may read beyond array bounds. |
| 22 | /// The caller must allocate at this this many extra bytes after the tensor data passed to XNNPACK. |
| 23 | /// |
| 24 | /// Note: XNNPACK reads, but never writes beyond array bounds. |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 25 | #define XNN_EXTRA_BYTES 16 |
| 26 | |
Marat Dukhan | ca2733c | 2019-11-15 23:21:17 -0800 | [diff] [blame] | 27 | /// Maximum number of dimensions in tensor shape. |
| 28 | #define XNN_MAX_TENSOR_DIMS 4 |
| 29 | |
Marat Dukhan | 5609a08 | 2019-10-07 10:56:58 -0700 | [diff] [blame] | 30 | /// The convolution operator represents a depthwise convolution, and use HWGo layout for filters. |
Marat Dukhan | dd69f0b | 2019-10-04 19:40:03 -0700 | [diff] [blame] | 31 | #define XNN_FLAG_DEPTHWISE_CONVOLUTION 0x00000001 |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 32 | |
Marat Dukhan | 5609a08 | 2019-10-07 10:56:58 -0700 | [diff] [blame] | 33 | /// The operator assumes NHWC layout for the input, regardless of the output layout. |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 34 | #define XNN_FLAG_INPUT_NHWC 0x00000002 |
| 35 | |
Marat Dukhan | 8440fde | 2019-10-24 12:46:13 -0700 | [diff] [blame] | 36 | /// Match "SAME" padding in TensorFlow. Exact padding values are computed dynamically depending on input size. |
| 37 | #define XNN_FLAG_TENSORFLOW_SAME_PADDING 0x00000004 |
| 38 | |
Marat Dukhan | 6972249 | 2019-11-11 19:55:50 -0800 | [diff] [blame] | 39 | /// Match behaviour of TensorFlow 1.x. |
| 40 | #define XNN_FLAG_TENSORFLOW_LEGACY_MODE 0x00000004 |
| 41 | |
| 42 | /// Align corners of input and output images in resize operations. |
| 43 | #define XNN_FLAG_ALIGN_CORNERS 0x00000008 |
| 44 | |
Marat Dukhan | 5609a08 | 2019-10-07 10:56:58 -0700 | [diff] [blame] | 45 | /// Status code for any XNNPACK function call. |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 46 | enum xnn_status { |
Marat Dukhan | 5609a08 | 2019-10-07 10:56:58 -0700 | [diff] [blame] | 47 | /// The call succeeded, and all output arguments now contain valid data. |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 48 | xnn_status_success = 0, |
| 49 | xnn_status_uninitialized = 1, |
| 50 | xnn_status_invalid_parameter = 2, |
| 51 | xnn_status_invalid_state = 3, |
| 52 | xnn_status_unsupported_parameter = 4, |
| 53 | xnn_status_unsupported_hardware = 5, |
| 54 | xnn_status_out_of_memory = 6, |
| 55 | }; |
| 56 | |
Marat Dukhan | 5609a08 | 2019-10-07 10:56:58 -0700 | [diff] [blame] | 57 | /// Initialize XNNPACK library. |
| 58 | /// |
| 59 | /// XNNPACK must be successfully initialized before use. |
| 60 | /// During initialization, XNNPACK populates internal structures depending on host processor. It can be time-consuming. |
| 61 | /// |
| 62 | /// @retval xnn_status_success - XNNPACK is succesfully initialized and ready to use. |
| 63 | /// @retval xnn_status_out_of_memory - initialization failed due to out-of-memory condition. |
| 64 | /// @retval xnn_status_unsupported_hardware - initialization failed because the host processor does not satisfy the |
| 65 | /// minimum hardware requirements for XNNPACK. E.g. this may happen on x86 |
| 66 | /// processors without SSE2 extension, or on 32-bit ARM processors without |
| 67 | /// the NEON SIMD extension. |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 68 | enum xnn_status xnn_initialize(void); |
| 69 | |
Marat Dukhan | 5609a08 | 2019-10-07 10:56:58 -0700 | [diff] [blame] | 70 | /// Deinitialize XNNPACK library. |
| 71 | /// |
| 72 | /// To avoid memory and resource leaks, users must call xnn_deinitialize once for each successful xnn_initialize call. |
| 73 | /// |
| 74 | /// @retval xnn_status_success - deinitialization call succeeded. |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 75 | enum xnn_status xnn_deinitialize(void); |
| 76 | |
| 77 | typedef struct xnn_operator* xnn_operator_t; |
| 78 | |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 79 | enum xnn_status xnn_run_operator( |
| 80 | xnn_operator_t op, |
| 81 | pthreadpool_t threadpool); |
| 82 | |
| 83 | enum xnn_status xnn_delete_operator( |
| 84 | xnn_operator_t op); |
| 85 | |
| 86 | #ifndef XNN_NO_F32_OPERATORS |
| 87 | |
| 88 | enum xnn_status xnn_create_add_nc_f32( |
| 89 | size_t channels, |
| 90 | size_t a_stride, |
| 91 | size_t b_stride, |
| 92 | size_t sum_stride, |
| 93 | float sum_min, |
| 94 | float sum_max, |
| 95 | uint32_t flags, |
| 96 | xnn_operator_t* add_op_out); |
| 97 | |
| 98 | enum xnn_status xnn_setup_add_nc_f32( |
| 99 | xnn_operator_t add_op, |
| 100 | size_t batch_size, |
| 101 | const float* a, |
| 102 | const float* b, |
| 103 | float* sum, |
| 104 | pthreadpool_t threadpool); |
| 105 | |
| 106 | enum xnn_status xnn_create_argmax_pooling2d_nhwc_f32( |
| 107 | uint32_t input_padding_top, |
| 108 | uint32_t input_padding_right, |
| 109 | uint32_t input_padding_bottom, |
| 110 | uint32_t input_padding_left, |
| 111 | uint32_t pooling_height, |
| 112 | uint32_t pooling_width, |
| 113 | size_t channels, |
| 114 | size_t input_pixel_stride, |
| 115 | size_t output_pixel_stride, |
| 116 | float output_min, |
| 117 | float output_max, |
| 118 | uint32_t flags, |
| 119 | xnn_operator_t* argmax_pooling_op_out); |
| 120 | |
| 121 | enum xnn_status xnn_setup_argmax_pooling2d_nhwc_f32( |
| 122 | xnn_operator_t argmax_pooling_op, |
| 123 | size_t batch_size, |
| 124 | size_t input_height, |
| 125 | size_t input_width, |
| 126 | const float* input, |
| 127 | float* output, |
| 128 | uint32_t* index, |
| 129 | pthreadpool_t threadpool); |
| 130 | |
| 131 | enum xnn_status xnn_create_average_pooling2d_nhwc_f32( |
| 132 | uint32_t input_padding_top, |
| 133 | uint32_t input_padding_right, |
| 134 | uint32_t input_padding_bottom, |
| 135 | uint32_t input_padding_left, |
| 136 | uint32_t pooling_height, |
| 137 | uint32_t pooling_width, |
| 138 | uint32_t stride_height, |
| 139 | uint32_t stride_width, |
| 140 | size_t channels, |
| 141 | size_t input_pixel_stride, |
| 142 | size_t output_pixel_stride, |
| 143 | float output_min, |
| 144 | float output_max, |
| 145 | uint32_t flags, |
| 146 | xnn_operator_t* average_pooling_op_out); |
| 147 | |
| 148 | enum xnn_status xnn_setup_average_pooling2d_nhwc_f32( |
| 149 | xnn_operator_t average_pooling_op, |
| 150 | size_t batch_size, |
| 151 | size_t input_height, |
| 152 | size_t input_width, |
| 153 | const float* input, |
| 154 | float* output, |
| 155 | pthreadpool_t threadpool); |
| 156 | |
| 157 | enum xnn_status xnn_create_clamp_nc_f32( |
| 158 | size_t channels, |
| 159 | size_t input_stride, |
| 160 | size_t output_stride, |
| 161 | float output_min, |
| 162 | float output_max, |
| 163 | uint32_t flags, |
| 164 | xnn_operator_t* clamp_op_out); |
| 165 | |
| 166 | enum xnn_status xnn_setup_clamp_nc_f32( |
| 167 | xnn_operator_t clamp_op, |
| 168 | size_t batch_size, |
| 169 | const float* input, |
| 170 | float* output, |
| 171 | pthreadpool_t threadpool); |
| 172 | |
| 173 | enum xnn_status xnn_create_convolution2d_nhwc_f32( |
| 174 | uint32_t input_padding_top, |
| 175 | uint32_t input_padding_right, |
| 176 | uint32_t input_padding_bottom, |
| 177 | uint32_t input_padding_left, |
| 178 | uint32_t kernel_height, |
| 179 | uint32_t kernel_width, |
| 180 | uint32_t subsampling_height, |
| 181 | uint32_t subsampling_width, |
| 182 | uint32_t dilation_height, |
| 183 | uint32_t dilation_width, |
| 184 | uint32_t groups, |
| 185 | size_t group_input_channels, |
| 186 | size_t group_output_channels, |
| 187 | size_t input_pixel_stride, |
| 188 | size_t output_pixel_stride, |
| 189 | const float* kernel, |
| 190 | const float* bias, |
| 191 | float output_min, |
| 192 | float output_max, |
| 193 | uint32_t flags, |
| 194 | xnn_operator_t* convolution_op_out); |
| 195 | |
| 196 | enum xnn_status xnn_setup_convolution2d_nhwc_f32( |
| 197 | xnn_operator_t convolution_op, |
| 198 | size_t batch_size, |
| 199 | size_t input_height, |
| 200 | size_t input_width, |
| 201 | const float* input, |
| 202 | float* output, |
| 203 | pthreadpool_t threadpool); |
| 204 | |
| 205 | enum xnn_status xnn_create_deconvolution2d_nhwc_f32( |
| 206 | uint32_t output_padding_top, |
| 207 | uint32_t output_padding_right, |
| 208 | uint32_t output_padding_bottom, |
| 209 | uint32_t output_padding_left, |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 210 | uint32_t kernel_height, |
| 211 | uint32_t kernel_width, |
| 212 | uint32_t stride_height, |
| 213 | uint32_t stride_width, |
| 214 | uint32_t dilation_height, |
| 215 | uint32_t dilation_width, |
| 216 | uint32_t groups, |
| 217 | size_t group_input_channels, |
| 218 | size_t group_output_channels, |
| 219 | size_t input_pixel_stride, |
| 220 | size_t output_pixel_stride, |
| 221 | const float* kernel, |
| 222 | const float* bias, |
| 223 | float output_min, |
| 224 | float output_max, |
| 225 | uint32_t flags, |
| 226 | xnn_operator_t* deconvolution_op_out); |
| 227 | |
| 228 | enum xnn_status xnn_setup_deconvolution2d_nhwc_f32( |
| 229 | xnn_operator_t deconvolution_op, |
| 230 | size_t batch_size, |
| 231 | size_t input_height, |
| 232 | size_t input_width, |
Marat Dukhan | 1898b91 | 2019-11-05 12:25:18 -0800 | [diff] [blame] | 233 | uint32_t adjustment_height, |
| 234 | uint32_t adjustment_width, |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 235 | const float* input, |
| 236 | float* output, |
| 237 | pthreadpool_t threadpool); |
| 238 | |
| 239 | enum xnn_status xnn_create_fully_connected_nc_f32( |
| 240 | size_t input_channels, |
| 241 | size_t output_channels, |
| 242 | size_t input_stride, |
| 243 | size_t output_stride, |
| 244 | const float* kernel, |
| 245 | const float* bias, |
| 246 | float output_min, |
| 247 | float output_max, |
| 248 | uint32_t flags, |
| 249 | xnn_operator_t* fully_connected_op_out); |
| 250 | |
| 251 | enum xnn_status xnn_setup_fully_connected_nc_f32( |
| 252 | xnn_operator_t fully_connected_op, |
| 253 | size_t batch_size, |
| 254 | const float* input, |
| 255 | float* output, |
| 256 | pthreadpool_t threadpool); |
| 257 | |
| 258 | enum xnn_status xnn_create_global_average_pooling_nwc_f32( |
| 259 | size_t channels, |
| 260 | size_t input_stride, |
| 261 | size_t output_stride, |
| 262 | float output_min, |
| 263 | float output_max, |
| 264 | uint32_t flags, |
| 265 | xnn_operator_t* global_average_pooling_op_out); |
| 266 | |
| 267 | enum xnn_status xnn_setup_global_average_pooling_nwc_f32( |
| 268 | xnn_operator_t global_average_pooling_op, |
| 269 | size_t batch_size, |
| 270 | size_t width, |
| 271 | const float* input, |
| 272 | float* output, |
| 273 | pthreadpool_t threadpool); |
| 274 | |
| 275 | enum xnn_status xnn_create_hardswish_nc_f32( |
| 276 | size_t channels, |
| 277 | size_t input_stride, |
| 278 | size_t output_stride, |
| 279 | uint32_t flags, |
| 280 | xnn_operator_t* hardswish_op_out); |
| 281 | |
| 282 | enum xnn_status xnn_setup_hardswish_nc_f32( |
| 283 | xnn_operator_t hardswish_op, |
| 284 | size_t batch_size, |
| 285 | const float* input, |
| 286 | float* output, |
| 287 | pthreadpool_t threadpool); |
| 288 | |
| 289 | enum xnn_status xnn_create_max_pooling2d_nhwc_f32( |
| 290 | uint32_t input_padding_top, |
| 291 | uint32_t input_padding_right, |
| 292 | uint32_t input_padding_bottom, |
| 293 | uint32_t input_padding_left, |
| 294 | uint32_t pooling_height, |
| 295 | uint32_t pooling_width, |
| 296 | uint32_t stride_height, |
| 297 | uint32_t stride_width, |
| 298 | uint32_t dilation_height, |
| 299 | uint32_t dilation_width, |
| 300 | size_t channels, |
| 301 | size_t input_pixel_stride, |
| 302 | size_t output_pixel_stride, |
| 303 | float output_min, |
| 304 | float output_max, |
| 305 | uint32_t flags, |
| 306 | xnn_operator_t* max_pooling_op_out); |
| 307 | |
| 308 | enum xnn_status xnn_setup_max_pooling2d_nhwc_f32( |
| 309 | xnn_operator_t max_pooling_op, |
| 310 | size_t batch_size, |
| 311 | size_t input_height, |
| 312 | size_t input_width, |
| 313 | const float* input, |
| 314 | float* output, |
| 315 | pthreadpool_t threadpool); |
| 316 | |
Marat Dukhan | ca2733c | 2019-11-15 23:21:17 -0800 | [diff] [blame] | 317 | enum xnn_status xnn_create_multiply_nd_f32( |
| 318 | float output_min, |
| 319 | float output_max, |
| 320 | uint32_t flags, |
| 321 | xnn_operator_t* multiply_op_out); |
| 322 | |
| 323 | enum xnn_status xnn_setup_multiply_nd_f32( |
| 324 | xnn_operator_t multiply_op, |
| 325 | size_t num_input1_dims, |
| 326 | const size_t* input1_shape, |
| 327 | size_t num_input2_dims, |
| 328 | const size_t* input2_shape, |
| 329 | const float* input1, |
| 330 | const float* input2, |
| 331 | float* output, |
| 332 | pthreadpool_t threadpool); |
| 333 | |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 334 | enum xnn_status xnn_create_prelu_nc_f32( |
| 335 | size_t channels, |
| 336 | size_t input_stride, |
| 337 | size_t output_stride, |
| 338 | const float* negative_slope, |
| 339 | float output_min, |
| 340 | float output_max, |
| 341 | uint32_t flags, |
| 342 | xnn_operator_t* prelu_op_out); |
| 343 | |
| 344 | enum xnn_status xnn_setup_prelu_nc_f32( |
| 345 | xnn_operator_t prelu_op, |
| 346 | size_t batch_size, |
| 347 | const float* input, |
| 348 | float* output, |
| 349 | pthreadpool_t threadpool); |
| 350 | |
Marat Dukhan | 6972249 | 2019-11-11 19:55:50 -0800 | [diff] [blame] | 351 | enum xnn_status xnn_create_resize_bilinear2d_nhwc_f32( |
| 352 | size_t channels, |
| 353 | size_t input_pixel_stride, |
| 354 | size_t output_pixel_stride, |
| 355 | uint32_t flags, |
| 356 | xnn_operator_t* resize_op_out); |
| 357 | |
| 358 | enum xnn_status xnn_setup_resize_bilinear2d_nhwc_f32( |
| 359 | xnn_operator_t resize_op, |
| 360 | size_t batch_size, |
| 361 | size_t input_height, |
| 362 | size_t input_width, |
| 363 | size_t output_height, |
| 364 | size_t output_width, |
| 365 | const float* input, |
| 366 | float* output, |
| 367 | pthreadpool_t threadpool); |
| 368 | |
Marat Dukhan | 346a9e5 | 2019-11-15 09:06:30 -0800 | [diff] [blame] | 369 | enum xnn_status xnn_create_sigmoid_nc_f32( |
| 370 | size_t channels, |
| 371 | size_t input_stride, |
| 372 | size_t output_stride, |
| 373 | uint32_t flags, |
| 374 | xnn_operator_t* sigmoid_op_out); |
| 375 | |
| 376 | enum xnn_status xnn_setup_sigmoid_nc_f32( |
| 377 | xnn_operator_t sigmoid_op, |
| 378 | size_t batch_size, |
| 379 | const float* input, |
| 380 | float* output, |
| 381 | pthreadpool_t threadpool); |
| 382 | |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame^] | 383 | #ifndef XNN_NO_NCHW_OPERATORS |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 384 | |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame^] | 385 | enum xnn_status xnn_create_convolution2d_nchw_f32( |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 386 | uint32_t input_padding_top, |
| 387 | uint32_t input_padding_right, |
| 388 | uint32_t input_padding_bottom, |
| 389 | uint32_t input_padding_left, |
| 390 | uint32_t kernel_height, |
| 391 | uint32_t kernel_width, |
| 392 | uint32_t subsampling_height, |
| 393 | uint32_t subsampling_width, |
| 394 | uint32_t dilation_height, |
| 395 | uint32_t dilation_width, |
| 396 | uint32_t groups, |
| 397 | size_t group_input_channels, |
| 398 | size_t group_output_channels, |
| 399 | const float* kernel, |
| 400 | const float* bias, |
| 401 | float output_min, |
| 402 | float output_max, |
| 403 | uint32_t flags, |
| 404 | xnn_operator_t* convolution_op_out); |
| 405 | |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame^] | 406 | enum xnn_status xnn_setup_convolution2d_nchw_f32( |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 407 | xnn_operator_t convolution_op, |
| 408 | size_t batch_size, |
| 409 | size_t input_batch_stride, |
| 410 | size_t output_batch_stride, |
| 411 | size_t input_height, |
| 412 | size_t input_width, |
| 413 | const float* input, |
| 414 | float* output, |
| 415 | pthreadpool_t threadpool); |
| 416 | |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame^] | 417 | enum xnn_status xnn_create_global_average_pooling_ncw_f32( |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 418 | size_t channels, |
| 419 | float output_min, |
| 420 | float output_max, |
| 421 | uint32_t flags, |
| 422 | xnn_operator_t* global_average_pooling_op_out); |
| 423 | |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame^] | 424 | enum xnn_status xnn_setup_global_average_pooling_ncw_f32( |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 425 | xnn_operator_t global_average_pooling_op, |
| 426 | size_t batch_size, |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 427 | size_t width, |
| 428 | const float* input, |
| 429 | float* output, |
| 430 | pthreadpool_t threadpool); |
| 431 | |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame^] | 432 | #endif // XNN_NO_NCHW_OPERATORS |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 433 | |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 434 | #endif // XNN_NO_F32_OPERATORS |
| 435 | |
| 436 | #ifndef XNN_NO_X32_OPERATORS |
| 437 | |
| 438 | enum xnn_status xnn_create_channel_pad_nc_x32( |
| 439 | size_t input_channels, |
| 440 | size_t pad_before_channels, |
| 441 | size_t pad_after_channels, |
| 442 | size_t input_stride, |
| 443 | size_t output_stride, |
| 444 | const void* pad_value, |
| 445 | uint32_t flags, |
| 446 | xnn_operator_t* channel_pad_op_out); |
| 447 | |
| 448 | enum xnn_status xnn_setup_channel_pad_nc_x32( |
| 449 | xnn_operator_t channel_pad_op, |
| 450 | size_t batch_size, |
| 451 | const void* input, |
| 452 | void* output, |
| 453 | pthreadpool_t threadpool); |
| 454 | |
| 455 | enum xnn_status xnn_create_channel_shuffle_nc_x32( |
| 456 | size_t groups, |
| 457 | size_t group_channels, |
| 458 | size_t input_stride, |
| 459 | size_t output_stride, |
| 460 | uint32_t flags, |
| 461 | xnn_operator_t* channel_shuffle_op_out); |
| 462 | |
| 463 | enum xnn_status xnn_setup_channel_shuffle_nc_x32( |
| 464 | xnn_operator_t channel_shuffle_op, |
| 465 | size_t batch_size, |
| 466 | const void* input, |
| 467 | void* output, |
| 468 | pthreadpool_t threadpool); |
| 469 | |
| 470 | enum xnn_status xnn_create_unpooling2d_nhwc_x32( |
| 471 | uint32_t input_padding_top, |
| 472 | uint32_t input_padding_right, |
| 473 | uint32_t input_padding_bottom, |
| 474 | uint32_t input_padding_left, |
| 475 | uint32_t pooling_height, |
| 476 | uint32_t pooling_width, |
| 477 | size_t channels, |
| 478 | size_t input_pixel_stride, |
| 479 | size_t output_pixel_stride, |
| 480 | uint32_t flags, |
| 481 | xnn_operator_t* unpooling_op_out); |
| 482 | |
| 483 | enum xnn_status xnn_setup_unpooling2d_nhwc_x32( |
| 484 | xnn_operator_t unpooling_op, |
| 485 | size_t batch_size, |
| 486 | size_t input_height, |
| 487 | size_t input_width, |
| 488 | const void* input, |
| 489 | const uint32_t* index, |
| 490 | void* output, |
| 491 | pthreadpool_t threadpool); |
| 492 | |
| 493 | #endif // XNN_NO_X32_OPERATORS |
| 494 | |
| 495 | #ifndef XNN_NO_Q8_OPERATORS |
| 496 | |
| 497 | enum xnn_status xnn_create_add_nc_q8( |
| 498 | size_t channels, |
| 499 | size_t a_stride, |
| 500 | size_t b_stride, |
| 501 | size_t sum_stride, |
| 502 | uint8_t a_zero_point, |
| 503 | float a_scale, |
| 504 | uint8_t b_zero_point, |
| 505 | float b_scale, |
| 506 | uint8_t sum_zero_point, |
| 507 | float sum_scale, |
| 508 | uint8_t sum_min, |
| 509 | uint8_t sum_max, |
| 510 | uint32_t flags, |
| 511 | xnn_operator_t* add_op_out); |
| 512 | |
| 513 | enum xnn_status xnn_setup_add_nc_q8( |
| 514 | xnn_operator_t add_op, |
| 515 | size_t batch_size, |
| 516 | const uint8_t* a, |
| 517 | const uint8_t* b, |
| 518 | uint8_t* sum, |
| 519 | pthreadpool_t threadpool); |
| 520 | |
| 521 | enum xnn_status xnn_create_average_pooling2d_nhwc_q8( |
| 522 | uint32_t input_padding_top, |
| 523 | uint32_t input_padding_right, |
| 524 | uint32_t input_padding_bottom, |
| 525 | uint32_t input_padding_left, |
| 526 | uint32_t pooling_height, |
| 527 | uint32_t pooling_width, |
| 528 | uint32_t stride_height, |
| 529 | uint32_t stride_width, |
| 530 | size_t channels, |
| 531 | size_t input_pixel_stride, |
| 532 | size_t output_pixel_stride, |
| 533 | uint8_t input_zero_point, |
| 534 | float input_scale, |
| 535 | uint8_t output_zero_point, |
| 536 | float output_scale, |
| 537 | uint8_t output_min, |
| 538 | uint8_t output_max, |
| 539 | uint32_t flags, |
| 540 | xnn_operator_t* average_pooling_op_out); |
| 541 | |
| 542 | enum xnn_status xnn_setup_average_pooling2d_nhwc_q8( |
| 543 | xnn_operator_t average_pooling_op, |
| 544 | size_t batch_size, |
| 545 | size_t input_height, |
| 546 | size_t input_width, |
| 547 | const uint8_t* input, |
| 548 | uint8_t* output, |
| 549 | pthreadpool_t threadpool); |
| 550 | |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 551 | enum xnn_status xnn_create_convolution2d_nhwc_q8( |
| 552 | uint32_t input_padding_top, |
| 553 | uint32_t input_padding_right, |
| 554 | uint32_t input_padding_bottom, |
| 555 | uint32_t input_padding_left, |
| 556 | uint32_t kernel_height, |
| 557 | uint32_t kernel_width, |
| 558 | uint32_t subsampling_height, |
| 559 | uint32_t subsampling_width, |
| 560 | uint32_t dilation_height, |
| 561 | uint32_t dilation_width, |
| 562 | uint32_t groups, |
| 563 | size_t group_input_channels, |
| 564 | size_t group_output_channels, |
| 565 | size_t input_pixel_stride, |
| 566 | size_t output_pixel_stride, |
| 567 | uint8_t input_zero_point, |
| 568 | float input_scale, |
| 569 | uint8_t kernel_zero_point, |
| 570 | float kernel_scale, |
| 571 | const uint8_t* kernel, |
| 572 | const int32_t* bias, |
| 573 | uint8_t output_zero_point, |
| 574 | float output_scale, |
| 575 | uint8_t output_min, |
| 576 | uint8_t output_max, |
| 577 | uint32_t flags, |
| 578 | xnn_operator_t* convolution_op_out); |
| 579 | |
| 580 | enum xnn_status xnn_setup_convolution2d_nhwc_q8( |
| 581 | xnn_operator_t convolution_op, |
| 582 | size_t batch_size, |
| 583 | size_t input_height, |
| 584 | size_t input_width, |
| 585 | const uint8_t* input, |
| 586 | uint8_t* output, |
| 587 | pthreadpool_t threadpool); |
| 588 | |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 589 | enum xnn_status xnn_create_deconvolution2d_nhwc_q8( |
| 590 | uint32_t output_padding_top, |
| 591 | uint32_t output_padding_right, |
| 592 | uint32_t output_padding_bottom, |
| 593 | uint32_t output_padding_left, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 594 | uint32_t kernel_height, |
| 595 | uint32_t kernel_width, |
| 596 | uint32_t stride_height, |
| 597 | uint32_t stride_width, |
| 598 | uint32_t dilation_height, |
| 599 | uint32_t dilation_width, |
| 600 | uint32_t groups, |
| 601 | size_t group_input_channels, |
| 602 | size_t group_output_channels, |
| 603 | size_t input_pixel_stride, |
| 604 | size_t output_pixel_stride, |
| 605 | uint8_t input_zero_point, |
| 606 | float input_scale, |
| 607 | uint8_t kernel_zero_point, |
| 608 | float kernel_scale, |
| 609 | const uint8_t* kernel, |
| 610 | const int32_t* bias, |
| 611 | uint8_t output_zero_point, |
| 612 | float output_scale, |
| 613 | uint8_t output_min, |
| 614 | uint8_t output_max, |
| 615 | uint32_t flags, |
| 616 | xnn_operator_t* deconvolution_op_out); |
| 617 | |
| 618 | enum xnn_status xnn_setup_deconvolution2d_nhwc_q8( |
| 619 | xnn_operator_t deconvolution_op, |
| 620 | size_t batch_size, |
| 621 | size_t input_height, |
| 622 | size_t input_width, |
Marat Dukhan | 1898b91 | 2019-11-05 12:25:18 -0800 | [diff] [blame] | 623 | uint32_t adjustment_height, |
| 624 | uint32_t adjustment_width, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 625 | const uint8_t* input, |
| 626 | uint8_t* output, |
| 627 | pthreadpool_t threadpool); |
| 628 | |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 629 | enum xnn_status xnn_create_fully_connected_nc_q8( |
| 630 | size_t input_channels, |
| 631 | size_t output_channels, |
| 632 | size_t input_stride, |
| 633 | size_t output_stride, |
| 634 | uint8_t input_zero_point, |
| 635 | float input_scale, |
| 636 | uint8_t kernel_zero_point, |
| 637 | float kernel_scale, |
| 638 | const uint8_t* kernel, |
| 639 | const int32_t* bias, |
| 640 | uint8_t output_zero_point, |
| 641 | float output_scale, |
| 642 | uint8_t output_min, |
| 643 | uint8_t output_max, |
| 644 | uint32_t flags, |
| 645 | xnn_operator_t* fully_connected_op_out); |
| 646 | |
| 647 | enum xnn_status xnn_setup_fully_connected_nc_q8( |
| 648 | xnn_operator_t fully_connected_op, |
| 649 | size_t batch_size, |
| 650 | const uint8_t* input, |
| 651 | uint8_t* output, |
| 652 | pthreadpool_t threadpool); |
| 653 | |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 654 | enum xnn_status xnn_create_global_average_pooling_nwc_q8( |
| 655 | size_t channels, |
| 656 | size_t input_stride, |
| 657 | size_t output_stride, |
| 658 | uint8_t input_zero_point, |
| 659 | float input_scale, |
| 660 | uint8_t output_zero_point, |
| 661 | float output_scale, |
| 662 | uint8_t output_min, |
| 663 | uint8_t output_max, |
| 664 | uint32_t flags, |
| 665 | xnn_operator_t* global_average_pooling_op_out); |
| 666 | |
| 667 | enum xnn_status xnn_setup_global_average_pooling_nwc_q8( |
| 668 | xnn_operator_t global_average_pooling_op, |
| 669 | size_t batch_size, |
| 670 | size_t width, |
| 671 | const uint8_t* input, |
| 672 | uint8_t* output, |
| 673 | pthreadpool_t threadpool); |
| 674 | |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 675 | enum xnn_status xnn_create_leaky_relu_nc_q8( |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 676 | size_t channels, |
| 677 | size_t input_stride, |
| 678 | size_t output_stride, |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 679 | float negative_slope, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 680 | uint8_t input_zero_point, |
| 681 | float input_scale, |
| 682 | uint8_t output_zero_point, |
| 683 | float output_scale, |
| 684 | uint8_t output_min, |
| 685 | uint8_t output_max, |
| 686 | uint32_t flags, |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 687 | xnn_operator_t* leaky_relu_op_out); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 688 | |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 689 | enum xnn_status xnn_setup_leaky_relu_nc_q8( |
| 690 | xnn_operator_t leaky_relu_op, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 691 | size_t batch_size, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 692 | const uint8_t* input, |
| 693 | uint8_t* output, |
| 694 | pthreadpool_t threadpool); |
| 695 | |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 696 | enum xnn_status xnn_create_sigmoid_nc_q8( |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 697 | size_t channels, |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 698 | size_t input_stride, |
| 699 | size_t output_stride, |
| 700 | uint8_t input_zero_point, |
| 701 | float input_scale, |
| 702 | uint8_t output_zero_point, |
| 703 | float output_scale, |
| 704 | uint8_t output_min, |
| 705 | uint8_t output_max, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 706 | uint32_t flags, |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 707 | xnn_operator_t* sigmoid_op_out); |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 708 | |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 709 | enum xnn_status xnn_setup_sigmoid_nc_q8( |
| 710 | xnn_operator_t sigmoid_op, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 711 | size_t batch_size, |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 712 | const uint8_t* input, |
| 713 | uint8_t* output, |
| 714 | pthreadpool_t threadpool); |
| 715 | |
| 716 | enum xnn_status xnn_create_softargmax_nc_q8( |
| 717 | size_t channels, |
| 718 | size_t input_stride, |
| 719 | size_t output_stride, |
| 720 | float input_scale, |
| 721 | uint8_t output_zero_point, |
| 722 | float output_scale, |
| 723 | uint32_t flags, |
| 724 | xnn_operator_t* softargmax_op_out); |
| 725 | |
| 726 | enum xnn_status xnn_setup_softargmax_nc_q8( |
| 727 | xnn_operator_t softargmax_op, |
| 728 | size_t batch_size, |
| 729 | const uint8_t* input, |
| 730 | uint8_t* output, |
| 731 | pthreadpool_t threadpool); |
| 732 | |
| 733 | #endif // XNN_NO_Q8_OPERATORS |
| 734 | |
| 735 | #ifndef XNN_NO_U8_OPERATORS |
| 736 | |
| 737 | enum xnn_status xnn_create_clamp_nc_u8( |
| 738 | size_t channels, |
| 739 | size_t input_stride, |
| 740 | size_t output_stride, |
| 741 | uint8_t output_min, |
| 742 | uint8_t output_max, |
| 743 | uint32_t flags, |
| 744 | xnn_operator_t* clamp_op_out); |
| 745 | |
| 746 | enum xnn_status xnn_setup_clamp_nc_u8( |
| 747 | xnn_operator_t clamp_op, |
| 748 | size_t batch_size, |
| 749 | const uint8_t* input, |
| 750 | uint8_t* output, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 751 | pthreadpool_t threadpool); |
| 752 | |
| 753 | enum xnn_status xnn_create_max_pooling2d_nhwc_u8( |
| 754 | uint32_t input_padding_top, |
| 755 | uint32_t input_padding_right, |
| 756 | uint32_t input_padding_bottom, |
| 757 | uint32_t input_padding_left, |
| 758 | uint32_t pooling_height, |
| 759 | uint32_t pooling_width, |
| 760 | uint32_t stride_height, |
| 761 | uint32_t stride_width, |
| 762 | uint32_t dilation_height, |
| 763 | uint32_t dilation_width, |
| 764 | size_t channels, |
| 765 | size_t input_pixel_stride, |
| 766 | size_t output_pixel_stride, |
| 767 | uint8_t output_min, |
| 768 | uint8_t output_max, |
| 769 | uint32_t flags, |
| 770 | xnn_operator_t* max_pooling_op_out); |
| 771 | |
| 772 | enum xnn_status xnn_setup_max_pooling2d_nhwc_u8( |
| 773 | xnn_operator_t max_pooling_op, |
| 774 | size_t batch_size, |
| 775 | size_t input_height, |
| 776 | size_t input_width, |
| 777 | const uint8_t* input, |
| 778 | uint8_t* output, |
| 779 | pthreadpool_t threadpool); |
| 780 | |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 781 | #endif // XNN_NO_U8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 782 | |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 783 | #ifndef XNN_NO_X8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 784 | |
| 785 | enum xnn_status xnn_create_channel_shuffle_nc_x8( |
| 786 | size_t groups, |
| 787 | size_t group_channels, |
| 788 | size_t input_stride, |
| 789 | size_t output_stride, |
| 790 | uint32_t flags, |
| 791 | xnn_operator_t* channel_shuffle_op_out); |
| 792 | |
| 793 | enum xnn_status xnn_setup_channel_shuffle_nc_x8( |
| 794 | xnn_operator_t channel_shuffle_op, |
| 795 | size_t batch_size, |
| 796 | const void* input, |
| 797 | void* output, |
| 798 | pthreadpool_t threadpool); |
| 799 | |
Marat Dukhan | d620972 | 2019-10-07 12:54:25 -0700 | [diff] [blame] | 800 | #endif // XNN_NO_X8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 801 | |
| 802 | #ifdef __cplusplus |
| 803 | } // extern "C" |
| 804 | #endif |