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XNNPACK Teamb455b122019-09-27 18:10:33 -07001// Copyright 2019 Google LLC
2//
3// This source code is licensed under the BSD-style license found in the
4// LICENSE file in the root directory of this source tree.
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08005//
6// Auto-generated file. Do not edit!
7// Specification: test/f32-prelu.yaml
8// Generator: tools/generate-prelu-test.py
9
XNNPACK Teamb455b122019-09-27 18:10:33 -070010
XNNPACK Teamb455b122019-09-27 18:10:33 -070011#include <gtest/gtest.h>
12
Marat Dukhan1dadbf72019-10-01 10:46:20 -070013#include <xnnpack/common.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070014#include <xnnpack/isa-checks.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070015
Marat Dukhan1dadbf72019-10-01 10:46:20 -070016#include <xnnpack/prelu.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -070017#include "prelu-microkernel-tester.h"
18
19
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080020#if XNN_ARCH_ARM || XNN_ARCH_ARM64
21 TEST(F32_PRELU__NEON_2X4, channels_eq_4) {
22 TEST_REQUIRES_ARM_NEON;
XNNPACK Teamb455b122019-09-27 18:10:33 -070023 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080024 .rows(2)
25 .channels(4)
26 .Test(xnn_f32_prelu_ukernel__neon_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070027 }
28
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080029 TEST(F32_PRELU__NEON_2X4, channels_div_4) {
30 TEST_REQUIRES_ARM_NEON;
31 for (size_t channels = 8; channels < 40; channels += 4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070032 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080033 .rows(2)
34 .channels(channels)
35 .Test(xnn_f32_prelu_ukernel__neon_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070036 }
37 }
38
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080039 TEST(F32_PRELU__NEON_2X4, channels_lt_4) {
40 TEST_REQUIRES_ARM_NEON;
41 for (size_t channels = 1; channels < 4; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070042 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080043 .rows(2)
44 .channels(channels)
45 .Test(xnn_f32_prelu_ukernel__neon_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070046 }
47 }
48
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080049 TEST(F32_PRELU__NEON_2X4, channels_gt_4) {
50 TEST_REQUIRES_ARM_NEON;
51 for (size_t channels = 5; channels < 8; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070052 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080053 .rows(2)
54 .channels(channels)
55 .Test(xnn_f32_prelu_ukernel__neon_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070056 }
57 }
58
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080059 TEST(F32_PRELU__NEON_2X4, rows_lt_2) {
60 TEST_REQUIRES_ARM_NEON;
61 for (size_t rows = 1; rows < 2; rows++) {
62 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070063 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080064 .rows(rows)
65 .channels(channels)
66 .Test(xnn_f32_prelu_ukernel__neon_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070067 }
68 }
69 }
70
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080071 TEST(F32_PRELU__NEON_2X4, rows_div_2) {
72 TEST_REQUIRES_ARM_NEON;
73 for (size_t rows = 4; rows <= 8; rows += 2) {
74 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070075 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080076 .rows(rows)
77 .channels(channels)
78 .Test(xnn_f32_prelu_ukernel__neon_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070079 }
80 }
81 }
82
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080083 TEST(F32_PRELU__NEON_2X4, rows_gt_2) {
84 TEST_REQUIRES_ARM_NEON;
85 for (size_t rows = 3; rows < 4; rows++) {
86 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070087 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080088 .rows(rows)
89 .channels(channels)
90 .Test(xnn_f32_prelu_ukernel__neon_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -070091 }
92 }
93 }
94
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080095 TEST(F32_PRELU__NEON_2X4, input_stride) {
96 TEST_REQUIRES_ARM_NEON;
97 for (size_t rows = 1; rows <= 6; rows += 1) {
98 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -070099 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800100 .rows(rows)
101 .channels(channels)
102 .input_stride(23)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700103 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800104 .Test(xnn_f32_prelu_ukernel__neon_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700105 }
106 }
107 }
108
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800109 TEST(F32_PRELU__NEON_2X4, output_stride) {
110 TEST_REQUIRES_ARM_NEON;
111 for (size_t rows = 1; rows <= 6; rows += 1) {
112 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700113 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800114 .rows(rows)
115 .channels(channels)
116 .output_stride(23)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700117 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800118 .Test(xnn_f32_prelu_ukernel__neon_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700119 }
120 }
121 }
122
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800123 TEST(F32_PRELU__NEON_2X4, inplace) {
124 TEST_REQUIRES_ARM_NEON;
125 for (size_t rows = 1; rows <= 6; rows += 1) {
126 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700127 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800128 .rows(rows)
129 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700130 .inplace(true)
131 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800132 .Test(xnn_f32_prelu_ukernel__neon_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700133 }
134 }
135 }
136
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800137 TEST(F32_PRELU__NEON_2X4, qmin) {
138 TEST_REQUIRES_ARM_NEON;
139 for (size_t rows = 1; rows <= 6; rows += 1) {
140 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700141 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800142 .rows(rows)
143 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700144 .qmin(128)
145 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800146 .Test(xnn_f32_prelu_ukernel__neon_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700147 }
148 }
149 }
150
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800151 TEST(F32_PRELU__NEON_2X4, qmax) {
152 TEST_REQUIRES_ARM_NEON;
153 for (size_t rows = 1; rows <= 6; rows += 1) {
154 for (size_t channels = 1; channels <= 20; channels += 3) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700155 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800156 .rows(rows)
157 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700158 .qmax(128)
159 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800160 .Test(xnn_f32_prelu_ukernel__neon_2x4);
161 }
162 }
163 }
164#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
165
166
167#if XNN_ARCH_ARM || XNN_ARCH_ARM64
168 TEST(F32_PRELU__NEON_2X8, channels_eq_8) {
169 TEST_REQUIRES_ARM_NEON;
170 PReLUMicrokernelTester()
171 .rows(2)
172 .channels(8)
173 .Test(xnn_f32_prelu_ukernel__neon_2x8);
174 }
175
176 TEST(F32_PRELU__NEON_2X8, channels_div_8) {
177 TEST_REQUIRES_ARM_NEON;
178 for (size_t channels = 16; channels < 80; channels += 8) {
179 PReLUMicrokernelTester()
180 .rows(2)
181 .channels(channels)
182 .Test(xnn_f32_prelu_ukernel__neon_2x8);
183 }
184 }
185
186 TEST(F32_PRELU__NEON_2X8, channels_lt_8) {
187 TEST_REQUIRES_ARM_NEON;
188 for (size_t channels = 1; channels < 8; channels++) {
189 PReLUMicrokernelTester()
190 .rows(2)
191 .channels(channels)
192 .Test(xnn_f32_prelu_ukernel__neon_2x8);
193 }
194 }
195
196 TEST(F32_PRELU__NEON_2X8, channels_gt_8) {
197 TEST_REQUIRES_ARM_NEON;
198 for (size_t channels = 9; channels < 16; channels++) {
199 PReLUMicrokernelTester()
200 .rows(2)
201 .channels(channels)
202 .Test(xnn_f32_prelu_ukernel__neon_2x8);
203 }
204 }
205
206 TEST(F32_PRELU__NEON_2X8, rows_lt_2) {
207 TEST_REQUIRES_ARM_NEON;
208 for (size_t rows = 1; rows < 2; rows++) {
209 for (size_t channels = 1; channels <= 40; channels += 7) {
210 PReLUMicrokernelTester()
211 .rows(rows)
212 .channels(channels)
213 .Test(xnn_f32_prelu_ukernel__neon_2x8);
214 }
215 }
216 }
217
218 TEST(F32_PRELU__NEON_2X8, rows_div_2) {
219 TEST_REQUIRES_ARM_NEON;
220 for (size_t rows = 4; rows <= 8; rows += 2) {
221 for (size_t channels = 1; channels <= 40; channels += 7) {
222 PReLUMicrokernelTester()
223 .rows(rows)
224 .channels(channels)
225 .Test(xnn_f32_prelu_ukernel__neon_2x8);
226 }
227 }
228 }
229
230 TEST(F32_PRELU__NEON_2X8, rows_gt_2) {
231 TEST_REQUIRES_ARM_NEON;
232 for (size_t rows = 3; rows < 4; rows++) {
233 for (size_t channels = 1; channels <= 40; channels += 7) {
234 PReLUMicrokernelTester()
235 .rows(rows)
236 .channels(channels)
237 .Test(xnn_f32_prelu_ukernel__neon_2x8);
238 }
239 }
240 }
241
242 TEST(F32_PRELU__NEON_2X8, input_stride) {
243 TEST_REQUIRES_ARM_NEON;
244 for (size_t rows = 1; rows <= 6; rows += 1) {
245 for (size_t channels = 1; channels <= 40; channels += 7) {
246 PReLUMicrokernelTester()
247 .rows(rows)
248 .channels(channels)
249 .input_stride(43)
250 .iterations(1)
251 .Test(xnn_f32_prelu_ukernel__neon_2x8);
252 }
253 }
254 }
255
256 TEST(F32_PRELU__NEON_2X8, output_stride) {
257 TEST_REQUIRES_ARM_NEON;
258 for (size_t rows = 1; rows <= 6; rows += 1) {
259 for (size_t channels = 1; channels <= 40; channels += 7) {
260 PReLUMicrokernelTester()
261 .rows(rows)
262 .channels(channels)
263 .output_stride(43)
264 .iterations(1)
265 .Test(xnn_f32_prelu_ukernel__neon_2x8);
266 }
267 }
268 }
269
270 TEST(F32_PRELU__NEON_2X8, inplace) {
271 TEST_REQUIRES_ARM_NEON;
272 for (size_t rows = 1; rows <= 6; rows += 1) {
273 for (size_t channels = 1; channels <= 40; channels += 7) {
274 PReLUMicrokernelTester()
275 .rows(rows)
276 .channels(channels)
277 .inplace(true)
278 .iterations(1)
279 .Test(xnn_f32_prelu_ukernel__neon_2x8);
280 }
281 }
282 }
283
284 TEST(F32_PRELU__NEON_2X8, qmin) {
285 TEST_REQUIRES_ARM_NEON;
286 for (size_t rows = 1; rows <= 6; rows += 1) {
287 for (size_t channels = 1; channels <= 40; channels += 7) {
288 PReLUMicrokernelTester()
289 .rows(rows)
290 .channels(channels)
291 .qmin(128)
292 .iterations(1)
293 .Test(xnn_f32_prelu_ukernel__neon_2x8);
294 }
295 }
296 }
297
298 TEST(F32_PRELU__NEON_2X8, qmax) {
299 TEST_REQUIRES_ARM_NEON;
300 for (size_t rows = 1; rows <= 6; rows += 1) {
301 for (size_t channels = 1; channels <= 40; channels += 7) {
302 PReLUMicrokernelTester()
303 .rows(rows)
304 .channels(channels)
305 .qmax(128)
306 .iterations(1)
307 .Test(xnn_f32_prelu_ukernel__neon_2x8);
308 }
309 }
310 }
311#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
312
313
314#if XNN_ARCH_X86 || XNN_ARCH_X86_64
315 TEST(F32_PRELU__SSE2_2X4, channels_eq_4) {
316 TEST_REQUIRES_X86_SSE2;
317 PReLUMicrokernelTester()
318 .rows(2)
319 .channels(4)
320 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
321 }
322
323 TEST(F32_PRELU__SSE2_2X4, channels_div_4) {
324 TEST_REQUIRES_X86_SSE2;
325 for (size_t channels = 8; channels < 40; channels += 4) {
326 PReLUMicrokernelTester()
327 .rows(2)
328 .channels(channels)
329 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
330 }
331 }
332
333 TEST(F32_PRELU__SSE2_2X4, channels_lt_4) {
334 TEST_REQUIRES_X86_SSE2;
335 for (size_t channels = 1; channels < 4; channels++) {
336 PReLUMicrokernelTester()
337 .rows(2)
338 .channels(channels)
339 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
340 }
341 }
342
343 TEST(F32_PRELU__SSE2_2X4, channels_gt_4) {
344 TEST_REQUIRES_X86_SSE2;
345 for (size_t channels = 5; channels < 8; channels++) {
346 PReLUMicrokernelTester()
347 .rows(2)
348 .channels(channels)
349 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
350 }
351 }
352
353 TEST(F32_PRELU__SSE2_2X4, rows_lt_2) {
354 TEST_REQUIRES_X86_SSE2;
355 for (size_t rows = 1; rows < 2; rows++) {
356 for (size_t channels = 1; channels <= 20; channels += 3) {
357 PReLUMicrokernelTester()
358 .rows(rows)
359 .channels(channels)
360 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
361 }
362 }
363 }
364
365 TEST(F32_PRELU__SSE2_2X4, rows_div_2) {
366 TEST_REQUIRES_X86_SSE2;
367 for (size_t rows = 4; rows <= 8; rows += 2) {
368 for (size_t channels = 1; channels <= 20; channels += 3) {
369 PReLUMicrokernelTester()
370 .rows(rows)
371 .channels(channels)
372 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
373 }
374 }
375 }
376
377 TEST(F32_PRELU__SSE2_2X4, rows_gt_2) {
378 TEST_REQUIRES_X86_SSE2;
379 for (size_t rows = 3; rows < 4; rows++) {
380 for (size_t channels = 1; channels <= 20; channels += 3) {
381 PReLUMicrokernelTester()
382 .rows(rows)
383 .channels(channels)
384 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
385 }
386 }
387 }
388
389 TEST(F32_PRELU__SSE2_2X4, input_stride) {
390 TEST_REQUIRES_X86_SSE2;
391 for (size_t rows = 1; rows <= 6; rows += 1) {
392 for (size_t channels = 1; channels <= 20; channels += 3) {
393 PReLUMicrokernelTester()
394 .rows(rows)
395 .channels(channels)
396 .input_stride(23)
397 .iterations(1)
398 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
399 }
400 }
401 }
402
403 TEST(F32_PRELU__SSE2_2X4, output_stride) {
404 TEST_REQUIRES_X86_SSE2;
405 for (size_t rows = 1; rows <= 6; rows += 1) {
406 for (size_t channels = 1; channels <= 20; channels += 3) {
407 PReLUMicrokernelTester()
408 .rows(rows)
409 .channels(channels)
410 .output_stride(23)
411 .iterations(1)
412 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
413 }
414 }
415 }
416
417 TEST(F32_PRELU__SSE2_2X4, inplace) {
418 TEST_REQUIRES_X86_SSE2;
419 for (size_t rows = 1; rows <= 6; rows += 1) {
420 for (size_t channels = 1; channels <= 20; channels += 3) {
421 PReLUMicrokernelTester()
422 .rows(rows)
423 .channels(channels)
424 .inplace(true)
425 .iterations(1)
426 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
427 }
428 }
429 }
430
431 TEST(F32_PRELU__SSE2_2X4, qmin) {
432 TEST_REQUIRES_X86_SSE2;
433 for (size_t rows = 1; rows <= 6; rows += 1) {
434 for (size_t channels = 1; channels <= 20; channels += 3) {
435 PReLUMicrokernelTester()
436 .rows(rows)
437 .channels(channels)
438 .qmin(128)
439 .iterations(1)
440 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
441 }
442 }
443 }
444
445 TEST(F32_PRELU__SSE2_2X4, qmax) {
446 TEST_REQUIRES_X86_SSE2;
447 for (size_t rows = 1; rows <= 6; rows += 1) {
448 for (size_t channels = 1; channels <= 20; channels += 3) {
449 PReLUMicrokernelTester()
450 .rows(rows)
451 .channels(channels)
452 .qmax(128)
453 .iterations(1)
454 .Test(xnn_f32_prelu_ukernel__sse2_2x4);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700455 }
456 }
457 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700458#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700459
460
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800461#if XNN_ARCH_X86 || XNN_ARCH_X86_64
462 TEST(F32_PRELU__SSE2_2X8, channels_eq_8) {
463 TEST_REQUIRES_X86_SSE2;
XNNPACK Teamb455b122019-09-27 18:10:33 -0700464 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800465 .rows(2)
466 .channels(8)
467 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700468 }
469
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800470 TEST(F32_PRELU__SSE2_2X8, channels_div_8) {
471 TEST_REQUIRES_X86_SSE2;
472 for (size_t channels = 16; channels < 80; channels += 8) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700473 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800474 .rows(2)
475 .channels(channels)
476 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700477 }
478 }
479
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800480 TEST(F32_PRELU__SSE2_2X8, channels_lt_8) {
481 TEST_REQUIRES_X86_SSE2;
482 for (size_t channels = 1; channels < 8; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700483 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800484 .rows(2)
485 .channels(channels)
486 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700487 }
488 }
489
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800490 TEST(F32_PRELU__SSE2_2X8, channels_gt_8) {
491 TEST_REQUIRES_X86_SSE2;
492 for (size_t channels = 9; channels < 16; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700493 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800494 .rows(2)
495 .channels(channels)
496 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700497 }
498 }
499
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800500 TEST(F32_PRELU__SSE2_2X8, rows_lt_2) {
501 TEST_REQUIRES_X86_SSE2;
502 for (size_t rows = 1; rows < 2; rows++) {
503 for (size_t channels = 1; channels <= 40; channels += 7) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700504 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800505 .rows(rows)
506 .channels(channels)
507 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700508 }
509 }
510 }
511
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800512 TEST(F32_PRELU__SSE2_2X8, rows_div_2) {
513 TEST_REQUIRES_X86_SSE2;
514 for (size_t rows = 4; rows <= 8; rows += 2) {
515 for (size_t channels = 1; channels <= 40; channels += 7) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700516 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800517 .rows(rows)
518 .channels(channels)
519 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700520 }
521 }
522 }
523
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800524 TEST(F32_PRELU__SSE2_2X8, rows_gt_2) {
525 TEST_REQUIRES_X86_SSE2;
526 for (size_t rows = 3; rows < 4; rows++) {
527 for (size_t channels = 1; channels <= 40; channels += 7) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700528 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800529 .rows(rows)
530 .channels(channels)
531 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700532 }
533 }
534 }
535
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800536 TEST(F32_PRELU__SSE2_2X8, input_stride) {
537 TEST_REQUIRES_X86_SSE2;
538 for (size_t rows = 1; rows <= 6; rows += 1) {
539 for (size_t channels = 1; channels <= 40; channels += 7) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700540 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800541 .rows(rows)
542 .channels(channels)
543 .input_stride(43)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700544 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800545 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700546 }
547 }
548 }
549
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800550 TEST(F32_PRELU__SSE2_2X8, output_stride) {
551 TEST_REQUIRES_X86_SSE2;
552 for (size_t rows = 1; rows <= 6; rows += 1) {
553 for (size_t channels = 1; channels <= 40; channels += 7) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700554 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800555 .rows(rows)
556 .channels(channels)
557 .output_stride(43)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700558 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800559 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700560 }
561 }
562 }
563
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800564 TEST(F32_PRELU__SSE2_2X8, inplace) {
565 TEST_REQUIRES_X86_SSE2;
566 for (size_t rows = 1; rows <= 6; rows += 1) {
567 for (size_t channels = 1; channels <= 40; channels += 7) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700568 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800569 .rows(rows)
570 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700571 .inplace(true)
572 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800573 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700574 }
575 }
576 }
577
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800578 TEST(F32_PRELU__SSE2_2X8, qmin) {
579 TEST_REQUIRES_X86_SSE2;
580 for (size_t rows = 1; rows <= 6; rows += 1) {
581 for (size_t channels = 1; channels <= 40; channels += 7) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700582 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800583 .rows(rows)
584 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700585 .qmin(128)
586 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800587 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700588 }
589 }
590 }
591
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800592 TEST(F32_PRELU__SSE2_2X8, qmax) {
593 TEST_REQUIRES_X86_SSE2;
594 for (size_t rows = 1; rows <= 6; rows += 1) {
595 for (size_t channels = 1; channels <= 40; channels += 7) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700596 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800597 .rows(rows)
598 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700599 .qmax(128)
600 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800601 .Test(xnn_f32_prelu_ukernel__sse2_2x8);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700602 }
603 }
604 }
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800605#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700606
607
Marat Dukhan69c3f2c2019-11-06 12:30:01 -0800608#if XNN_ARCH_X86 || XNN_ARCH_X86_64
609 TEST(F32_PRELU__SSE41_2X4, channels_eq_4) {
610 TEST_REQUIRES_X86_SSE41;
611 PReLUMicrokernelTester()
612 .rows(2)
613 .channels(4)
614 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
615 }
616
617 TEST(F32_PRELU__SSE41_2X4, channels_div_4) {
618 TEST_REQUIRES_X86_SSE41;
619 for (size_t channels = 8; channels < 40; channels += 4) {
620 PReLUMicrokernelTester()
621 .rows(2)
622 .channels(channels)
623 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
624 }
625 }
626
627 TEST(F32_PRELU__SSE41_2X4, channels_lt_4) {
628 TEST_REQUIRES_X86_SSE41;
629 for (size_t channels = 1; channels < 4; channels++) {
630 PReLUMicrokernelTester()
631 .rows(2)
632 .channels(channels)
633 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
634 }
635 }
636
637 TEST(F32_PRELU__SSE41_2X4, channels_gt_4) {
638 TEST_REQUIRES_X86_SSE41;
639 for (size_t channels = 5; channels < 8; channels++) {
640 PReLUMicrokernelTester()
641 .rows(2)
642 .channels(channels)
643 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
644 }
645 }
646
647 TEST(F32_PRELU__SSE41_2X4, rows_lt_2) {
648 TEST_REQUIRES_X86_SSE41;
649 for (size_t rows = 1; rows < 2; rows++) {
650 for (size_t channels = 1; channels <= 20; channels += 3) {
651 PReLUMicrokernelTester()
652 .rows(rows)
653 .channels(channels)
654 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
655 }
656 }
657 }
658
659 TEST(F32_PRELU__SSE41_2X4, rows_div_2) {
660 TEST_REQUIRES_X86_SSE41;
661 for (size_t rows = 4; rows <= 8; rows += 2) {
662 for (size_t channels = 1; channels <= 20; channels += 3) {
663 PReLUMicrokernelTester()
664 .rows(rows)
665 .channels(channels)
666 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
667 }
668 }
669 }
670
671 TEST(F32_PRELU__SSE41_2X4, rows_gt_2) {
672 TEST_REQUIRES_X86_SSE41;
673 for (size_t rows = 3; rows < 4; rows++) {
674 for (size_t channels = 1; channels <= 20; channels += 3) {
675 PReLUMicrokernelTester()
676 .rows(rows)
677 .channels(channels)
678 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
679 }
680 }
681 }
682
683 TEST(F32_PRELU__SSE41_2X4, input_stride) {
684 TEST_REQUIRES_X86_SSE41;
685 for (size_t rows = 1; rows <= 6; rows += 1) {
686 for (size_t channels = 1; channels <= 20; channels += 3) {
687 PReLUMicrokernelTester()
688 .rows(rows)
689 .channels(channels)
690 .input_stride(23)
691 .iterations(1)
692 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
693 }
694 }
695 }
696
697 TEST(F32_PRELU__SSE41_2X4, output_stride) {
698 TEST_REQUIRES_X86_SSE41;
699 for (size_t rows = 1; rows <= 6; rows += 1) {
700 for (size_t channels = 1; channels <= 20; channels += 3) {
701 PReLUMicrokernelTester()
702 .rows(rows)
703 .channels(channels)
704 .output_stride(23)
705 .iterations(1)
706 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
707 }
708 }
709 }
710
711 TEST(F32_PRELU__SSE41_2X4, inplace) {
712 TEST_REQUIRES_X86_SSE41;
713 for (size_t rows = 1; rows <= 6; rows += 1) {
714 for (size_t channels = 1; channels <= 20; channels += 3) {
715 PReLUMicrokernelTester()
716 .rows(rows)
717 .channels(channels)
718 .inplace(true)
719 .iterations(1)
720 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
721 }
722 }
723 }
724
725 TEST(F32_PRELU__SSE41_2X4, qmin) {
726 TEST_REQUIRES_X86_SSE41;
727 for (size_t rows = 1; rows <= 6; rows += 1) {
728 for (size_t channels = 1; channels <= 20; channels += 3) {
729 PReLUMicrokernelTester()
730 .rows(rows)
731 .channels(channels)
732 .qmin(128)
733 .iterations(1)
734 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
735 }
736 }
737 }
738
739 TEST(F32_PRELU__SSE41_2X4, qmax) {
740 TEST_REQUIRES_X86_SSE41;
741 for (size_t rows = 1; rows <= 6; rows += 1) {
742 for (size_t channels = 1; channels <= 20; channels += 3) {
743 PReLUMicrokernelTester()
744 .rows(rows)
745 .channels(channels)
746 .qmax(128)
747 .iterations(1)
748 .Test(xnn_f32_prelu_ukernel__sse41_2x4);
749 }
750 }
751 }
752#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
753
754
755#if XNN_ARCH_X86 || XNN_ARCH_X86_64
756 TEST(F32_PRELU__SSE41_2X8, channels_eq_8) {
757 TEST_REQUIRES_X86_SSE41;
758 PReLUMicrokernelTester()
759 .rows(2)
760 .channels(8)
761 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
762 }
763
764 TEST(F32_PRELU__SSE41_2X8, channels_div_8) {
765 TEST_REQUIRES_X86_SSE41;
766 for (size_t channels = 16; channels < 80; channels += 8) {
767 PReLUMicrokernelTester()
768 .rows(2)
769 .channels(channels)
770 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
771 }
772 }
773
774 TEST(F32_PRELU__SSE41_2X8, channels_lt_8) {
775 TEST_REQUIRES_X86_SSE41;
776 for (size_t channels = 1; channels < 8; channels++) {
777 PReLUMicrokernelTester()
778 .rows(2)
779 .channels(channels)
780 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
781 }
782 }
783
784 TEST(F32_PRELU__SSE41_2X8, channels_gt_8) {
785 TEST_REQUIRES_X86_SSE41;
786 for (size_t channels = 9; channels < 16; channels++) {
787 PReLUMicrokernelTester()
788 .rows(2)
789 .channels(channels)
790 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
791 }
792 }
793
794 TEST(F32_PRELU__SSE41_2X8, rows_lt_2) {
795 TEST_REQUIRES_X86_SSE41;
796 for (size_t rows = 1; rows < 2; rows++) {
797 for (size_t channels = 1; channels <= 40; channels += 7) {
798 PReLUMicrokernelTester()
799 .rows(rows)
800 .channels(channels)
801 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
802 }
803 }
804 }
805
806 TEST(F32_PRELU__SSE41_2X8, rows_div_2) {
807 TEST_REQUIRES_X86_SSE41;
808 for (size_t rows = 4; rows <= 8; rows += 2) {
809 for (size_t channels = 1; channels <= 40; channels += 7) {
810 PReLUMicrokernelTester()
811 .rows(rows)
812 .channels(channels)
813 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
814 }
815 }
816 }
817
818 TEST(F32_PRELU__SSE41_2X8, rows_gt_2) {
819 TEST_REQUIRES_X86_SSE41;
820 for (size_t rows = 3; rows < 4; rows++) {
821 for (size_t channels = 1; channels <= 40; channels += 7) {
822 PReLUMicrokernelTester()
823 .rows(rows)
824 .channels(channels)
825 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
826 }
827 }
828 }
829
830 TEST(F32_PRELU__SSE41_2X8, input_stride) {
831 TEST_REQUIRES_X86_SSE41;
832 for (size_t rows = 1; rows <= 6; rows += 1) {
833 for (size_t channels = 1; channels <= 40; channels += 7) {
834 PReLUMicrokernelTester()
835 .rows(rows)
836 .channels(channels)
837 .input_stride(43)
838 .iterations(1)
839 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
840 }
841 }
842 }
843
844 TEST(F32_PRELU__SSE41_2X8, output_stride) {
845 TEST_REQUIRES_X86_SSE41;
846 for (size_t rows = 1; rows <= 6; rows += 1) {
847 for (size_t channels = 1; channels <= 40; channels += 7) {
848 PReLUMicrokernelTester()
849 .rows(rows)
850 .channels(channels)
851 .output_stride(43)
852 .iterations(1)
853 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
854 }
855 }
856 }
857
858 TEST(F32_PRELU__SSE41_2X8, inplace) {
859 TEST_REQUIRES_X86_SSE41;
860 for (size_t rows = 1; rows <= 6; rows += 1) {
861 for (size_t channels = 1; channels <= 40; channels += 7) {
862 PReLUMicrokernelTester()
863 .rows(rows)
864 .channels(channels)
865 .inplace(true)
866 .iterations(1)
867 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
868 }
869 }
870 }
871
872 TEST(F32_PRELU__SSE41_2X8, qmin) {
873 TEST_REQUIRES_X86_SSE41;
874 for (size_t rows = 1; rows <= 6; rows += 1) {
875 for (size_t channels = 1; channels <= 40; channels += 7) {
876 PReLUMicrokernelTester()
877 .rows(rows)
878 .channels(channels)
879 .qmin(128)
880 .iterations(1)
881 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
882 }
883 }
884 }
885
886 TEST(F32_PRELU__SSE41_2X8, qmax) {
887 TEST_REQUIRES_X86_SSE41;
888 for (size_t rows = 1; rows <= 6; rows += 1) {
889 for (size_t channels = 1; channels <= 40; channels += 7) {
890 PReLUMicrokernelTester()
891 .rows(rows)
892 .channels(channels)
893 .qmax(128)
894 .iterations(1)
895 .Test(xnn_f32_prelu_ukernel__sse41_2x8);
896 }
897 }
898 }
899#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
900
901
902#if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM
903 TEST(F32_PRELU__PSIMD_2X4, channels_eq_4) {
904 TEST_REQUIRES_PSIMD;
905 PReLUMicrokernelTester()
906 .rows(2)
907 .channels(4)
908 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
909 }
910
911 TEST(F32_PRELU__PSIMD_2X4, channels_div_4) {
912 TEST_REQUIRES_PSIMD;
913 for (size_t channels = 8; channels < 40; channels += 4) {
914 PReLUMicrokernelTester()
915 .rows(2)
916 .channels(channels)
917 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
918 }
919 }
920
921 TEST(F32_PRELU__PSIMD_2X4, channels_lt_4) {
922 TEST_REQUIRES_PSIMD;
923 for (size_t channels = 1; channels < 4; channels++) {
924 PReLUMicrokernelTester()
925 .rows(2)
926 .channels(channels)
927 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
928 }
929 }
930
931 TEST(F32_PRELU__PSIMD_2X4, channels_gt_4) {
932 TEST_REQUIRES_PSIMD;
933 for (size_t channels = 5; channels < 8; channels++) {
934 PReLUMicrokernelTester()
935 .rows(2)
936 .channels(channels)
937 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
938 }
939 }
940
941 TEST(F32_PRELU__PSIMD_2X4, rows_lt_2) {
942 TEST_REQUIRES_PSIMD;
943 for (size_t rows = 1; rows < 2; rows++) {
944 for (size_t channels = 1; channels <= 20; channels += 3) {
945 PReLUMicrokernelTester()
946 .rows(rows)
947 .channels(channels)
948 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
949 }
950 }
951 }
952
953 TEST(F32_PRELU__PSIMD_2X4, rows_div_2) {
954 TEST_REQUIRES_PSIMD;
955 for (size_t rows = 4; rows <= 8; rows += 2) {
956 for (size_t channels = 1; channels <= 20; channels += 3) {
957 PReLUMicrokernelTester()
958 .rows(rows)
959 .channels(channels)
960 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
961 }
962 }
963 }
964
965 TEST(F32_PRELU__PSIMD_2X4, rows_gt_2) {
966 TEST_REQUIRES_PSIMD;
967 for (size_t rows = 3; rows < 4; rows++) {
968 for (size_t channels = 1; channels <= 20; channels += 3) {
969 PReLUMicrokernelTester()
970 .rows(rows)
971 .channels(channels)
972 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
973 }
974 }
975 }
976
977 TEST(F32_PRELU__PSIMD_2X4, input_stride) {
978 TEST_REQUIRES_PSIMD;
979 for (size_t rows = 1; rows <= 6; rows += 1) {
980 for (size_t channels = 1; channels <= 20; channels += 3) {
981 PReLUMicrokernelTester()
982 .rows(rows)
983 .channels(channels)
984 .input_stride(23)
985 .iterations(1)
986 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
987 }
988 }
989 }
990
991 TEST(F32_PRELU__PSIMD_2X4, output_stride) {
992 TEST_REQUIRES_PSIMD;
993 for (size_t rows = 1; rows <= 6; rows += 1) {
994 for (size_t channels = 1; channels <= 20; channels += 3) {
995 PReLUMicrokernelTester()
996 .rows(rows)
997 .channels(channels)
998 .output_stride(23)
999 .iterations(1)
1000 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
1001 }
1002 }
1003 }
1004
1005 TEST(F32_PRELU__PSIMD_2X4, inplace) {
1006 TEST_REQUIRES_PSIMD;
1007 for (size_t rows = 1; rows <= 6; rows += 1) {
1008 for (size_t channels = 1; channels <= 20; channels += 3) {
1009 PReLUMicrokernelTester()
1010 .rows(rows)
1011 .channels(channels)
1012 .inplace(true)
1013 .iterations(1)
1014 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
1015 }
1016 }
1017 }
1018
1019 TEST(F32_PRELU__PSIMD_2X4, qmin) {
1020 TEST_REQUIRES_PSIMD;
1021 for (size_t rows = 1; rows <= 6; rows += 1) {
1022 for (size_t channels = 1; channels <= 20; channels += 3) {
1023 PReLUMicrokernelTester()
1024 .rows(rows)
1025 .channels(channels)
1026 .qmin(128)
1027 .iterations(1)
1028 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
1029 }
1030 }
1031 }
1032
1033 TEST(F32_PRELU__PSIMD_2X4, qmax) {
1034 TEST_REQUIRES_PSIMD;
1035 for (size_t rows = 1; rows <= 6; rows += 1) {
1036 for (size_t channels = 1; channels <= 20; channels += 3) {
1037 PReLUMicrokernelTester()
1038 .rows(rows)
1039 .channels(channels)
1040 .qmax(128)
1041 .iterations(1)
1042 .Test(xnn_f32_prelu_ukernel__psimd_2x4, PReLUMicrokernelTester::Variant::Scalar);
1043 }
1044 }
1045 }
1046#endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM
1047
1048
1049#if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM
1050 TEST(F32_PRELU__PSIMD_2X8, channels_eq_8) {
1051 TEST_REQUIRES_PSIMD;
1052 PReLUMicrokernelTester()
1053 .rows(2)
1054 .channels(8)
1055 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1056 }
1057
1058 TEST(F32_PRELU__PSIMD_2X8, channels_div_8) {
1059 TEST_REQUIRES_PSIMD;
1060 for (size_t channels = 16; channels < 80; channels += 8) {
1061 PReLUMicrokernelTester()
1062 .rows(2)
1063 .channels(channels)
1064 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1065 }
1066 }
1067
1068 TEST(F32_PRELU__PSIMD_2X8, channels_lt_8) {
1069 TEST_REQUIRES_PSIMD;
1070 for (size_t channels = 1; channels < 8; channels++) {
1071 PReLUMicrokernelTester()
1072 .rows(2)
1073 .channels(channels)
1074 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1075 }
1076 }
1077
1078 TEST(F32_PRELU__PSIMD_2X8, channels_gt_8) {
1079 TEST_REQUIRES_PSIMD;
1080 for (size_t channels = 9; channels < 16; channels++) {
1081 PReLUMicrokernelTester()
1082 .rows(2)
1083 .channels(channels)
1084 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1085 }
1086 }
1087
1088 TEST(F32_PRELU__PSIMD_2X8, rows_lt_2) {
1089 TEST_REQUIRES_PSIMD;
1090 for (size_t rows = 1; rows < 2; rows++) {
1091 for (size_t channels = 1; channels <= 40; channels += 7) {
1092 PReLUMicrokernelTester()
1093 .rows(rows)
1094 .channels(channels)
1095 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1096 }
1097 }
1098 }
1099
1100 TEST(F32_PRELU__PSIMD_2X8, rows_div_2) {
1101 TEST_REQUIRES_PSIMD;
1102 for (size_t rows = 4; rows <= 8; rows += 2) {
1103 for (size_t channels = 1; channels <= 40; channels += 7) {
1104 PReLUMicrokernelTester()
1105 .rows(rows)
1106 .channels(channels)
1107 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1108 }
1109 }
1110 }
1111
1112 TEST(F32_PRELU__PSIMD_2X8, rows_gt_2) {
1113 TEST_REQUIRES_PSIMD;
1114 for (size_t rows = 3; rows < 4; rows++) {
1115 for (size_t channels = 1; channels <= 40; channels += 7) {
1116 PReLUMicrokernelTester()
1117 .rows(rows)
1118 .channels(channels)
1119 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1120 }
1121 }
1122 }
1123
1124 TEST(F32_PRELU__PSIMD_2X8, input_stride) {
1125 TEST_REQUIRES_PSIMD;
1126 for (size_t rows = 1; rows <= 6; rows += 1) {
1127 for (size_t channels = 1; channels <= 40; channels += 7) {
1128 PReLUMicrokernelTester()
1129 .rows(rows)
1130 .channels(channels)
1131 .input_stride(43)
1132 .iterations(1)
1133 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1134 }
1135 }
1136 }
1137
1138 TEST(F32_PRELU__PSIMD_2X8, output_stride) {
1139 TEST_REQUIRES_PSIMD;
1140 for (size_t rows = 1; rows <= 6; rows += 1) {
1141 for (size_t channels = 1; channels <= 40; channels += 7) {
1142 PReLUMicrokernelTester()
1143 .rows(rows)
1144 .channels(channels)
1145 .output_stride(43)
1146 .iterations(1)
1147 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1148 }
1149 }
1150 }
1151
1152 TEST(F32_PRELU__PSIMD_2X8, inplace) {
1153 TEST_REQUIRES_PSIMD;
1154 for (size_t rows = 1; rows <= 6; rows += 1) {
1155 for (size_t channels = 1; channels <= 40; channels += 7) {
1156 PReLUMicrokernelTester()
1157 .rows(rows)
1158 .channels(channels)
1159 .inplace(true)
1160 .iterations(1)
1161 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1162 }
1163 }
1164 }
1165
1166 TEST(F32_PRELU__PSIMD_2X8, qmin) {
1167 TEST_REQUIRES_PSIMD;
1168 for (size_t rows = 1; rows <= 6; rows += 1) {
1169 for (size_t channels = 1; channels <= 40; channels += 7) {
1170 PReLUMicrokernelTester()
1171 .rows(rows)
1172 .channels(channels)
1173 .qmin(128)
1174 .iterations(1)
1175 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1176 }
1177 }
1178 }
1179
1180 TEST(F32_PRELU__PSIMD_2X8, qmax) {
1181 TEST_REQUIRES_PSIMD;
1182 for (size_t rows = 1; rows <= 6; rows += 1) {
1183 for (size_t channels = 1; channels <= 40; channels += 7) {
1184 PReLUMicrokernelTester()
1185 .rows(rows)
1186 .channels(channels)
1187 .qmax(128)
1188 .iterations(1)
1189 .Test(xnn_f32_prelu_ukernel__psimd_2x8, PReLUMicrokernelTester::Variant::Scalar);
1190 }
1191 }
1192 }
1193#endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM
1194
1195
Marat Dukhan436ebe62019-12-04 15:10:12 -08001196#if XNN_ARCH_WASM
1197 TEST(F32_PRELU__WASM_2X1, channels_eq_1) {
1198 PReLUMicrokernelTester()
1199 .rows(2)
1200 .channels(1)
1201 .Test(xnn_f32_prelu_ukernel__wasm_2x1, PReLUMicrokernelTester::Variant::Scalar);
1202 }
1203
1204 TEST(F32_PRELU__WASM_2X1, channels_gt_1) {
1205 for (size_t channels = 2; channels < 10; channels++) {
1206 PReLUMicrokernelTester()
1207 .rows(2)
1208 .channels(channels)
1209 .Test(xnn_f32_prelu_ukernel__wasm_2x1, PReLUMicrokernelTester::Variant::Scalar);
1210 }
1211 }
1212
1213 TEST(F32_PRELU__WASM_2X1, rows_lt_2) {
1214 for (size_t rows = 1; rows < 2; rows++) {
1215 for (size_t channels = 1; channels <= 5; channels += 1) {
1216 PReLUMicrokernelTester()
1217 .rows(rows)
1218 .channels(channels)
1219 .Test(xnn_f32_prelu_ukernel__wasm_2x1, PReLUMicrokernelTester::Variant::Scalar);
1220 }
1221 }
1222 }
1223
1224 TEST(F32_PRELU__WASM_2X1, rows_div_2) {
1225 for (size_t rows = 4; rows <= 8; rows += 2) {
1226 for (size_t channels = 1; channels <= 5; channels += 1) {
1227 PReLUMicrokernelTester()
1228 .rows(rows)
1229 .channels(channels)
1230 .Test(xnn_f32_prelu_ukernel__wasm_2x1, PReLUMicrokernelTester::Variant::Scalar);
1231 }
1232 }
1233 }
1234
1235 TEST(F32_PRELU__WASM_2X1, rows_gt_2) {
1236 for (size_t rows = 3; rows < 4; rows++) {
1237 for (size_t channels = 1; channels <= 5; channels += 1) {
1238 PReLUMicrokernelTester()
1239 .rows(rows)
1240 .channels(channels)
1241 .Test(xnn_f32_prelu_ukernel__wasm_2x1, PReLUMicrokernelTester::Variant::Scalar);
1242 }
1243 }
1244 }
1245
1246 TEST(F32_PRELU__WASM_2X1, input_stride) {
1247 for (size_t rows = 1; rows <= 6; rows += 1) {
1248 for (size_t channels = 1; channels <= 5; channels += 1) {
1249 PReLUMicrokernelTester()
1250 .rows(rows)
1251 .channels(channels)
1252 .input_stride(7)
1253 .iterations(1)
1254 .Test(xnn_f32_prelu_ukernel__wasm_2x1, PReLUMicrokernelTester::Variant::Scalar);
1255 }
1256 }
1257 }
1258
1259 TEST(F32_PRELU__WASM_2X1, output_stride) {
1260 for (size_t rows = 1; rows <= 6; rows += 1) {
1261 for (size_t channels = 1; channels <= 5; channels += 1) {
1262 PReLUMicrokernelTester()
1263 .rows(rows)
1264 .channels(channels)
1265 .output_stride(7)
1266 .iterations(1)
1267 .Test(xnn_f32_prelu_ukernel__wasm_2x1, PReLUMicrokernelTester::Variant::Scalar);
1268 }
1269 }
1270 }
1271
1272 TEST(F32_PRELU__WASM_2X1, inplace) {
1273 for (size_t rows = 1; rows <= 6; rows += 1) {
1274 for (size_t channels = 1; channels <= 5; channels += 1) {
1275 PReLUMicrokernelTester()
1276 .rows(rows)
1277 .channels(channels)
1278 .inplace(true)
1279 .iterations(1)
1280 .Test(xnn_f32_prelu_ukernel__wasm_2x1, PReLUMicrokernelTester::Variant::Scalar);
1281 }
1282 }
1283 }
1284
1285 TEST(F32_PRELU__WASM_2X1, qmin) {
1286 for (size_t rows = 1; rows <= 6; rows += 1) {
1287 for (size_t channels = 1; channels <= 5; channels += 1) {
1288 PReLUMicrokernelTester()
1289 .rows(rows)
1290 .channels(channels)
1291 .qmin(128)
1292 .iterations(1)
1293 .Test(xnn_f32_prelu_ukernel__wasm_2x1, PReLUMicrokernelTester::Variant::Scalar);
1294 }
1295 }
1296 }
1297
1298 TEST(F32_PRELU__WASM_2X1, qmax) {
1299 for (size_t rows = 1; rows <= 6; rows += 1) {
1300 for (size_t channels = 1; channels <= 5; channels += 1) {
1301 PReLUMicrokernelTester()
1302 .rows(rows)
1303 .channels(channels)
1304 .qmax(128)
1305 .iterations(1)
1306 .Test(xnn_f32_prelu_ukernel__wasm_2x1, PReLUMicrokernelTester::Variant::Scalar);
1307 }
1308 }
1309 }
1310#endif // XNN_ARCH_WASM
1311
1312
1313#if XNN_ARCH_WASM
1314 TEST(F32_PRELU__WASM_2X4, channels_eq_4) {
1315 PReLUMicrokernelTester()
1316 .rows(2)
1317 .channels(4)
1318 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1319 }
1320
1321 TEST(F32_PRELU__WASM_2X4, channels_div_4) {
1322 for (size_t channels = 8; channels < 40; channels += 4) {
1323 PReLUMicrokernelTester()
1324 .rows(2)
1325 .channels(channels)
1326 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1327 }
1328 }
1329
1330 TEST(F32_PRELU__WASM_2X4, channels_lt_4) {
1331 for (size_t channels = 1; channels < 4; channels++) {
1332 PReLUMicrokernelTester()
1333 .rows(2)
1334 .channels(channels)
1335 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1336 }
1337 }
1338
1339 TEST(F32_PRELU__WASM_2X4, channels_gt_4) {
1340 for (size_t channels = 5; channels < 8; channels++) {
1341 PReLUMicrokernelTester()
1342 .rows(2)
1343 .channels(channels)
1344 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1345 }
1346 }
1347
1348 TEST(F32_PRELU__WASM_2X4, rows_lt_2) {
1349 for (size_t rows = 1; rows < 2; rows++) {
1350 for (size_t channels = 1; channels <= 20; channels += 3) {
1351 PReLUMicrokernelTester()
1352 .rows(rows)
1353 .channels(channels)
1354 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1355 }
1356 }
1357 }
1358
1359 TEST(F32_PRELU__WASM_2X4, rows_div_2) {
1360 for (size_t rows = 4; rows <= 8; rows += 2) {
1361 for (size_t channels = 1; channels <= 20; channels += 3) {
1362 PReLUMicrokernelTester()
1363 .rows(rows)
1364 .channels(channels)
1365 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1366 }
1367 }
1368 }
1369
1370 TEST(F32_PRELU__WASM_2X4, rows_gt_2) {
1371 for (size_t rows = 3; rows < 4; rows++) {
1372 for (size_t channels = 1; channels <= 20; channels += 3) {
1373 PReLUMicrokernelTester()
1374 .rows(rows)
1375 .channels(channels)
1376 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1377 }
1378 }
1379 }
1380
1381 TEST(F32_PRELU__WASM_2X4, input_stride) {
1382 for (size_t rows = 1; rows <= 6; rows += 1) {
1383 for (size_t channels = 1; channels <= 20; channels += 3) {
1384 PReLUMicrokernelTester()
1385 .rows(rows)
1386 .channels(channels)
1387 .input_stride(23)
1388 .iterations(1)
1389 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1390 }
1391 }
1392 }
1393
1394 TEST(F32_PRELU__WASM_2X4, output_stride) {
1395 for (size_t rows = 1; rows <= 6; rows += 1) {
1396 for (size_t channels = 1; channels <= 20; channels += 3) {
1397 PReLUMicrokernelTester()
1398 .rows(rows)
1399 .channels(channels)
1400 .output_stride(23)
1401 .iterations(1)
1402 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1403 }
1404 }
1405 }
1406
1407 TEST(F32_PRELU__WASM_2X4, inplace) {
1408 for (size_t rows = 1; rows <= 6; rows += 1) {
1409 for (size_t channels = 1; channels <= 20; channels += 3) {
1410 PReLUMicrokernelTester()
1411 .rows(rows)
1412 .channels(channels)
1413 .inplace(true)
1414 .iterations(1)
1415 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1416 }
1417 }
1418 }
1419
1420 TEST(F32_PRELU__WASM_2X4, qmin) {
1421 for (size_t rows = 1; rows <= 6; rows += 1) {
1422 for (size_t channels = 1; channels <= 20; channels += 3) {
1423 PReLUMicrokernelTester()
1424 .rows(rows)
1425 .channels(channels)
1426 .qmin(128)
1427 .iterations(1)
1428 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1429 }
1430 }
1431 }
1432
1433 TEST(F32_PRELU__WASM_2X4, qmax) {
1434 for (size_t rows = 1; rows <= 6; rows += 1) {
1435 for (size_t channels = 1; channels <= 20; channels += 3) {
1436 PReLUMicrokernelTester()
1437 .rows(rows)
1438 .channels(channels)
1439 .qmax(128)
1440 .iterations(1)
1441 .Test(xnn_f32_prelu_ukernel__wasm_2x4, PReLUMicrokernelTester::Variant::Scalar);
1442 }
1443 }
1444 }
1445#endif // XNN_ARCH_WASM
1446
1447
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001448TEST(F32_PRELU__SCALAR_2X1, channels_eq_1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001449 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001450 .rows(2)
1451 .channels(1)
1452 .Test(xnn_f32_prelu_ukernel__scalar_2x1, PReLUMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001453}
1454
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001455TEST(F32_PRELU__SCALAR_2X1, channels_gt_1) {
Marat Dukhan0f06b5c2019-11-07 19:55:54 -08001456 for (size_t channels = 2; channels < 10; channels++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001457 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001458 .rows(2)
1459 .channels(channels)
1460 .Test(xnn_f32_prelu_ukernel__scalar_2x1, PReLUMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001461 }
1462}
1463
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001464TEST(F32_PRELU__SCALAR_2X1, rows_lt_2) {
1465 for (size_t rows = 1; rows < 2; rows++) {
1466 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001467 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001468 .rows(rows)
1469 .channels(channels)
1470 .Test(xnn_f32_prelu_ukernel__scalar_2x1, PReLUMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001471 }
1472 }
1473}
1474
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001475TEST(F32_PRELU__SCALAR_2X1, rows_div_2) {
1476 for (size_t rows = 4; rows <= 8; rows += 2) {
1477 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001478 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001479 .rows(rows)
1480 .channels(channels)
1481 .Test(xnn_f32_prelu_ukernel__scalar_2x1, PReLUMicrokernelTester::Variant::Scalar);
1482 }
1483 }
1484}
1485
1486TEST(F32_PRELU__SCALAR_2X1, rows_gt_2) {
1487 for (size_t rows = 3; rows < 4; rows++) {
1488 for (size_t channels = 1; channels <= 5; channels += 1) {
1489 PReLUMicrokernelTester()
1490 .rows(rows)
1491 .channels(channels)
1492 .Test(xnn_f32_prelu_ukernel__scalar_2x1, PReLUMicrokernelTester::Variant::Scalar);
1493 }
1494 }
1495}
1496
1497TEST(F32_PRELU__SCALAR_2X1, input_stride) {
1498 for (size_t rows = 1; rows <= 6; rows += 1) {
1499 for (size_t channels = 1; channels <= 5; channels += 1) {
1500 PReLUMicrokernelTester()
1501 .rows(rows)
1502 .channels(channels)
1503 .input_stride(7)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001504 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001505 .Test(xnn_f32_prelu_ukernel__scalar_2x1, PReLUMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001506 }
1507 }
1508}
1509
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001510TEST(F32_PRELU__SCALAR_2X1, output_stride) {
1511 for (size_t rows = 1; rows <= 6; rows += 1) {
1512 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001513 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001514 .rows(rows)
1515 .channels(channels)
1516 .output_stride(7)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001517 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001518 .Test(xnn_f32_prelu_ukernel__scalar_2x1, PReLUMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001519 }
1520 }
1521}
1522
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001523TEST(F32_PRELU__SCALAR_2X1, inplace) {
1524 for (size_t rows = 1; rows <= 6; rows += 1) {
1525 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001526 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001527 .rows(rows)
1528 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001529 .inplace(true)
1530 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001531 .Test(xnn_f32_prelu_ukernel__scalar_2x1, PReLUMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001532 }
1533 }
1534}
1535
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001536TEST(F32_PRELU__SCALAR_2X1, qmin) {
1537 for (size_t rows = 1; rows <= 6; rows += 1) {
1538 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001539 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001540 .rows(rows)
1541 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001542 .qmin(128)
1543 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001544 .Test(xnn_f32_prelu_ukernel__scalar_2x1, PReLUMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001545 }
1546 }
1547}
1548
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001549TEST(F32_PRELU__SCALAR_2X1, qmax) {
1550 for (size_t rows = 1; rows <= 6; rows += 1) {
1551 for (size_t channels = 1; channels <= 5; channels += 1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -07001552 PReLUMicrokernelTester()
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001553 .rows(rows)
1554 .channels(channels)
XNNPACK Teamb455b122019-09-27 18:10:33 -07001555 .qmax(128)
1556 .iterations(1)
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001557 .Test(xnn_f32_prelu_ukernel__scalar_2x1, PReLUMicrokernelTester::Variant::Scalar);
XNNPACK Teamb455b122019-09-27 18:10:33 -07001558 }
1559 }
1560}
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08001561
1562TEST(F32_PRELU__SCALAR_2X4, channels_eq_4) {
1563 PReLUMicrokernelTester()
1564 .rows(2)
1565 .channels(4)
1566 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1567}
1568
1569TEST(F32_PRELU__SCALAR_2X4, channels_div_4) {
1570 for (size_t channels = 8; channels < 40; channels += 4) {
1571 PReLUMicrokernelTester()
1572 .rows(2)
1573 .channels(channels)
1574 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1575 }
1576}
1577
1578TEST(F32_PRELU__SCALAR_2X4, channels_lt_4) {
1579 for (size_t channels = 1; channels < 4; channels++) {
1580 PReLUMicrokernelTester()
1581 .rows(2)
1582 .channels(channels)
1583 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1584 }
1585}
1586
1587TEST(F32_PRELU__SCALAR_2X4, channels_gt_4) {
1588 for (size_t channels = 5; channels < 8; channels++) {
1589 PReLUMicrokernelTester()
1590 .rows(2)
1591 .channels(channels)
1592 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1593 }
1594}
1595
1596TEST(F32_PRELU__SCALAR_2X4, rows_lt_2) {
1597 for (size_t rows = 1; rows < 2; rows++) {
1598 for (size_t channels = 1; channels <= 20; channels += 3) {
1599 PReLUMicrokernelTester()
1600 .rows(rows)
1601 .channels(channels)
1602 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1603 }
1604 }
1605}
1606
1607TEST(F32_PRELU__SCALAR_2X4, rows_div_2) {
1608 for (size_t rows = 4; rows <= 8; rows += 2) {
1609 for (size_t channels = 1; channels <= 20; channels += 3) {
1610 PReLUMicrokernelTester()
1611 .rows(rows)
1612 .channels(channels)
1613 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1614 }
1615 }
1616}
1617
1618TEST(F32_PRELU__SCALAR_2X4, rows_gt_2) {
1619 for (size_t rows = 3; rows < 4; rows++) {
1620 for (size_t channels = 1; channels <= 20; channels += 3) {
1621 PReLUMicrokernelTester()
1622 .rows(rows)
1623 .channels(channels)
1624 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1625 }
1626 }
1627}
1628
1629TEST(F32_PRELU__SCALAR_2X4, input_stride) {
1630 for (size_t rows = 1; rows <= 6; rows += 1) {
1631 for (size_t channels = 1; channels <= 20; channels += 3) {
1632 PReLUMicrokernelTester()
1633 .rows(rows)
1634 .channels(channels)
1635 .input_stride(23)
1636 .iterations(1)
1637 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1638 }
1639 }
1640}
1641
1642TEST(F32_PRELU__SCALAR_2X4, output_stride) {
1643 for (size_t rows = 1; rows <= 6; rows += 1) {
1644 for (size_t channels = 1; channels <= 20; channels += 3) {
1645 PReLUMicrokernelTester()
1646 .rows(rows)
1647 .channels(channels)
1648 .output_stride(23)
1649 .iterations(1)
1650 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1651 }
1652 }
1653}
1654
1655TEST(F32_PRELU__SCALAR_2X4, inplace) {
1656 for (size_t rows = 1; rows <= 6; rows += 1) {
1657 for (size_t channels = 1; channels <= 20; channels += 3) {
1658 PReLUMicrokernelTester()
1659 .rows(rows)
1660 .channels(channels)
1661 .inplace(true)
1662 .iterations(1)
1663 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1664 }
1665 }
1666}
1667
1668TEST(F32_PRELU__SCALAR_2X4, qmin) {
1669 for (size_t rows = 1; rows <= 6; rows += 1) {
1670 for (size_t channels = 1; channels <= 20; channels += 3) {
1671 PReLUMicrokernelTester()
1672 .rows(rows)
1673 .channels(channels)
1674 .qmin(128)
1675 .iterations(1)
1676 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1677 }
1678 }
1679}
1680
1681TEST(F32_PRELU__SCALAR_2X4, qmax) {
1682 for (size_t rows = 1; rows <= 6; rows += 1) {
1683 for (size_t channels = 1; channels <= 20; channels += 3) {
1684 PReLUMicrokernelTester()
1685 .rows(rows)
1686 .channels(channels)
1687 .qmax(128)
1688 .iterations(1)
1689 .Test(xnn_f32_prelu_ukernel__scalar_2x4, PReLUMicrokernelTester::Variant::Scalar);
1690 }
1691 }
1692}