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Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001// Copyright 2019 Google LLC
2//
3// This source code is licensed under the BSD-style license found in the
4// LICENSE file in the root directory of this source tree.
5//
6// Auto-generated file. Do not edit!
7// Specification: test/f32-vlrelu.yaml
8// Generator: tools/generate-vunary-test.py
9
10
11#include <gtest/gtest.h>
12
13#include <xnnpack/common.h>
14#include <xnnpack/isa-checks.h>
15
16#include <xnnpack/vunary.h>
17#include "vunary-microkernel-tester.h"
18
19
20#if XNN_ARCH_ARM || XNN_ARCH_ARM64
21 TEST(F32_VLRELU__NEON_X4, batch_eq_4) {
22 TEST_REQUIRES_ARM_NEON;
Marat Dukhan87ed45c2021-05-13 12:25:22 -070023 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070024 .batch_size(4)
Marat Dukhan2894e992021-12-30 08:29:48 -080025 .Test(xnn_f32_vlrelu_ukernel__neon_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070026 }
27
28 TEST(F32_VLRELU__NEON_X4, batch_div_4) {
29 TEST_REQUIRES_ARM_NEON;
30 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070031 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070032 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -080033 .Test(xnn_f32_vlrelu_ukernel__neon_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070034 }
35 }
36
37 TEST(F32_VLRELU__NEON_X4, batch_lt_4) {
38 TEST_REQUIRES_ARM_NEON;
39 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070040 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070041 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -080042 .Test(xnn_f32_vlrelu_ukernel__neon_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070043 }
44 }
45
46 TEST(F32_VLRELU__NEON_X4, batch_gt_4) {
47 TEST_REQUIRES_ARM_NEON;
48 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070049 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070050 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -080051 .Test(xnn_f32_vlrelu_ukernel__neon_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070052 }
53 }
54
55 TEST(F32_VLRELU__NEON_X4, inplace) {
56 TEST_REQUIRES_ARM_NEON;
57 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070058 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070059 .batch_size(batch_size)
60 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -080061 .Test(xnn_f32_vlrelu_ukernel__neon_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070062 }
63 }
64
65 TEST(F32_VLRELU__NEON_X4, slope) {
66 TEST_REQUIRES_ARM_NEON;
67 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
68 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070069 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070070 .batch_size(batch_size)
71 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -080072 .Test(xnn_f32_vlrelu_ukernel__neon_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070073 }
74 }
75 }
76#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
77
78
79#if XNN_ARCH_ARM || XNN_ARCH_ARM64
80 TEST(F32_VLRELU__NEON_X8, batch_eq_8) {
81 TEST_REQUIRES_ARM_NEON;
Marat Dukhan87ed45c2021-05-13 12:25:22 -070082 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070083 .batch_size(8)
Marat Dukhan2894e992021-12-30 08:29:48 -080084 .Test(xnn_f32_vlrelu_ukernel__neon_x8, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070085 }
86
87 TEST(F32_VLRELU__NEON_X8, batch_div_8) {
88 TEST_REQUIRES_ARM_NEON;
89 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070090 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070091 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -080092 .Test(xnn_f32_vlrelu_ukernel__neon_x8, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -070093 }
94 }
95
96 TEST(F32_VLRELU__NEON_X8, batch_lt_8) {
97 TEST_REQUIRES_ARM_NEON;
98 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -070099 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700100 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800101 .Test(xnn_f32_vlrelu_ukernel__neon_x8, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700102 }
103 }
104
105 TEST(F32_VLRELU__NEON_X8, batch_gt_8) {
106 TEST_REQUIRES_ARM_NEON;
107 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700108 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700109 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800110 .Test(xnn_f32_vlrelu_ukernel__neon_x8, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700111 }
112 }
113
114 TEST(F32_VLRELU__NEON_X8, inplace) {
115 TEST_REQUIRES_ARM_NEON;
116 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700117 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700118 .batch_size(batch_size)
119 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800120 .Test(xnn_f32_vlrelu_ukernel__neon_x8, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700121 }
122 }
123
124 TEST(F32_VLRELU__NEON_X8, slope) {
125 TEST_REQUIRES_ARM_NEON;
126 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
127 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700128 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700129 .batch_size(batch_size)
130 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800131 .Test(xnn_f32_vlrelu_ukernel__neon_x8, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700132 }
133 }
134 }
135#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
136
137
138#if XNN_ARCH_X86 || XNN_ARCH_X86_64
139 TEST(F32_VLRELU__SSE_X4, batch_eq_4) {
140 TEST_REQUIRES_X86_SSE;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700141 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700142 .batch_size(4)
Marat Dukhan2894e992021-12-30 08:29:48 -0800143 .Test(xnn_f32_vlrelu_ukernel__sse_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700144 }
145
146 TEST(F32_VLRELU__SSE_X4, batch_div_4) {
147 TEST_REQUIRES_X86_SSE;
148 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700149 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700150 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800151 .Test(xnn_f32_vlrelu_ukernel__sse_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700152 }
153 }
154
155 TEST(F32_VLRELU__SSE_X4, batch_lt_4) {
156 TEST_REQUIRES_X86_SSE;
157 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700158 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700159 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800160 .Test(xnn_f32_vlrelu_ukernel__sse_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700161 }
162 }
163
164 TEST(F32_VLRELU__SSE_X4, batch_gt_4) {
165 TEST_REQUIRES_X86_SSE;
166 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700167 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700168 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800169 .Test(xnn_f32_vlrelu_ukernel__sse_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700170 }
171 }
172
173 TEST(F32_VLRELU__SSE_X4, inplace) {
174 TEST_REQUIRES_X86_SSE;
175 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700176 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700177 .batch_size(batch_size)
178 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800179 .Test(xnn_f32_vlrelu_ukernel__sse_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700180 }
181 }
182
183 TEST(F32_VLRELU__SSE_X4, slope) {
184 TEST_REQUIRES_X86_SSE;
185 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
186 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700187 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700188 .batch_size(batch_size)
189 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800190 .Test(xnn_f32_vlrelu_ukernel__sse_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700191 }
192 }
193 }
194#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
195
196
197#if XNN_ARCH_X86 || XNN_ARCH_X86_64
198 TEST(F32_VLRELU__SSE_X8, batch_eq_8) {
199 TEST_REQUIRES_X86_SSE;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700200 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700201 .batch_size(8)
Marat Dukhan2894e992021-12-30 08:29:48 -0800202 .Test(xnn_f32_vlrelu_ukernel__sse_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700203 }
204
205 TEST(F32_VLRELU__SSE_X8, batch_div_8) {
206 TEST_REQUIRES_X86_SSE;
207 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700208 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700209 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800210 .Test(xnn_f32_vlrelu_ukernel__sse_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700211 }
212 }
213
214 TEST(F32_VLRELU__SSE_X8, batch_lt_8) {
215 TEST_REQUIRES_X86_SSE;
216 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700217 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700218 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800219 .Test(xnn_f32_vlrelu_ukernel__sse_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700220 }
221 }
222
223 TEST(F32_VLRELU__SSE_X8, batch_gt_8) {
224 TEST_REQUIRES_X86_SSE;
225 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700226 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700227 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800228 .Test(xnn_f32_vlrelu_ukernel__sse_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700229 }
230 }
231
232 TEST(F32_VLRELU__SSE_X8, inplace) {
233 TEST_REQUIRES_X86_SSE;
234 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700235 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700236 .batch_size(batch_size)
237 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800238 .Test(xnn_f32_vlrelu_ukernel__sse_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700239 }
240 }
241
242 TEST(F32_VLRELU__SSE_X8, slope) {
243 TEST_REQUIRES_X86_SSE;
244 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
245 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700246 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700247 .batch_size(batch_size)
248 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800249 .Test(xnn_f32_vlrelu_ukernel__sse_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700250 }
251 }
252 }
253#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
254
255
256#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700257 TEST(F32_VLRELU__SSE2_X4, batch_eq_4) {
258 TEST_REQUIRES_X86_SSE2;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700259 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700260 .batch_size(4)
Marat Dukhan2894e992021-12-30 08:29:48 -0800261 .Test(xnn_f32_vlrelu_ukernel__sse2_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700262 }
263
264 TEST(F32_VLRELU__SSE2_X4, batch_div_4) {
265 TEST_REQUIRES_X86_SSE2;
266 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700267 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700268 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800269 .Test(xnn_f32_vlrelu_ukernel__sse2_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700270 }
271 }
272
273 TEST(F32_VLRELU__SSE2_X4, batch_lt_4) {
274 TEST_REQUIRES_X86_SSE2;
275 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700276 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700277 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800278 .Test(xnn_f32_vlrelu_ukernel__sse2_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700279 }
280 }
281
282 TEST(F32_VLRELU__SSE2_X4, batch_gt_4) {
283 TEST_REQUIRES_X86_SSE2;
284 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700285 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700286 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800287 .Test(xnn_f32_vlrelu_ukernel__sse2_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700288 }
289 }
290
291 TEST(F32_VLRELU__SSE2_X4, inplace) {
292 TEST_REQUIRES_X86_SSE2;
293 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700294 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700295 .batch_size(batch_size)
296 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800297 .Test(xnn_f32_vlrelu_ukernel__sse2_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700298 }
299 }
300
301 TEST(F32_VLRELU__SSE2_X4, slope) {
302 TEST_REQUIRES_X86_SSE2;
303 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
304 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700305 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700306 .batch_size(batch_size)
307 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800308 .Test(xnn_f32_vlrelu_ukernel__sse2_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700309 }
310 }
311 }
312#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
313
314
315#if XNN_ARCH_X86 || XNN_ARCH_X86_64
316 TEST(F32_VLRELU__SSE2_X8, batch_eq_8) {
317 TEST_REQUIRES_X86_SSE2;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700318 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700319 .batch_size(8)
Marat Dukhan2894e992021-12-30 08:29:48 -0800320 .Test(xnn_f32_vlrelu_ukernel__sse2_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700321 }
322
323 TEST(F32_VLRELU__SSE2_X8, batch_div_8) {
324 TEST_REQUIRES_X86_SSE2;
325 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700326 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700327 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800328 .Test(xnn_f32_vlrelu_ukernel__sse2_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700329 }
330 }
331
332 TEST(F32_VLRELU__SSE2_X8, batch_lt_8) {
333 TEST_REQUIRES_X86_SSE2;
334 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700335 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700336 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800337 .Test(xnn_f32_vlrelu_ukernel__sse2_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700338 }
339 }
340
341 TEST(F32_VLRELU__SSE2_X8, batch_gt_8) {
342 TEST_REQUIRES_X86_SSE2;
343 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700344 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700345 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800346 .Test(xnn_f32_vlrelu_ukernel__sse2_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700347 }
348 }
349
350 TEST(F32_VLRELU__SSE2_X8, inplace) {
351 TEST_REQUIRES_X86_SSE2;
352 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700353 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700354 .batch_size(batch_size)
355 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800356 .Test(xnn_f32_vlrelu_ukernel__sse2_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700357 }
358 }
359
360 TEST(F32_VLRELU__SSE2_X8, slope) {
361 TEST_REQUIRES_X86_SSE2;
362 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
363 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700364 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700365 .batch_size(batch_size)
366 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800367 .Test(xnn_f32_vlrelu_ukernel__sse2_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700368 }
369 }
370 }
371#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
372
373
374#if XNN_ARCH_X86 || XNN_ARCH_X86_64
375 TEST(F32_VLRELU__SSE41_X4, batch_eq_4) {
376 TEST_REQUIRES_X86_SSE41;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700377 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700378 .batch_size(4)
Marat Dukhan2894e992021-12-30 08:29:48 -0800379 .Test(xnn_f32_vlrelu_ukernel__sse41_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700380 }
381
382 TEST(F32_VLRELU__SSE41_X4, batch_div_4) {
383 TEST_REQUIRES_X86_SSE41;
384 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700385 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700386 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800387 .Test(xnn_f32_vlrelu_ukernel__sse41_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700388 }
389 }
390
391 TEST(F32_VLRELU__SSE41_X4, batch_lt_4) {
392 TEST_REQUIRES_X86_SSE41;
393 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700394 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700395 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800396 .Test(xnn_f32_vlrelu_ukernel__sse41_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700397 }
398 }
399
400 TEST(F32_VLRELU__SSE41_X4, batch_gt_4) {
401 TEST_REQUIRES_X86_SSE41;
402 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700403 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700404 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800405 .Test(xnn_f32_vlrelu_ukernel__sse41_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700406 }
407 }
408
409 TEST(F32_VLRELU__SSE41_X4, inplace) {
410 TEST_REQUIRES_X86_SSE41;
411 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700412 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700413 .batch_size(batch_size)
414 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800415 .Test(xnn_f32_vlrelu_ukernel__sse41_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700416 }
417 }
418
419 TEST(F32_VLRELU__SSE41_X4, slope) {
420 TEST_REQUIRES_X86_SSE41;
421 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
422 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700423 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700424 .batch_size(batch_size)
425 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800426 .Test(xnn_f32_vlrelu_ukernel__sse41_x4, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700427 }
428 }
429 }
430#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
431
432
433#if XNN_ARCH_X86 || XNN_ARCH_X86_64
434 TEST(F32_VLRELU__SSE41_X8, batch_eq_8) {
435 TEST_REQUIRES_X86_SSE41;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700436 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700437 .batch_size(8)
Marat Dukhan2894e992021-12-30 08:29:48 -0800438 .Test(xnn_f32_vlrelu_ukernel__sse41_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700439 }
440
441 TEST(F32_VLRELU__SSE41_X8, batch_div_8) {
442 TEST_REQUIRES_X86_SSE41;
443 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700444 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700445 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800446 .Test(xnn_f32_vlrelu_ukernel__sse41_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700447 }
448 }
449
450 TEST(F32_VLRELU__SSE41_X8, batch_lt_8) {
451 TEST_REQUIRES_X86_SSE41;
452 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700453 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700454 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800455 .Test(xnn_f32_vlrelu_ukernel__sse41_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700456 }
457 }
458
459 TEST(F32_VLRELU__SSE41_X8, batch_gt_8) {
460 TEST_REQUIRES_X86_SSE41;
461 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700462 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700463 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800464 .Test(xnn_f32_vlrelu_ukernel__sse41_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700465 }
466 }
467
468 TEST(F32_VLRELU__SSE41_X8, inplace) {
469 TEST_REQUIRES_X86_SSE41;
470 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700471 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700472 .batch_size(batch_size)
473 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800474 .Test(xnn_f32_vlrelu_ukernel__sse41_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700475 }
476 }
477
478 TEST(F32_VLRELU__SSE41_X8, slope) {
479 TEST_REQUIRES_X86_SSE41;
480 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
481 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700482 VUnaryMicrokernelTester()
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700483 .batch_size(batch_size)
484 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800485 .Test(xnn_f32_vlrelu_ukernel__sse41_x8, xnn_init_f32_lrelu_sse_params);
Marat Dukhan0d3f4672020-06-25 16:42:58 -0700486 }
487 }
488 }
489#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
490
491
492#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700493 TEST(F32_VLRELU__AVX_X8, batch_eq_8) {
494 TEST_REQUIRES_X86_AVX;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700495 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700496 .batch_size(8)
Marat Dukhan2894e992021-12-30 08:29:48 -0800497 .Test(xnn_f32_vlrelu_ukernel__avx_x8, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700498 }
499
500 TEST(F32_VLRELU__AVX_X8, batch_div_8) {
501 TEST_REQUIRES_X86_AVX;
502 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700503 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700504 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800505 .Test(xnn_f32_vlrelu_ukernel__avx_x8, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700506 }
507 }
508
509 TEST(F32_VLRELU__AVX_X8, batch_lt_8) {
510 TEST_REQUIRES_X86_AVX;
511 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700512 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700513 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800514 .Test(xnn_f32_vlrelu_ukernel__avx_x8, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700515 }
516 }
517
518 TEST(F32_VLRELU__AVX_X8, batch_gt_8) {
519 TEST_REQUIRES_X86_AVX;
520 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700521 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700522 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800523 .Test(xnn_f32_vlrelu_ukernel__avx_x8, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700524 }
525 }
526
527 TEST(F32_VLRELU__AVX_X8, inplace) {
528 TEST_REQUIRES_X86_AVX;
529 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700530 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700531 .batch_size(batch_size)
532 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800533 .Test(xnn_f32_vlrelu_ukernel__avx_x8, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700534 }
535 }
536
537 TEST(F32_VLRELU__AVX_X8, slope) {
538 TEST_REQUIRES_X86_AVX;
539 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
540 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700541 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700542 .batch_size(batch_size)
543 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800544 .Test(xnn_f32_vlrelu_ukernel__avx_x8, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700545 }
546 }
547 }
548#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
549
550
551#if XNN_ARCH_X86 || XNN_ARCH_X86_64
552 TEST(F32_VLRELU__AVX_X16, batch_eq_16) {
553 TEST_REQUIRES_X86_AVX;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700554 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700555 .batch_size(16)
Marat Dukhan2894e992021-12-30 08:29:48 -0800556 .Test(xnn_f32_vlrelu_ukernel__avx_x16, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700557 }
558
559 TEST(F32_VLRELU__AVX_X16, batch_div_16) {
560 TEST_REQUIRES_X86_AVX;
561 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700562 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700563 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800564 .Test(xnn_f32_vlrelu_ukernel__avx_x16, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700565 }
566 }
567
568 TEST(F32_VLRELU__AVX_X16, batch_lt_16) {
569 TEST_REQUIRES_X86_AVX;
570 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700571 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700572 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800573 .Test(xnn_f32_vlrelu_ukernel__avx_x16, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700574 }
575 }
576
577 TEST(F32_VLRELU__AVX_X16, batch_gt_16) {
578 TEST_REQUIRES_X86_AVX;
579 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700580 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700581 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800582 .Test(xnn_f32_vlrelu_ukernel__avx_x16, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700583 }
584 }
585
586 TEST(F32_VLRELU__AVX_X16, inplace) {
587 TEST_REQUIRES_X86_AVX;
588 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700589 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700590 .batch_size(batch_size)
591 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800592 .Test(xnn_f32_vlrelu_ukernel__avx_x16, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700593 }
594 }
595
596 TEST(F32_VLRELU__AVX_X16, slope) {
597 TEST_REQUIRES_X86_AVX;
598 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
599 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700600 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700601 .batch_size(batch_size)
602 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800603 .Test(xnn_f32_vlrelu_ukernel__avx_x16, xnn_init_f32_lrelu_avx_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700604 }
605 }
606 }
607#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
608
609
610#if XNN_ARCH_X86 || XNN_ARCH_X86_64
611 TEST(F32_VLRELU__AVX512F_X16, batch_eq_16) {
612 TEST_REQUIRES_X86_AVX512F;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700613 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700614 .batch_size(16)
Marat Dukhan2894e992021-12-30 08:29:48 -0800615 .Test(xnn_f32_vlrelu_ukernel__avx512f_x16, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700616 }
617
618 TEST(F32_VLRELU__AVX512F_X16, batch_div_16) {
619 TEST_REQUIRES_X86_AVX512F;
620 for (size_t batch_size = 32; batch_size < 160; batch_size += 16) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700621 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700622 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800623 .Test(xnn_f32_vlrelu_ukernel__avx512f_x16, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700624 }
625 }
626
627 TEST(F32_VLRELU__AVX512F_X16, batch_lt_16) {
628 TEST_REQUIRES_X86_AVX512F;
629 for (size_t batch_size = 1; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700630 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700631 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800632 .Test(xnn_f32_vlrelu_ukernel__avx512f_x16, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700633 }
634 }
635
636 TEST(F32_VLRELU__AVX512F_X16, batch_gt_16) {
637 TEST_REQUIRES_X86_AVX512F;
638 for (size_t batch_size = 17; batch_size < 32; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700639 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700640 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800641 .Test(xnn_f32_vlrelu_ukernel__avx512f_x16, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700642 }
643 }
644
645 TEST(F32_VLRELU__AVX512F_X16, inplace) {
646 TEST_REQUIRES_X86_AVX512F;
647 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700648 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700649 .batch_size(batch_size)
650 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800651 .Test(xnn_f32_vlrelu_ukernel__avx512f_x16, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700652 }
653 }
654
655 TEST(F32_VLRELU__AVX512F_X16, slope) {
656 TEST_REQUIRES_X86_AVX512F;
657 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
658 for (size_t batch_size = 1; batch_size <= 80; batch_size += 15) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700659 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700660 .batch_size(batch_size)
661 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800662 .Test(xnn_f32_vlrelu_ukernel__avx512f_x16, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700663 }
664 }
665 }
666#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
667
668
669#if XNN_ARCH_X86 || XNN_ARCH_X86_64
670 TEST(F32_VLRELU__AVX512F_X32, batch_eq_32) {
671 TEST_REQUIRES_X86_AVX512F;
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700672 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700673 .batch_size(32)
Marat Dukhan2894e992021-12-30 08:29:48 -0800674 .Test(xnn_f32_vlrelu_ukernel__avx512f_x32, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700675 }
676
677 TEST(F32_VLRELU__AVX512F_X32, batch_div_32) {
678 TEST_REQUIRES_X86_AVX512F;
679 for (size_t batch_size = 64; batch_size < 320; batch_size += 32) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700680 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700681 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800682 .Test(xnn_f32_vlrelu_ukernel__avx512f_x32, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700683 }
684 }
685
686 TEST(F32_VLRELU__AVX512F_X32, batch_lt_32) {
687 TEST_REQUIRES_X86_AVX512F;
688 for (size_t batch_size = 1; batch_size < 32; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700689 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700690 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800691 .Test(xnn_f32_vlrelu_ukernel__avx512f_x32, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700692 }
693 }
694
695 TEST(F32_VLRELU__AVX512F_X32, batch_gt_32) {
696 TEST_REQUIRES_X86_AVX512F;
697 for (size_t batch_size = 33; batch_size < 64; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700698 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700699 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800700 .Test(xnn_f32_vlrelu_ukernel__avx512f_x32, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700701 }
702 }
703
704 TEST(F32_VLRELU__AVX512F_X32, inplace) {
705 TEST_REQUIRES_X86_AVX512F;
706 for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700707 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700708 .batch_size(batch_size)
709 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800710 .Test(xnn_f32_vlrelu_ukernel__avx512f_x32, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700711 }
712 }
713
714 TEST(F32_VLRELU__AVX512F_X32, slope) {
715 TEST_REQUIRES_X86_AVX512F;
716 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
717 for (size_t batch_size = 1; batch_size <= 160; batch_size += 31) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700718 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700719 .batch_size(batch_size)
720 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800721 .Test(xnn_f32_vlrelu_ukernel__avx512f_x32, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700722 }
723 }
724 }
725#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
726
727
Marat Dukhan4c617792021-12-21 15:47:58 -0800728#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhane6502da2020-07-15 16:31:36 -0700729 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X4, batch_eq_4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700730 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700731 .batch_size(4)
Marat Dukhan2894e992021-12-30 08:29:48 -0800732 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700733 }
734
735 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X4, batch_div_4) {
736 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700737 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700738 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800739 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700740 }
741 }
742
743 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X4, batch_lt_4) {
744 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700745 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700746 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800747 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700748 }
749 }
750
751 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X4, batch_gt_4) {
752 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700753 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700754 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800755 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700756 }
757 }
758
759 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X4, inplace) {
760 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700761 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700762 .batch_size(batch_size)
763 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800764 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700765 }
766 }
767
768 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X4, slope) {
769 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
770 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700771 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700772 .batch_size(batch_size)
773 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800774 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700775 }
776 }
777 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800778#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhane6502da2020-07-15 16:31:36 -0700779
780
Marat Dukhan4c617792021-12-21 15:47:58 -0800781#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhane6502da2020-07-15 16:31:36 -0700782 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X8, batch_eq_8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700783 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700784 .batch_size(8)
Marat Dukhan2894e992021-12-30 08:29:48 -0800785 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700786 }
787
788 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X8, batch_div_8) {
789 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700790 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700791 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800792 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700793 }
794 }
795
796 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X8, batch_lt_8) {
797 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700798 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700799 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800800 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700801 }
802 }
803
804 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X8, batch_gt_8) {
805 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700806 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700807 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800808 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700809 }
810 }
811
812 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X8, inplace) {
813 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700814 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700815 .batch_size(batch_size)
816 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800817 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700818 }
819 }
820
821 TEST(F32_VLRELU__WASMSIMD_BITSELECT_X8, slope) {
822 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
823 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700824 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700825 .batch_size(batch_size)
826 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800827 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_bitselect_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700828 }
829 }
830 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800831#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhane6502da2020-07-15 16:31:36 -0700832
833
Marat Dukhan4c617792021-12-21 15:47:58 -0800834#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhane6502da2020-07-15 16:31:36 -0700835 TEST(F32_VLRELU__WASMSIMD_MINMAX_X4, batch_eq_4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700836 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700837 .batch_size(4)
Marat Dukhan2894e992021-12-30 08:29:48 -0800838 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700839 }
840
841 TEST(F32_VLRELU__WASMSIMD_MINMAX_X4, batch_div_4) {
842 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700843 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700844 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800845 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700846 }
847 }
848
849 TEST(F32_VLRELU__WASMSIMD_MINMAX_X4, batch_lt_4) {
850 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700851 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700852 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800853 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700854 }
855 }
856
857 TEST(F32_VLRELU__WASMSIMD_MINMAX_X4, batch_gt_4) {
858 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700859 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700860 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800861 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700862 }
863 }
864
865 TEST(F32_VLRELU__WASMSIMD_MINMAX_X4, inplace) {
866 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700867 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700868 .batch_size(batch_size)
869 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800870 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700871 }
872 }
873
874 TEST(F32_VLRELU__WASMSIMD_MINMAX_X4, slope) {
875 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
876 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700877 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700878 .batch_size(batch_size)
879 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800880 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x4, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700881 }
882 }
883 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800884#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhane6502da2020-07-15 16:31:36 -0700885
886
Marat Dukhan4c617792021-12-21 15:47:58 -0800887#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhane6502da2020-07-15 16:31:36 -0700888 TEST(F32_VLRELU__WASMSIMD_MINMAX_X8, batch_eq_8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700889 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700890 .batch_size(8)
Marat Dukhan2894e992021-12-30 08:29:48 -0800891 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700892 }
893
894 TEST(F32_VLRELU__WASMSIMD_MINMAX_X8, batch_div_8) {
895 for (size_t batch_size = 16; batch_size < 80; batch_size += 8) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700896 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700897 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800898 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700899 }
900 }
901
902 TEST(F32_VLRELU__WASMSIMD_MINMAX_X8, batch_lt_8) {
903 for (size_t batch_size = 1; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700904 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700905 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800906 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700907 }
908 }
909
910 TEST(F32_VLRELU__WASMSIMD_MINMAX_X8, batch_gt_8) {
911 for (size_t batch_size = 9; batch_size < 16; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700912 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700913 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800914 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700915 }
916 }
917
918 TEST(F32_VLRELU__WASMSIMD_MINMAX_X8, inplace) {
919 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700920 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700921 .batch_size(batch_size)
922 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800923 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700924 }
925 }
926
927 TEST(F32_VLRELU__WASMSIMD_MINMAX_X8, slope) {
928 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
929 for (size_t batch_size = 1; batch_size <= 40; batch_size += 7) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700930 VUnaryMicrokernelTester()
Marat Dukhane6502da2020-07-15 16:31:36 -0700931 .batch_size(batch_size)
932 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800933 .Test(xnn_f32_vlrelu_ukernel__wasmsimd_minmax_x8, xnn_init_f32_lrelu_wasmsimd_params);
Marat Dukhane6502da2020-07-15 16:31:36 -0700934 }
935 }
936 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800937#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhane6502da2020-07-15 16:31:36 -0700938
939
Marat Dukhan4c617792021-12-21 15:47:58 -0800940#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700941 TEST(F32_VLRELU__WASM_X1, batch_eq_1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700942 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700943 .batch_size(1)
Marat Dukhan2894e992021-12-30 08:29:48 -0800944 .Test(xnn_f32_vlrelu_ukernel__wasm_x1, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700945 }
946
947 TEST(F32_VLRELU__WASM_X1, batch_gt_1) {
948 for (size_t batch_size = 2; batch_size < 10; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700949 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700950 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800951 .Test(xnn_f32_vlrelu_ukernel__wasm_x1, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700952 }
953 }
954
955 TEST(F32_VLRELU__WASM_X1, inplace) {
956 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700957 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700958 .batch_size(batch_size)
959 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -0800960 .Test(xnn_f32_vlrelu_ukernel__wasm_x1, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700961 }
962 }
963
964 TEST(F32_VLRELU__WASM_X1, slope) {
965 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
966 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700967 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700968 .batch_size(batch_size)
969 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -0800970 .Test(xnn_f32_vlrelu_ukernel__wasm_x1, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700971 }
972 }
973 }
Marat Dukhan4c617792021-12-21 15:47:58 -0800974#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700975
976
Marat Dukhan4c617792021-12-21 15:47:58 -0800977#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700978 TEST(F32_VLRELU__WASM_X2, batch_eq_2) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700979 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700980 .batch_size(2)
Marat Dukhan2894e992021-12-30 08:29:48 -0800981 .Test(xnn_f32_vlrelu_ukernel__wasm_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700982 }
983
984 TEST(F32_VLRELU__WASM_X2, batch_div_2) {
985 for (size_t batch_size = 4; batch_size < 20; batch_size += 2) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700986 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700987 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800988 .Test(xnn_f32_vlrelu_ukernel__wasm_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700989 }
990 }
991
992 TEST(F32_VLRELU__WASM_X2, batch_lt_2) {
993 for (size_t batch_size = 1; batch_size < 2; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -0700994 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700995 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -0800996 .Test(xnn_f32_vlrelu_ukernel__wasm_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -0700997 }
998 }
999
1000 TEST(F32_VLRELU__WASM_X2, batch_gt_2) {
1001 for (size_t batch_size = 3; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001002 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001003 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -08001004 .Test(xnn_f32_vlrelu_ukernel__wasm_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001005 }
1006 }
1007
1008 TEST(F32_VLRELU__WASM_X2, inplace) {
1009 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001010 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001011 .batch_size(batch_size)
1012 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -08001013 .Test(xnn_f32_vlrelu_ukernel__wasm_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001014 }
1015 }
1016
1017 TEST(F32_VLRELU__WASM_X2, slope) {
1018 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
1019 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001020 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001021 .batch_size(batch_size)
1022 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -08001023 .Test(xnn_f32_vlrelu_ukernel__wasm_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001024 }
1025 }
1026 }
Marat Dukhan4c617792021-12-21 15:47:58 -08001027#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001028
1029
Marat Dukhan4c617792021-12-21 15:47:58 -08001030#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001031 TEST(F32_VLRELU__WASM_X4, batch_eq_4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001032 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001033 .batch_size(4)
Marat Dukhan2894e992021-12-30 08:29:48 -08001034 .Test(xnn_f32_vlrelu_ukernel__wasm_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001035 }
1036
1037 TEST(F32_VLRELU__WASM_X4, batch_div_4) {
1038 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001039 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001040 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -08001041 .Test(xnn_f32_vlrelu_ukernel__wasm_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001042 }
1043 }
1044
1045 TEST(F32_VLRELU__WASM_X4, batch_lt_4) {
1046 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001047 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001048 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -08001049 .Test(xnn_f32_vlrelu_ukernel__wasm_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001050 }
1051 }
1052
1053 TEST(F32_VLRELU__WASM_X4, batch_gt_4) {
1054 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001055 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001056 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -08001057 .Test(xnn_f32_vlrelu_ukernel__wasm_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001058 }
1059 }
1060
1061 TEST(F32_VLRELU__WASM_X4, inplace) {
1062 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001063 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001064 .batch_size(batch_size)
1065 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -08001066 .Test(xnn_f32_vlrelu_ukernel__wasm_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001067 }
1068 }
1069
1070 TEST(F32_VLRELU__WASM_X4, slope) {
1071 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
1072 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001073 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001074 .batch_size(batch_size)
1075 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -08001076 .Test(xnn_f32_vlrelu_ukernel__wasm_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001077 }
1078 }
1079 }
Marat Dukhan4c617792021-12-21 15:47:58 -08001080#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001081
1082
1083TEST(F32_VLRELU__SCALAR_X1, batch_eq_1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001084 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001085 .batch_size(1)
Marat Dukhan2894e992021-12-30 08:29:48 -08001086 .Test(xnn_f32_vlrelu_ukernel__scalar_x1, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001087}
1088
1089TEST(F32_VLRELU__SCALAR_X1, batch_gt_1) {
1090 for (size_t batch_size = 2; batch_size < 10; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001091 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001092 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -08001093 .Test(xnn_f32_vlrelu_ukernel__scalar_x1, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001094 }
1095}
1096
1097TEST(F32_VLRELU__SCALAR_X1, inplace) {
1098 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001099 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001100 .batch_size(batch_size)
1101 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -08001102 .Test(xnn_f32_vlrelu_ukernel__scalar_x1, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001103 }
1104}
1105
1106TEST(F32_VLRELU__SCALAR_X1, slope) {
1107 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
1108 for (size_t batch_size = 1; batch_size <= 5; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001109 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001110 .batch_size(batch_size)
1111 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -08001112 .Test(xnn_f32_vlrelu_ukernel__scalar_x1, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001113 }
1114 }
1115}
1116
1117TEST(F32_VLRELU__SCALAR_X2, batch_eq_2) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001118 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001119 .batch_size(2)
Marat Dukhan2894e992021-12-30 08:29:48 -08001120 .Test(xnn_f32_vlrelu_ukernel__scalar_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001121}
1122
1123TEST(F32_VLRELU__SCALAR_X2, batch_div_2) {
1124 for (size_t batch_size = 4; batch_size < 20; batch_size += 2) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001125 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001126 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -08001127 .Test(xnn_f32_vlrelu_ukernel__scalar_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001128 }
1129}
1130
1131TEST(F32_VLRELU__SCALAR_X2, batch_lt_2) {
1132 for (size_t batch_size = 1; batch_size < 2; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001133 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001134 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -08001135 .Test(xnn_f32_vlrelu_ukernel__scalar_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001136 }
1137}
1138
1139TEST(F32_VLRELU__SCALAR_X2, batch_gt_2) {
1140 for (size_t batch_size = 3; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001141 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001142 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -08001143 .Test(xnn_f32_vlrelu_ukernel__scalar_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001144 }
1145}
1146
1147TEST(F32_VLRELU__SCALAR_X2, inplace) {
1148 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001149 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001150 .batch_size(batch_size)
1151 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -08001152 .Test(xnn_f32_vlrelu_ukernel__scalar_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001153 }
1154}
1155
1156TEST(F32_VLRELU__SCALAR_X2, slope) {
1157 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
1158 for (size_t batch_size = 1; batch_size <= 10; batch_size += 1) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001159 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001160 .batch_size(batch_size)
1161 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -08001162 .Test(xnn_f32_vlrelu_ukernel__scalar_x2, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001163 }
1164 }
1165}
1166
1167TEST(F32_VLRELU__SCALAR_X4, batch_eq_4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001168 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001169 .batch_size(4)
Marat Dukhan2894e992021-12-30 08:29:48 -08001170 .Test(xnn_f32_vlrelu_ukernel__scalar_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001171}
1172
1173TEST(F32_VLRELU__SCALAR_X4, batch_div_4) {
1174 for (size_t batch_size = 8; batch_size < 40; batch_size += 4) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001175 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001176 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -08001177 .Test(xnn_f32_vlrelu_ukernel__scalar_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001178 }
1179}
1180
1181TEST(F32_VLRELU__SCALAR_X4, batch_lt_4) {
1182 for (size_t batch_size = 1; batch_size < 4; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001183 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001184 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -08001185 .Test(xnn_f32_vlrelu_ukernel__scalar_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001186 }
1187}
1188
1189TEST(F32_VLRELU__SCALAR_X4, batch_gt_4) {
1190 for (size_t batch_size = 5; batch_size < 8; batch_size++) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001191 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001192 .batch_size(batch_size)
Marat Dukhan2894e992021-12-30 08:29:48 -08001193 .Test(xnn_f32_vlrelu_ukernel__scalar_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001194 }
1195}
1196
1197TEST(F32_VLRELU__SCALAR_X4, inplace) {
1198 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001199 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001200 .batch_size(batch_size)
1201 .inplace(true)
Marat Dukhan2894e992021-12-30 08:29:48 -08001202 .Test(xnn_f32_vlrelu_ukernel__scalar_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001203 }
1204}
1205
1206TEST(F32_VLRELU__SCALAR_X4, slope) {
1207 for (float slope : std::vector<float>({-0.7f, 0.3f, 1.3f})) {
1208 for (size_t batch_size = 1; batch_size <= 20; batch_size += 3) {
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001209 VUnaryMicrokernelTester()
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001210 .batch_size(batch_size)
1211 .slope(slope)
Marat Dukhan2894e992021-12-30 08:29:48 -08001212 .Test(xnn_f32_vlrelu_ukernel__scalar_x4, xnn_init_f32_lrelu_scalar_params);
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07001213 }
1214 }
Marat Dukhan87ed45c2021-05-13 12:25:22 -07001215}