blob: 3a0084bd807c68e5ded7e5e766788051898e8947 [file] [log] [blame]
Marat Dukhan0461f2d2021-08-08 12:36:29 -07001// Copyright 2019 Google LLC
2//
3// This source code is licensed under the BSD-style license found in the
4// LICENSE file in the root directory of this source tree.
5
6#include <gtest/gtest.h>
7
8#include <xnnpack/common.h>
9#include <xnnpack/isa-checks.h>
10
11#include <xnnpack/pad.h>
12#include "pad-microkernel-tester.h"
13
14
15#if XNN_ARCH_ARM || XNN_ARCH_ARM64
16 TEST(XX_PAD__NEON, fulltile_copy_channels_eq_16) {
17 TEST_REQUIRES_ARM_NEON;
18 PadMicrokernelTester()
19 .rows(1)
20 .input_channels(16)
21 .Test(xnn_xx_pad_ukernel__neon);
22 }
23
24 TEST(XX_PAD__NEON, fulltile_copy_channels_div_16) {
25 TEST_REQUIRES_ARM_NEON;
26 for (size_t channels = 32; channels <= 48; channels += 16) {
27 PadMicrokernelTester()
28 .rows(1)
29 .input_channels(channels)
30 .Test(xnn_xx_pad_ukernel__neon);
31 }
32 }
33
34 TEST(XX_PAD__NEON, fulltile_copy_channels_lt_16) {
35 TEST_REQUIRES_ARM_NEON;
36 for (size_t channels = 1; channels < 16; channels++) {
37 PadMicrokernelTester()
38 .rows(1)
39 .input_channels(channels)
40 .Test(xnn_xx_pad_ukernel__neon);
41 }
42 }
43
44 TEST(XX_PAD__NEON, fulltile_copy_channels_gt_16) {
45 TEST_REQUIRES_ARM_NEON;
46 for (size_t channels = 17; channels < 32; channels++) {
47 PadMicrokernelTester()
48 .rows(1)
49 .input_channels(channels)
50 .Test(xnn_xx_pad_ukernel__neon);
51 }
52 }
53
54 TEST(XX_PAD__NEON, fulltile_pre_padding_eq_1) {
55 TEST_REQUIRES_ARM_NEON;
56 PadMicrokernelTester()
57 .rows(1)
58 .input_channels(1)
59 .pre_padding(1)
60 .Test(xnn_xx_pad_ukernel__neon);
61 }
62
63 TEST(XX_PAD__NEON, fulltile_pre_padding_eq_2) {
64 TEST_REQUIRES_ARM_NEON;
65 PadMicrokernelTester()
66 .rows(1)
67 .input_channels(1)
68 .pre_padding(2)
69 .Test(xnn_xx_pad_ukernel__neon);
70 }
71
72 TEST(XX_PAD__NEON, fulltile_pre_padding_eq_4) {
73 TEST_REQUIRES_ARM_NEON;
74 PadMicrokernelTester()
75 .rows(1)
76 .input_channels(1)
77 .pre_padding(4)
78 .Test(xnn_xx_pad_ukernel__neon);
79 }
80
81 TEST(XX_PAD__NEON, fulltile_pre_padding_eq_16) {
82 TEST_REQUIRES_ARM_NEON;
83 PadMicrokernelTester()
84 .rows(1)
85 .input_channels(1)
86 .pre_padding(16)
87 .Test(xnn_xx_pad_ukernel__neon);
88 }
89
90 TEST(XX_PAD__NEON, fulltile_pre_padding_div_16) {
91 TEST_REQUIRES_ARM_NEON;
92 for (size_t pre_padding = 32; pre_padding <= 48; pre_padding += 16) {
93 PadMicrokernelTester()
94 .rows(1)
95 .input_channels(1)
96 .pre_padding(pre_padding)
97 .Test(xnn_xx_pad_ukernel__neon);
98 }
99 }
100
101 TEST(XX_PAD__NEON, fulltile_pre_padding_lt_16) {
102 TEST_REQUIRES_ARM_NEON;
103 for (size_t pre_padding = 1; pre_padding < 16; pre_padding++) {
104 PadMicrokernelTester()
105 .rows(1)
106 .input_channels(1)
107 .pre_padding(pre_padding)
108 .Test(xnn_xx_pad_ukernel__neon);
109 }
110 }
111
112 TEST(XX_PAD__NEON, fulltile_pre_padding_gt_16) {
113 TEST_REQUIRES_ARM_NEON;
114 for (size_t pre_padding = 17; pre_padding < 32; pre_padding++) {
115 PadMicrokernelTester()
116 .rows(1)
117 .input_channels(1)
118 .pre_padding(pre_padding)
119 .Test(xnn_xx_pad_ukernel__neon);
120 }
121 }
122
123 TEST(XX_PAD__NEON, fulltile_post_padding_eq_1) {
124 TEST_REQUIRES_ARM_NEON;
125 PadMicrokernelTester()
126 .rows(1)
127 .input_channels(1)
128 .post_padding(1)
129 .Test(xnn_xx_pad_ukernel__neon);
130 }
131
132 TEST(XX_PAD__NEON, fulltile_post_padding_eq_2) {
133 TEST_REQUIRES_ARM_NEON;
134 PadMicrokernelTester()
135 .rows(1)
136 .input_channels(1)
137 .post_padding(2)
138 .Test(xnn_xx_pad_ukernel__neon);
139 }
140
141 TEST(XX_PAD__NEON, fulltile_post_padding_eq_4) {
142 TEST_REQUIRES_ARM_NEON;
143 PadMicrokernelTester()
144 .rows(1)
145 .input_channels(1)
146 .post_padding(4)
147 .Test(xnn_xx_pad_ukernel__neon);
148 }
149
150 TEST(XX_PAD__NEON, fulltile_post_padding_eq_16) {
151 TEST_REQUIRES_ARM_NEON;
152 PadMicrokernelTester()
153 .rows(1)
154 .input_channels(1)
155 .post_padding(16)
156 .Test(xnn_xx_pad_ukernel__neon);
157 }
158
159 TEST(XX_PAD__NEON, fulltile_post_padding_div_16) {
160 TEST_REQUIRES_ARM_NEON;
161 for (size_t post_padding = 32; post_padding <= 48; post_padding += 16) {
162 PadMicrokernelTester()
163 .rows(1)
164 .input_channels(1)
165 .post_padding(post_padding)
166 .Test(xnn_xx_pad_ukernel__neon);
167 }
168 }
169
170 TEST(XX_PAD__NEON, fulltile_post_padding_lt_16) {
171 TEST_REQUIRES_ARM_NEON;
172 for (size_t post_padding = 1; post_padding < 16; post_padding++) {
173 PadMicrokernelTester()
174 .rows(1)
175 .input_channels(1)
176 .post_padding(post_padding)
177 .Test(xnn_xx_pad_ukernel__neon);
178 }
179 }
180
181 TEST(XX_PAD__NEON, fulltile_post_padding_gt_16) {
182 TEST_REQUIRES_ARM_NEON;
183 for (size_t post_padding = 17; post_padding < 32; post_padding++) {
184 PadMicrokernelTester()
185 .rows(1)
186 .input_channels(1)
187 .pre_padding(post_padding)
188 .Test(xnn_xx_pad_ukernel__neon);
189 }
190 }
191
192 TEST(XX_PAD__NEON, multitile) {
193 TEST_REQUIRES_ARM_NEON;
194 for (size_t rows = 2; rows <= 5; rows++) {
195 for (size_t channels = 1; channels < 48; channels += 3) {
196 PadMicrokernelTester()
197 .rows(rows)
198 .input_channels(channels)
199 .pre_padding(channels)
200 .post_padding(channels)
201 .Test(xnn_xx_pad_ukernel__neon);
202 }
203 }
204 }
205
206 TEST(XX_PAD__NEON, multitile_with_input_stride) {
207 TEST_REQUIRES_ARM_NEON;
208 for (size_t rows = 2; rows <= 5; rows++) {
209 for (size_t channels = 1; channels < 48; channels += 3) {
210 PadMicrokernelTester()
211 .rows(rows)
212 .input_channels(channels)
213 .pre_padding(channels)
214 .post_padding(channels)
215 .input_stride(51)
216 .Test(xnn_xx_pad_ukernel__neon);
217 }
218 }
219 }
220
221 TEST(XX_PAD__NEON, multitile_with_output_stride) {
222 TEST_REQUIRES_ARM_NEON;
223 for (size_t rows = 2; rows <= 5; rows++) {
224 for (size_t channels = 1; channels < 48; channels += 3) {
225 PadMicrokernelTester()
226 .rows(rows)
227 .input_channels(2 * channels)
228 .pre_padding(channels)
229 .post_padding(channels)
230 .output_stride(193)
231 .Test(xnn_xx_pad_ukernel__neon);
232 }
233 }
234 }
235#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
236
237
238#if XNN_ARCH_X86 || XNN_ARCH_X86_64
239 TEST(XX_PAD__SSE2, fulltile_copy_channels_eq_16) {
240 TEST_REQUIRES_X86_SSE2;
241 PadMicrokernelTester()
242 .rows(1)
243 .input_channels(16)
244 .Test(xnn_xx_pad_ukernel__sse2);
245 }
246
247 TEST(XX_PAD__SSE2, fulltile_copy_channels_div_16) {
248 TEST_REQUIRES_X86_SSE2;
249 for (size_t channels = 32; channels <= 48; channels += 16) {
250 PadMicrokernelTester()
251 .rows(1)
252 .input_channels(channels)
253 .Test(xnn_xx_pad_ukernel__sse2);
254 }
255 }
256
257 TEST(XX_PAD__SSE2, fulltile_copy_channels_lt_16) {
258 TEST_REQUIRES_X86_SSE2;
259 for (size_t channels = 1; channels < 16; channels++) {
260 PadMicrokernelTester()
261 .rows(1)
262 .input_channels(channels)
263 .Test(xnn_xx_pad_ukernel__sse2);
264 }
265 }
266
267 TEST(XX_PAD__SSE2, fulltile_copy_channels_gt_16) {
268 TEST_REQUIRES_X86_SSE2;
269 for (size_t channels = 17; channels < 32; channels++) {
270 PadMicrokernelTester()
271 .rows(1)
272 .input_channels(channels)
273 .Test(xnn_xx_pad_ukernel__sse2);
274 }
275 }
276
277 TEST(XX_PAD__SSE2, fulltile_pre_padding_eq_1) {
278 TEST_REQUIRES_X86_SSE2;
279 PadMicrokernelTester()
280 .rows(1)
281 .input_channels(1)
282 .pre_padding(1)
283 .Test(xnn_xx_pad_ukernel__sse2);
284 }
285
286 TEST(XX_PAD__SSE2, fulltile_pre_padding_eq_2) {
287 TEST_REQUIRES_X86_SSE2;
288 PadMicrokernelTester()
289 .rows(1)
290 .input_channels(1)
291 .pre_padding(2)
292 .Test(xnn_xx_pad_ukernel__sse2);
293 }
294
295 TEST(XX_PAD__SSE2, fulltile_pre_padding_eq_4) {
296 TEST_REQUIRES_X86_SSE2;
297 PadMicrokernelTester()
298 .rows(1)
299 .input_channels(1)
300 .pre_padding(4)
301 .Test(xnn_xx_pad_ukernel__sse2);
302 }
303
304 TEST(XX_PAD__SSE2, fulltile_pre_padding_eq_16) {
305 TEST_REQUIRES_X86_SSE2;
306 PadMicrokernelTester()
307 .rows(1)
308 .input_channels(1)
309 .pre_padding(16)
310 .Test(xnn_xx_pad_ukernel__sse2);
311 }
312
313 TEST(XX_PAD__SSE2, fulltile_pre_padding_div_16) {
314 TEST_REQUIRES_X86_SSE2;
315 for (size_t pre_padding = 32; pre_padding <= 48; pre_padding += 16) {
316 PadMicrokernelTester()
317 .rows(1)
318 .input_channels(1)
319 .pre_padding(pre_padding)
320 .Test(xnn_xx_pad_ukernel__sse2);
321 }
322 }
323
324 TEST(XX_PAD__SSE2, fulltile_pre_padding_lt_16) {
325 TEST_REQUIRES_X86_SSE2;
326 for (size_t pre_padding = 1; pre_padding < 16; pre_padding++) {
327 PadMicrokernelTester()
328 .rows(1)
329 .input_channels(1)
330 .pre_padding(pre_padding)
331 .Test(xnn_xx_pad_ukernel__sse2);
332 }
333 }
334
335 TEST(XX_PAD__SSE2, fulltile_pre_padding_gt_16) {
336 TEST_REQUIRES_X86_SSE2;
337 for (size_t pre_padding = 17; pre_padding < 32; pre_padding++) {
338 PadMicrokernelTester()
339 .rows(1)
340 .input_channels(1)
341 .pre_padding(pre_padding)
342 .Test(xnn_xx_pad_ukernel__sse2);
343 }
344 }
345
346 TEST(XX_PAD__SSE2, fulltile_post_padding_eq_1) {
347 TEST_REQUIRES_X86_SSE2;
348 PadMicrokernelTester()
349 .rows(1)
350 .input_channels(1)
351 .post_padding(1)
352 .Test(xnn_xx_pad_ukernel__sse2);
353 }
354
355 TEST(XX_PAD__SSE2, fulltile_post_padding_eq_2) {
356 TEST_REQUIRES_X86_SSE2;
357 PadMicrokernelTester()
358 .rows(1)
359 .input_channels(1)
360 .post_padding(2)
361 .Test(xnn_xx_pad_ukernel__sse2);
362 }
363
364 TEST(XX_PAD__SSE2, fulltile_post_padding_eq_4) {
365 TEST_REQUIRES_X86_SSE2;
366 PadMicrokernelTester()
367 .rows(1)
368 .input_channels(1)
369 .post_padding(4)
370 .Test(xnn_xx_pad_ukernel__sse2);
371 }
372
373 TEST(XX_PAD__SSE2, fulltile_post_padding_eq_16) {
374 TEST_REQUIRES_X86_SSE2;
375 PadMicrokernelTester()
376 .rows(1)
377 .input_channels(1)
378 .post_padding(16)
379 .Test(xnn_xx_pad_ukernel__sse2);
380 }
381
382 TEST(XX_PAD__SSE2, fulltile_post_padding_div_16) {
383 TEST_REQUIRES_X86_SSE2;
384 for (size_t post_padding = 32; post_padding <= 48; post_padding += 16) {
385 PadMicrokernelTester()
386 .rows(1)
387 .input_channels(1)
388 .post_padding(post_padding)
389 .Test(xnn_xx_pad_ukernel__sse2);
390 }
391 }
392
393 TEST(XX_PAD__SSE2, fulltile_post_padding_lt_16) {
394 TEST_REQUIRES_X86_SSE2;
395 for (size_t post_padding = 1; post_padding < 16; post_padding++) {
396 PadMicrokernelTester()
397 .rows(1)
398 .input_channels(1)
399 .post_padding(post_padding)
400 .Test(xnn_xx_pad_ukernel__sse2);
401 }
402 }
403
404 TEST(XX_PAD__SSE2, fulltile_post_padding_gt_16) {
405 TEST_REQUIRES_X86_SSE2;
406 for (size_t post_padding = 17; post_padding < 32; post_padding++) {
407 PadMicrokernelTester()
408 .rows(1)
409 .input_channels(1)
410 .pre_padding(post_padding)
411 .Test(xnn_xx_pad_ukernel__sse2);
412 }
413 }
414
415 TEST(XX_PAD__SSE2, multitile) {
416 TEST_REQUIRES_X86_SSE2;
417 for (size_t rows = 2; rows <= 5; rows++) {
418 for (size_t channels = 1; channels < 48; channels += 3) {
419 PadMicrokernelTester()
420 .rows(rows)
421 .input_channels(channels)
422 .pre_padding(channels)
423 .post_padding(channels)
424 .Test(xnn_xx_pad_ukernel__sse2);
425 }
426 }
427 }
428
429 TEST(XX_PAD__SSE2, multitile_with_input_stride) {
430 TEST_REQUIRES_X86_SSE2;
431 for (size_t rows = 2; rows <= 5; rows++) {
432 for (size_t channels = 1; channels < 48; channels += 3) {
433 PadMicrokernelTester()
434 .rows(rows)
435 .input_channels(channels)
436 .pre_padding(channels)
437 .post_padding(channels)
438 .input_stride(51)
439 .Test(xnn_xx_pad_ukernel__sse2);
440 }
441 }
442 }
443
444 TEST(XX_PAD__SSE2, multitile_with_output_stride) {
445 TEST_REQUIRES_X86_SSE2;
446 for (size_t rows = 2; rows <= 5; rows++) {
447 for (size_t channels = 1; channels < 48; channels += 3) {
448 PadMicrokernelTester()
449 .rows(rows)
450 .input_channels(2 * channels)
451 .pre_padding(channels)
452 .post_padding(channels)
453 .output_stride(193)
454 .Test(xnn_xx_pad_ukernel__sse2);
455 }
456 }
457 }
458#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
459
460
461#if XNN_ARCH_WASMSIMD
462 TEST(XX_PAD__WASMSIMD, fulltile_copy_channels_eq_16) {
463 PadMicrokernelTester()
464 .rows(1)
465 .input_channels(16)
466 .Test(xnn_xx_pad_ukernel__wasmsimd);
467 }
468
469 TEST(XX_PAD__WASMSIMD, fulltile_copy_channels_div_16) {
470 for (size_t channels = 32; channels <= 48; channels += 16) {
471 PadMicrokernelTester()
472 .rows(1)
473 .input_channels(channels)
474 .Test(xnn_xx_pad_ukernel__wasmsimd);
475 }
476 }
477
478 TEST(XX_PAD__WASMSIMD, fulltile_copy_channels_lt_16) {
479 for (size_t channels = 1; channels < 16; channels++) {
480 PadMicrokernelTester()
481 .rows(1)
482 .input_channels(channels)
483 .Test(xnn_xx_pad_ukernel__wasmsimd);
484 }
485 }
486
487 TEST(XX_PAD__WASMSIMD, fulltile_copy_channels_gt_16) {
488 for (size_t channels = 17; channels < 32; channels++) {
489 PadMicrokernelTester()
490 .rows(1)
491 .input_channels(channels)
492 .Test(xnn_xx_pad_ukernel__wasmsimd);
493 }
494 }
495
496 TEST(XX_PAD__WASMSIMD, fulltile_pre_padding_eq_1) {
497 PadMicrokernelTester()
498 .rows(1)
499 .input_channels(1)
500 .pre_padding(1)
501 .Test(xnn_xx_pad_ukernel__wasmsimd);
502 }
503
504 TEST(XX_PAD__WASMSIMD, fulltile_pre_padding_eq_2) {
505 PadMicrokernelTester()
506 .rows(1)
507 .input_channels(1)
508 .pre_padding(2)
509 .Test(xnn_xx_pad_ukernel__wasmsimd);
510 }
511
512 TEST(XX_PAD__WASMSIMD, fulltile_pre_padding_eq_4) {
513 PadMicrokernelTester()
514 .rows(1)
515 .input_channels(1)
516 .pre_padding(4)
517 .Test(xnn_xx_pad_ukernel__wasmsimd);
518 }
519
520 TEST(XX_PAD__WASMSIMD, fulltile_pre_padding_eq_16) {
521 PadMicrokernelTester()
522 .rows(1)
523 .input_channels(1)
524 .pre_padding(16)
525 .Test(xnn_xx_pad_ukernel__wasmsimd);
526 }
527
528 TEST(XX_PAD__WASMSIMD, fulltile_pre_padding_div_16) {
529 for (size_t pre_padding = 32; pre_padding <= 48; pre_padding += 16) {
530 PadMicrokernelTester()
531 .rows(1)
532 .input_channels(1)
533 .pre_padding(pre_padding)
534 .Test(xnn_xx_pad_ukernel__wasmsimd);
535 }
536 }
537
538 TEST(XX_PAD__WASMSIMD, fulltile_pre_padding_lt_16) {
539 for (size_t pre_padding = 1; pre_padding < 16; pre_padding++) {
540 PadMicrokernelTester()
541 .rows(1)
542 .input_channels(1)
543 .pre_padding(pre_padding)
544 .Test(xnn_xx_pad_ukernel__wasmsimd);
545 }
546 }
547
548 TEST(XX_PAD__WASMSIMD, fulltile_pre_padding_gt_16) {
549 for (size_t pre_padding = 17; pre_padding < 32; pre_padding++) {
550 PadMicrokernelTester()
551 .rows(1)
552 .input_channels(1)
553 .pre_padding(pre_padding)
554 .Test(xnn_xx_pad_ukernel__wasmsimd);
555 }
556 }
557
558 TEST(XX_PAD__WASMSIMD, fulltile_post_padding_eq_1) {
559 PadMicrokernelTester()
560 .rows(1)
561 .input_channels(1)
562 .post_padding(1)
563 .Test(xnn_xx_pad_ukernel__wasmsimd);
564 }
565
566 TEST(XX_PAD__WASMSIMD, fulltile_post_padding_eq_2) {
567 PadMicrokernelTester()
568 .rows(1)
569 .input_channels(1)
570 .post_padding(2)
571 .Test(xnn_xx_pad_ukernel__wasmsimd);
572 }
573
574 TEST(XX_PAD__WASMSIMD, fulltile_post_padding_eq_4) {
575 PadMicrokernelTester()
576 .rows(1)
577 .input_channels(1)
578 .post_padding(4)
579 .Test(xnn_xx_pad_ukernel__wasmsimd);
580 }
581
582 TEST(XX_PAD__WASMSIMD, fulltile_post_padding_eq_16) {
583 PadMicrokernelTester()
584 .rows(1)
585 .input_channels(1)
586 .post_padding(16)
587 .Test(xnn_xx_pad_ukernel__wasmsimd);
588 }
589
590 TEST(XX_PAD__WASMSIMD, fulltile_post_padding_div_16) {
591 for (size_t post_padding = 32; post_padding <= 48; post_padding += 16) {
592 PadMicrokernelTester()
593 .rows(1)
594 .input_channels(1)
595 .post_padding(post_padding)
596 .Test(xnn_xx_pad_ukernel__wasmsimd);
597 }
598 }
599
600 TEST(XX_PAD__WASMSIMD, fulltile_post_padding_lt_16) {
601 for (size_t post_padding = 1; post_padding < 16; post_padding++) {
602 PadMicrokernelTester()
603 .rows(1)
604 .input_channels(1)
605 .post_padding(post_padding)
606 .Test(xnn_xx_pad_ukernel__wasmsimd);
607 }
608 }
609
610 TEST(XX_PAD__WASMSIMD, fulltile_post_padding_gt_16) {
611 for (size_t post_padding = 17; post_padding < 32; post_padding++) {
612 PadMicrokernelTester()
613 .rows(1)
614 .input_channels(1)
615 .pre_padding(post_padding)
616 .Test(xnn_xx_pad_ukernel__wasmsimd);
617 }
618 }
619
620 TEST(XX_PAD__WASMSIMD, multitile) {
621 for (size_t rows = 2; rows <= 5; rows++) {
622 for (size_t channels = 1; channels < 48; channels += 3) {
623 PadMicrokernelTester()
624 .rows(rows)
625 .input_channels(channels)
626 .pre_padding(channels)
627 .post_padding(channels)
628 .Test(xnn_xx_pad_ukernel__wasmsimd);
629 }
630 }
631 }
632
633 TEST(XX_PAD__WASMSIMD, multitile_with_input_stride) {
634 for (size_t rows = 2; rows <= 5; rows++) {
635 for (size_t channels = 1; channels < 48; channels += 3) {
636 PadMicrokernelTester()
637 .rows(rows)
638 .input_channels(channels)
639 .pre_padding(channels)
640 .post_padding(channels)
641 .input_stride(51)
642 .Test(xnn_xx_pad_ukernel__wasmsimd);
643 }
644 }
645 }
646
647 TEST(XX_PAD__WASMSIMD, multitile_with_output_stride) {
648 for (size_t rows = 2; rows <= 5; rows++) {
649 for (size_t channels = 1; channels < 48; channels += 3) {
650 PadMicrokernelTester()
651 .rows(rows)
652 .input_channels(2 * channels)
653 .pre_padding(channels)
654 .post_padding(channels)
655 .output_stride(193)
656 .Test(xnn_xx_pad_ukernel__wasmsimd);
657 }
658 }
659 }
660#endif // XNN_ARCH_WASMSIMD
661
662
663TEST(XX_PAD__SCALAR, fulltile_copy_channels_eq_16) {
664 PadMicrokernelTester()
665 .rows(1)
666 .input_channels(16)
667 .Test(xnn_xx_pad_ukernel__scalar);
668}
669
670TEST(XX_PAD__SCALAR, fulltile_copy_channels_div_16) {
671 for (size_t channels = 32; channels <= 48; channels += 16) {
672 PadMicrokernelTester()
673 .rows(1)
674 .input_channels(channels)
675 .Test(xnn_xx_pad_ukernel__scalar);
676 }
677}
678
679TEST(XX_PAD__SCALAR, fulltile_copy_channels_lt_16) {
680 for (size_t channels = 1; channels < 16; channels++) {
681 PadMicrokernelTester()
682 .rows(1)
683 .input_channels(channels)
684 .Test(xnn_xx_pad_ukernel__scalar);
685 }
686}
687
688TEST(XX_PAD__SCALAR, fulltile_copy_channels_gt_16) {
689 for (size_t channels = 17; channels < 32; channels++) {
690 PadMicrokernelTester()
691 .rows(1)
692 .input_channels(channels)
693 .Test(xnn_xx_pad_ukernel__scalar);
694 }
695}
696
697TEST(XX_PAD__SCALAR, fulltile_pre_padding_eq_1) {
698 PadMicrokernelTester()
699 .rows(1)
700 .input_channels(1)
701 .pre_padding(1)
702 .Test(xnn_xx_pad_ukernel__scalar);
703}
704
705TEST(XX_PAD__SCALAR, fulltile_pre_padding_eq_2) {
706 PadMicrokernelTester()
707 .rows(1)
708 .input_channels(1)
709 .pre_padding(2)
710 .Test(xnn_xx_pad_ukernel__scalar);
711}
712
713TEST(XX_PAD__SCALAR, fulltile_pre_padding_eq_4) {
714 PadMicrokernelTester()
715 .rows(1)
716 .input_channels(1)
717 .pre_padding(4)
718 .Test(xnn_xx_pad_ukernel__scalar);
719}
720
721TEST(XX_PAD__SCALAR, fulltile_pre_padding_div_4) {
722 for (size_t pre_padding = 8; pre_padding <= 12; pre_padding += 4) {
723 PadMicrokernelTester()
724 .rows(1)
725 .input_channels(1)
726 .pre_padding(pre_padding)
727 .Test(xnn_xx_pad_ukernel__scalar);
728 }
729}
730
731TEST(XX_PAD__SCALAR, fulltile_pre_padding_lt_4) {
732 for (size_t pre_padding = 1; pre_padding < 4; pre_padding++) {
733 PadMicrokernelTester()
734 .rows(1)
735 .input_channels(1)
736 .pre_padding(pre_padding)
737 .Test(xnn_xx_pad_ukernel__scalar);
738 }
739}
740
741TEST(XX_PAD__SCALAR, fulltile_pre_padding_gt_4) {
742 for (size_t pre_padding = 5; pre_padding < 8; pre_padding++) {
743 PadMicrokernelTester()
744 .rows(1)
745 .input_channels(1)
746 .pre_padding(pre_padding)
747 .Test(xnn_xx_pad_ukernel__scalar);
748 }
749}
750
751TEST(XX_PAD__SCALAR, fulltile_post_padding_eq_1) {
752 PadMicrokernelTester()
753 .rows(1)
754 .input_channels(1)
755 .post_padding(1)
756 .Test(xnn_xx_pad_ukernel__scalar);
757}
758
759TEST(XX_PAD__SCALAR, fulltile_post_padding_eq_2) {
760 PadMicrokernelTester()
761 .rows(1)
762 .input_channels(1)
763 .post_padding(2)
764 .Test(xnn_xx_pad_ukernel__scalar);
765}
766
767TEST(XX_PAD__SCALAR, fulltile_post_padding_eq_4) {
768 PadMicrokernelTester()
769 .rows(1)
770 .input_channels(1)
771 .post_padding(4)
772 .Test(xnn_xx_pad_ukernel__scalar);
773}
774
775TEST(XX_PAD__SCALAR, fulltile_post_padding_div_4) {
776 for (size_t post_padding = 8; post_padding <= 12; post_padding += 4) {
777 PadMicrokernelTester()
778 .rows(1)
779 .input_channels(1)
780 .post_padding(post_padding)
781 .Test(xnn_xx_pad_ukernel__scalar);
782 }
783}
784
785TEST(XX_PAD__SCALAR, fulltile_post_padding_lt_4) {
786 for (size_t post_padding = 1; post_padding < 4; post_padding++) {
787 PadMicrokernelTester()
788 .rows(1)
789 .input_channels(1)
790 .post_padding(post_padding)
791 .Test(xnn_xx_pad_ukernel__scalar);
792 }
793}
794
795TEST(XX_PAD__SCALAR, fulltile_post_padding_gt_4) {
796 for (size_t post_padding = 5; post_padding < 8; post_padding++) {
797 PadMicrokernelTester()
798 .rows(1)
799 .input_channels(1)
800 .pre_padding(post_padding)
801 .Test(xnn_xx_pad_ukernel__scalar);
802 }
803}
804
805TEST(XX_PAD__SCALAR, multitile) {
806 for (size_t rows = 2; rows <= 5; rows++) {
807 for (size_t channels = 1; channels < 12; channels += 3) {
808 PadMicrokernelTester()
809 .rows(rows)
810 .input_channels(channels)
811 .pre_padding(channels)
812 .post_padding(channels)
813 .Test(xnn_xx_pad_ukernel__scalar);
814 }
815 }
816}
817
818TEST(XX_PAD__SCALAR, multitile_with_input_stride) {
819 for (size_t rows = 2; rows <= 5; rows++) {
820 for (size_t channels = 1; channels < 12; channels += 3) {
821 PadMicrokernelTester()
822 .rows(rows)
823 .input_channels(channels)
824 .pre_padding(channels)
825 .post_padding(channels)
826 .input_stride(51)
827 .Test(xnn_xx_pad_ukernel__scalar);
828 }
829 }
830}
831
832TEST(XX_PAD__SCALAR, multitile_with_output_stride) {
833 for (size_t rows = 2; rows <= 5; rows++) {
834 for (size_t channels = 1; channels < 12; channels += 3) {
835 PadMicrokernelTester()
836 .rows(rows)
837 .input_channels(2 * channels)
838 .pre_padding(channels)
839 .post_padding(channels)
840 .output_stride(193)
841 .Test(xnn_xx_pad_ukernel__scalar);
842 }
843 }
844}