- 2bd2bd2 X8 & X16 Copy NC operators by Marat Dukhan · 2 years, 5 months ago
- 5756a92 F16 Max Pooling NHWC operator by Marat Dukhan · 2 years, 5 months ago
- af1671a Support FP32 weights in F16 PReLU operator by Marat Dukhan · 2 years, 5 months ago
- 10f2bf8 F16 MAXPOOL microkernel for F16C by Marat Dukhan · 2 years, 5 months ago
- 0a756b5 F16 PReLU operator by Marat Dukhan · 2 years, 5 months ago
- ba05c64 Fix MSVC compilation issues by Marat Dukhan · 2 years, 5 months ago
- 6b45a7f 16-bit Constant Pad ND operator by Marat Dukhan · 2 years, 5 months ago
- 16c0912 F16 MAXPOOL microkernel for NEON FP16ARITH by Marat Dukhan · 2 years, 5 months ago
- 9532079 Create a macro to define JIT GEMM generators by Zhi An Ng · 2 years, 5 months ago
- f30a859 Port aarch64 F32 IGEMM 1x8 A75 microkernel to JIT, add tests, benchmarks, enable in init.c if JIT is enabled by Zhi An Ng · 2 years, 5 months ago
- f672851 Implement str (s register, post index) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 1738f11 Implement ldr (post-index) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- eb7256b Port F32 GEMM A75 1x8 microkernel to JIT and specialize for min/max, add tests and benchmarks by Zhi An Ng · 2 years, 5 months ago
- 94def8a Fix bug in Convert operator on large tensors with multi-threading by Marat Dukhan · 2 years, 5 months ago
- 4620ca6 Reland "Graph rewriting for FP16 inference" by Marat Dukhan · 2 years, 5 months ago
- 6b72e6c Convert F32 IGEMM for A75 to JIT, add tests by Zhi An Ng · 2 years, 5 months ago
- 9a365d0 Revert "Graph rewriting for FP16 inference" by Antonio Sanchez · 2 years, 5 months ago
- 4decc8e Implement mov (x registers) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 8ceeebe Implement stp (x registers) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 9e51ad6 Implement cmp (x registers) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 94a0b0b Graph rewriting for FP16 inference by Marat Dukhan · 2 years, 5 months ago
- 3e3124e Make void* params argument of JIT generators const by Zhi An Ng · 2 years, 5 months ago
- 34251d8 QS8 4x8 lane GEMM AArch32 microkernel for Cortex A7 by Frank Barchard · 2 years, 5 months ago
- 101271e QC8 4x8 lane GEMM AArch32 microkernel for Cortex A7 by Frank Barchard · 2 years, 5 months ago
- 9e4d2aa QS8 4x8 lane GEMM AArch32 microkernel for Cortex A53 by Frank Barchard · 2 years, 5 months ago
- cfd947d Add neon zip microkernel generator by Alan Kelly · 2 years, 5 months ago
- 3deae1d Guard JIT-related structs and functionality behind XNN_PLATFORM_JIT by Zhi An Ng · 2 years, 5 months ago
- f9fc9ec Integrate JIT generated GEMM microkernels into create_convolution2d_nhwc by Zhi An Ng · 2 years, 5 months ago
- 348c377 QU8 GEMM/IGEMM WAsm SIMD microkernels with SR=4 by Marat Dukhan · 2 years, 5 months ago
- fbd67a7 Pad K to a multiple of SR in GEMM/IGEMM microkernels by Marat Dukhan · 2 years, 5 months ago
- f2b233b Make SSE2 microkernels consistent with neon zip microkernels. - DEC is now MOV by Alan Kelly · 2 years, 5 months ago
- 8b758bf Integrate JIT generated GEMM microkernels into create_convolution2d_nhwc by XNNPACK Team · 2 years, 5 months ago
- 64cb10f Guard JIT-related structs and functionality behind XNN_PLATFORM_JIT by XNNPACK Team · 2 years, 5 months ago
- c9a2e74 Guard JIT-related structs and functionality behind XNN_PLATFORM_JIT by Zhi An Ng · 2 years, 5 months ago
- df51e11 Integrate JIT generated GEMM microkernels into create_convolution2d_nhwc by Zhi An Ng · 2 years, 5 months ago
- c607028 Remove wb from JIT aarch32 instructions, use mem operand and ++ instead by Zhi An Ng · 2 years, 5 months ago
- d2bea50 Remove default member initializer for VRegister and ScalarVRegister so that we can aggregate initialize them (on GCC) by Zhi An Ng · 2 years, 5 months ago
- 870108c QS8/QC8 4x8 dot product IGEMM AArch32 microkernel for Cortex A55 by Frank Barchard · 2 years, 5 months ago
- 773458c Change return type for assembler functions to void to simplify code, move emit32 into common assembler by Zhi An Ng · 2 years, 5 months ago
- 752b980 Avoid importing the entire xnnpack namespace in aarch32 assembler by Zhi An Ng · 2 years, 5 months ago
- c2e2da8 Fix conversion script for aarch64 assembly kernels and convert a single F32 GEMM as a test by Zhi An Ng · 2 years, 5 months ago
- 4a1c6a8 Implement ldp (d registers) offset and post index for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 048704d Implement stp (q registers) offset and post indexed for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 3cec451 Implement tst (immediate) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 8709ac9 Implement csel for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 35d8e68 Implemnet stp (d register) offset and pre-index for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 6c30427 Remove unused transpose ukernel declarations and unnecessary semi-colons. by Alan Kelly · 2 years, 5 months ago
- 658a67d Implement add (x registers) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 80eac62 Implement cmp (immediate) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- ac654f1 QC8 4x8 dot product GEMM AArch32 microkernel for Cortex A55 by Frank Barchard · 2 years, 5 months ago
- 491e9e0 Implement ldr for s and d registers and str for d registers (post-indexed) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 0f294ad QS8 4x8 dot product GEMM AArch32 microkernel for Cortex A55 by Frank Barchard · 2 years, 5 months ago
- 2f24c3e Implement dup (vector) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- f761632 Implement str (q register, post-indexed) and str (s register, offset) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 5a5c9e1 Implement mov (VRegister) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 5e31395 Implement stp (post-indexed) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 4915509 Implement add with immediate for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 4ab1390 Rename kTbz enum to kTbxz and add comment to clarify its usage for both TBZ and TBNZ by Zhi An Ng · 2 years, 5 months ago
- b10677e Implement unconditional branch for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 56e8b91 Implement tbz for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- cdfff79 Implement ret for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 3176868 Implement sub (x register) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 3f34299 Implement st1 for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 544d73d Implement fmax and fmin (vector) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- ecfb1f0 Implement fadd (vector) for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 0981080 Implement tbnz for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 6a1151b Implement fmla for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 157b0f4 Implement ldr ldp for q registers in aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- f67f1be Implement labels and B.cond for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- e2dc2ec Implement subs for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 234d6b4 Implement prfm (only PLDL1KEEP) on aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 65ccb13 Implement movi for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 6e68f54 Implement ld1 for 1, 2, and 3 registers for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 5702efb Implement ld2r for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 04cdc41 Implement ldr for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 0ba29e7 Implement LDP for aarch64 assembler by Zhi An Ng · 2 years, 5 months ago
- 109a5eb Initial aarch64 assembler structure by Zhi An Ng · 2 years, 5 months ago
- 66eb508 Add missing declarations and unit tests for F16 DWCONV microkernels by Marat Dukhan · 2 years, 5 months ago
- 0ec25cf Duplicate test methods in gemm-microkernel-test for JIT codegen, update IGEMM generator signature and test generation script. by Zhi An Ng · 2 years, 5 months ago
- 901845c QU8 4x8 NEON MLA Lane microkernel AArch32 assembly language by Frank Barchard · 2 years, 5 months ago
- b26ead1 F16C implementation of F16 GAVGPOOL microkernels by Marat Dukhan · 2 years, 5 months ago
- c7c92b0 Generate F16 GAVGPOOL NEONFP16ARITH microkernels from template by Marat Dukhan · 2 years, 5 months ago
- 1d6b7c9 Support FP32 weights in FP16 NC Fully Connected operator by Marat Dukhan · 2 years, 5 months ago
- 6989ec4 Support FP32 weights in FP16 NHWC Convolution operator by Marat Dukhan · 2 years, 5 months ago
- 5e1a303 QC8 GEMM/IGEMM assembly microkernels for ARMv7 NEON by Frank Barchard · 2 years, 5 months ago
- 83844ae Change JIT generator signature to accept nc and kc to specialize on those values by Zhi An Ng · 2 years, 5 months ago
- 9dfdfb5 Remove unused transpose function declarations. by Alan Kelly · 2 years, 5 months ago
- 5da6d38 SSE2 transpose microkernel code generator. by Alan Kelly · 2 years, 5 months ago
- d19bde9 Add x64 scalar transpose microkernels by Alan Kelly · 2 years, 5 months ago
- cd21b02 Add x8 scalar transpose microkernels by Alan Kelly · 2 years, 5 months ago
- 84aae41 Add x16 scalar transpose microkernels by Alan Kelly · 2 years, 5 months ago
- 6315472 Remove declarations for scalar transpose microkernels that don't exist by Alan Kelly · 2 years, 5 months ago
- 58fe65e Change default JIT code buffer size to 16kb by Zhi An Ng · 2 years, 5 months ago
- 8575504 Switch QS8/QU8 GAVGPOOL NEON microkernels to RNDNU requantization by Marat Dukhan · 2 years, 5 months ago
- 33a98fa Switch QS8/QU8 VMUL[C] NEON microkernels to RNDNU requantization by Marat Dukhan · 2 years, 5 months ago
- d1f53e4 Generate QU8 GAVGPOOL microkernels from QS8 GAVGPOOL templates by Marat Dukhan · 2 years, 5 months ago
- 9e258d6 Remove multi-accumulator support in QS8 GAVGPOOL microkernels by Marat Dukhan · 2 years, 5 months ago
- 7d45d90 Create a new jit-test for jit-related tests that are not architecture specific by Zhi An Ng · 2 years, 5 months ago
- d7a4b22 Generate missing QS8 GAVGPOOL microkernels by Marat Dukhan · 2 years, 5 months ago
- 847ff5e Refactor naming of QS8 GAVGPOOL microkernels by Marat Dukhan · 2 years, 5 months ago