First public release of the ARM/Neon tests.
diff --git a/ref_vaddw.c b/ref_vaddw.c
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--- /dev/null
+++ b/ref_vaddw.c
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+/*
+
+Copyright (c) 2009, 2010, 2011 STMicroelectronics
+Written by Christophe Lyon
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+#ifdef __arm__
+#include <arm_neon.h>
+#else
+#error Target not supported
+#endif
+
+#include "stm-arm-neon-ref.h"
+
+#ifndef INSN_NAME
+#define INSN_NAME vaddw
+#define TEST_MSG "VADDW"
+#endif
+
+#define FNNAME1(NAME) void exec_ ## NAME (void)
+#define FNNAME(NAME) FNNAME1(NAME)
+
+FNNAME (INSN_NAME)
+{
+ /* Basic test: y=vaddw(x,x), then store the result. */
+#define TEST_VADDW1(INSN, T1, T2, W, W2, N) \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ INSN##_##T2##W(VECT_VAR(vector, T1, W2, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
+
+#define TEST_VADDW(INSN, T1, T2, W, W2, N) \
+ TEST_VADDW1(INSN, T1, T2, W, W2, N)
+
+ /* With ARM RVCT, we need to declare variables before any executable
+ statement */
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, uint, 64, 2);
+
+ DECL_VARIABLE(vector2, int, 8, 8);
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+ DECL_VARIABLE(vector2, uint, 8, 8);
+ DECL_VARIABLE(vector2, uint, 16, 4);
+ DECL_VARIABLE(vector2, uint, 32, 2);
+
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer" */
+ TEST_VLOAD(vector, buffer, q, int, s, 16, 8);
+ TEST_VLOAD(vector, buffer, q, int, s, 32, 4);
+ TEST_VLOAD(vector, buffer, q, int, s, 64, 2);
+ TEST_VLOAD(vector, buffer, q, uint, u, 16, 8);
+ TEST_VLOAD(vector, buffer, q, uint, u, 32, 4);
+ TEST_VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ /* Choose init value arbitrarily */
+ TEST_VDUP(vector2, , int, s, 8, 8, -13);
+ TEST_VDUP(vector2, , int, s, 16, 4, -14);
+ TEST_VDUP(vector2, , int, s, 32, 2, -16);
+ TEST_VDUP(vector2, , uint, u, 8, 8, 0xf3);
+ TEST_VDUP(vector2, , uint, u, 16, 4, 0xfff1);
+ TEST_VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
+
+ TEST_VADDW(INSN_NAME, int, s, 8, 16, 8);
+ TEST_VADDW(INSN_NAME, int, s, 16, 32, 4);
+ TEST_VADDW(INSN_NAME, int, s, 32, 64, 2);
+ TEST_VADDW(INSN_NAME, uint, u, 8, 16, 8);
+ TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4);
+ TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2);
+
+ /* FIXME: only a few result buffers are used, but we output all of them */
+ dump_results_hex (TEST_MSG);
+}