commit | 0e985d708e8f429c1fa1f557d3eea90e32de5228 | [log] [tgz] |
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author | Louis Mayencourt <louis.mayencourt@arm.com> | Tue Apr 09 16:29:01 2019 +0100 |
committer | Louis Mayencourt <louis.mayencourt@arm.com> | Wed Apr 17 13:46:43 2019 +0100 |
tree | 1fcdb2dc74d4f1f127a9360319f3426e37c2dbf5 | |
parent | 2c3b76ce7b9e36e5c8be3c454110e070a20332ca [diff] |
DSU: Implement workaround for errata 798953 Under certain near idle conditions, DSU may miss response transfers on the ACE master or Peripheral port, leading to deadlock. This workaround disables high-level clock gating of the DSU to prevent this. Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>