Merge pull request #1889 from jts-arm/var4
Apply variant 4 mitigation for Neoverse N1
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index debe872..d3c5bea 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -843,4 +843,9 @@
#define DIT S3_3_C4_C2_5
#define DIT_BIT BIT(24)
+/*******************************************************************************
+ * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
+ ******************************************************************************/
+#define SSBS S3_3_C4_C2_6
+
#endif /* ARCH_H */
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index c6a5c08..060c625 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -46,6 +46,10 @@
func neoverse_n1_reset_func
mov x19, x30
+
+ /* Disables speculative loads */
+ msr SSBS, xzr
+
bl cpu_get_rev_var
mov x18, x0