GIC: Fix Group 0 enabling

At present, the GIC drivers enable Group 0 interrupts only if there are
Secure SPIs listed in the interrupt properties/list. This means that,
even if there are Group 0 SGIs/PPIs configured, the group remained
disabled in the absence of a Group 0 SPI.

Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when
corresponding SGIs/PPIs are present.

Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c
index 2522695..dee63f1 100644
--- a/drivers/arm/gic/v3/gicv3_helpers.c
+++ b/drivers/arm/gic/v3/gicv3_helpers.c
@@ -541,12 +541,13 @@
 /*******************************************************************************
  * Helper function to configure properties of secure G0 and G1S PPIs and SGIs.
  ******************************************************************************/
-void gicv3_secure_ppi_sgi_configure_props(uintptr_t gicr_base,
+unsigned int gicv3_secure_ppi_sgi_configure_props(uintptr_t gicr_base,
 		const interrupt_prop_t *interrupt_props,
 		unsigned int interrupt_props_num)
 {
 	unsigned int i;
 	const interrupt_prop_t *current_prop;
+	unsigned int ctlr_enable = 0;
 
 	/* Make sure there's a valid property array */
 	assert(interrupt_props != NULL);
@@ -564,10 +565,13 @@
 		/* Configure this interrupt as G0 or a G1S interrupt */
 		assert((current_prop->intr_grp == INTR_GROUP0) ||
 				(current_prop->intr_grp == INTR_GROUP1S));
-		if (current_prop->intr_grp == INTR_GROUP1S)
+		if (current_prop->intr_grp == INTR_GROUP1S) {
 			gicr_set_igrpmodr0(gicr_base, current_prop->intr_num);
-		else
+			ctlr_enable |= CTLR_ENABLE_G1S_BIT;
+		} else {
 			gicr_clr_igrpmodr0(gicr_base, current_prop->intr_num);
+			ctlr_enable |= CTLR_ENABLE_G0_BIT;
+		}
 
 		/* Set the priority of this interrupt */
 		gicr_set_ipriorityr(gicr_base, current_prop->intr_num,
@@ -586,4 +590,6 @@
 		/* Enable this interrupt */
 		gicr_set_isenabler0(gicr_base, current_prop->intr_num);
 	}
+
+	return ctlr_enable;
 }