diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 73f023a..9c0927f 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -51,9 +51,6 @@
 
 	bl1_arch_next_el_setup();
 
-	/* Tell next EL what we want done */
-	bl2_ep->args.arg0 = RUN_IMAGE;
-
 	write_spsr_el3(bl2_ep->spsr);
 	write_elr_el3(bl2_ep->pc);
 
diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S
index 1d26229..75eb02a 100644
--- a/bl2/aarch64/bl2_entrypoint.S
+++ b/bl2/aarch64/bl2_entrypoint.S
@@ -39,13 +39,12 @@
 
 func bl2_entrypoint
 	/*---------------------------------------------
-	 * Store the extents of the tzram available to
-	 * BL2 for future use. Use the opcode param to
-	 * allow implement other functions if needed.
+	 * Save from x1 the extents of the tzram
+	 * available to BL2 for future use.
+	 * x0 is not currently used.
 	 * ---------------------------------------------
-	 */
-	mov	x20, x0
-	mov	x21, x1
+ 	 */
+ 	mov	x20, x1
 
 	/* ---------------------------------------------
 	 * Set the exception vector to something sane.
@@ -74,14 +73,6 @@
 	isb
 
 	/* ---------------------------------------------
-	 * Check the opcodes out of paranoia.
-	 * ---------------------------------------------
-	 */
-	mov	x0, #RUN_IMAGE
-	cmp	x0, x20
-	b.ne	_panic
-
-	/* ---------------------------------------------
 	 * Invalidate the RW memory used by the BL2
 	 * image. This includes the data and NOBITS
 	 * sections. This is done to safeguard against
@@ -126,7 +117,7 @@
 	 * specific early arch. setup e.g. mmu setup
 	 * ---------------------------------------------
 	 */
-	mov	x0, x21
+	mov	x0, x20
 	bl	bl2_early_platform_setup
 	bl	bl2_plat_arch_setup
 
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index c9a7a3d..0eec989 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -46,7 +46,6 @@
 #define BOTTOM	!TOP
 
 /******************************************************************************
- * Opcode passed in x0 to tell next EL that we want to run an image.
  * Corresponds to the function ID of the only SMC that the BL1 exception
  * handlers service. That's why the chosen value is the first function ID of
  * the ARM SMC64 range.