| commit | 5c6aa01affe14c40efdebdc9450cdbc4ae0bc494 | [log] [tgz] |
|---|---|---|
| author | Louis Mayencourt <louis.mayencourt@arm.com> | Mon Feb 25 15:17:44 2019 +0000 |
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | Tue Feb 26 16:21:06 2019 +0000 |
| tree | 4642c4f18dec3b95d02884414f2bc5124c756dc8 | |
| parent | 5cc8c7ba1b24ace2ef7345e96d933141f3609817 [diff] |
Add workaround for errata 1073348 for Cortex-A76 Concurrent instruction TLB miss and mispredicted return instruction might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to prevent this. Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>