tree f2144f3d54b1dfd7625bdcf08438573f569d2101
parent e6cab15dc710e2270d869c3fa76ed8d0d4943b66
author Louis Mayencourt <louis.mayencourt@arm.com> 1550664701 +0000
committer Louis Mayencourt <louis.mayencourt@arm.com> 1551196437 +0000

Add workaround for errata 764081 of Cortex-A75

Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.

Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>