tree fc6499c90c931c8d20aa7a569322fe8fb91bce53
parent 45b52c202f7173d7610e2ca667907a6e646e90fa
author Eleanor Bonnici <Eleanor.bonnici@arm.com> 1501695221 +0100
committer Jeenu Viswambharan <jeenu.viswambharan@arm.com> 1504790522 +0100

Cortex-A72: Implement workaround for erratum 859971

Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.

Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>