Merge pull request #1324 from michpappas/tf-issues#567Platforms_cannot_override_ENABLE_STACK_PROTECTOR
Platforms cannot override ENABLE_STACK_PROTECTOR
diff --git a/Makefile b/Makefile
index 48e078a..ca91e69 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
# Trusted Firmware Version
#
VERSION_MAJOR := 1
-VERSION_MINOR := 4
+VERSION_MINOR := 5
# Default goal is build all images
.DEFAULT_GOAL := all
diff --git a/bl1/aarch32/bl1_context_mgmt.c b/bl1/aarch32/bl1_context_mgmt.c
index 6623dfc..d1fd3ca 100644
--- a/bl1/aarch32/bl1_context_mgmt.c
+++ b/bl1/aarch32/bl1_context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,7 @@
#include <context_mgmt.h>
#include <debug.h>
#include <platform.h>
-#include <smcc_helpers.h>
+#include <smccc_helpers.h>
#include "../bl1_private.h"
/*
diff --git a/bl1/aarch32/bl1_entrypoint.S b/bl1/aarch32/bl1_entrypoint.S
index 7780626..16b26b9 100644
--- a/bl1/aarch32/bl1_entrypoint.S
+++ b/bl1/aarch32/bl1_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,8 +9,8 @@
#include <bl_common.h>
#include <context.h>
#include <el3_common_macros.S>
-#include <smcc_helpers.h>
-#include <smcc_macros.S>
+#include <smccc_helpers.h>
+#include <smccc_macros.S>
.globl bl1_vector_table
.globl bl1_entrypoint
diff --git a/bl1/aarch32/bl1_exceptions.S b/bl1/aarch32/bl1_exceptions.S
index a1e32f0..1540542 100644
--- a/bl1/aarch32/bl1_exceptions.S
+++ b/bl1/aarch32/bl1_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,8 +9,8 @@
#include <bl1.h>
#include <bl_common.h>
#include <context.h>
-#include <smcc_helpers.h>
-#include <smcc_macros.S>
+#include <smccc_helpers.h>
+#include <smccc_macros.S>
#include <xlat_tables.h>
.globl bl1_aarch32_smc_handler
@@ -93,7 +93,7 @@
* Save the GP registers.
* -----------------------------------------------------
*/
- smcc_save_gp_mode_regs
+ smccc_save_gp_mode_regs
/*
* `sp` still points to `smc_ctx_t`. Save it to a register
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index 92313fa..7ac028a 100644
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -218,7 +218,7 @@
smc_handler:
/* -----------------------------------------------------
* Save the GP registers x0-x29.
- * TODO: Revisit to store only SMCC specified registers.
+ * TODO: Revisit to store only SMCCC specified registers.
* -----------------------------------------------------
*/
bl save_gp_registers
diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c
index 3878083..ed027ab 100644
--- a/bl1/bl1_fwu.c
+++ b/bl1/bl1_fwu.c
@@ -15,7 +15,7 @@
#include <errno.h>
#include <platform.h>
#include <platform_def.h>
-#include <smcc_helpers.h>
+#include <smccc_helpers.h>
#include <string.h>
#include <utils.h>
#include "bl1_private.h"
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index c333285..9f7e290 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -15,7 +15,7 @@
#include <errata_report.h>
#include <platform.h>
#include <platform_def.h>
-#include <smcc_helpers.h>
+#include <smccc_helpers.h>
#include <utils.h>
#include <uuid.h>
#include "bl1_private.h"
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S
index 3dd2369..87ef3f3 100644
--- a/bl32/sp_min/aarch32/entrypoint.S
+++ b/bl32/sp_min/aarch32/entrypoint.S
@@ -10,8 +10,8 @@
#include <context.h>
#include <el3_common_macros.S>
#include <runtime_svc.h>
-#include <smcc_helpers.h>
-#include <smcc_macros.S>
+#include <smccc_helpers.h>
+#include <smccc_macros.S>
#include <xlat_tables_defs.h>
.globl sp_min_vector_table
@@ -164,7 +164,7 @@
/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
str lr, [sp, #SMC_CTX_LR_MON]
- smcc_save_gp_mode_regs
+ smccc_save_gp_mode_regs
clrex_on_monitor_entry
@@ -222,7 +222,7 @@
/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
str lr, [sp, #SMC_CTX_LR_MON]
- smcc_save_gp_mode_regs
+ smccc_save_gp_mode_regs
clrex_on_monitor_entry
diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c
index 4e8e685..8e891b7 100644
--- a/bl32/sp_min/sp_min_main.c
+++ b/bl32/sp_min/sp_min_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,7 +17,7 @@
#include <platform_sp_min.h>
#include <psci.h>
#include <runtime_svc.h>
-#include <smcc_helpers.h>
+#include <smccc_helpers.h>
#include <stddef.h>
#include <stdint.h>
#include <string.h>
@@ -32,7 +32,7 @@
static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT];
/******************************************************************************
- * Define the smcc helper library API's
+ * Define the smccc helper library API's
*****************************************************************************/
void *smc_get_ctx(unsigned int security_state)
{
diff --git a/docs/psci-lib-integration-guide.rst b/docs/psci-lib-integration-guide.rst
index 6e72f0e..47cbfcc 100644
--- a/docs/psci-lib-integration-guide.rst
+++ b/docs/psci-lib-integration-guide.rst
@@ -261,7 +261,7 @@
arguments), are the values of the registers r1 - r4 (in AArch32) or x1 - x4
(in AArch64) when the SMC is received. These are the arguments to PSCI API as
described in `PSCI spec`_. The 'flags' (8th argument) is a bit field parameter
-and is detailed in 'smcc.h' header. It includes whether the call is from the
+and is detailed in 'smccc.h' header. It includes whether the call is from the
secure or non-secure world. The ``cookie`` (6th argument) and the ``handle``
(7th argument) are not used and are reserved for future use.
diff --git a/docs/rt-svc-writers-guide.rst b/docs/rt-svc-writers-guide.rst
index 4d0016b..cec2ae7 100644
--- a/docs/rt-svc-writers-guide.rst
+++ b/docs/rt-svc-writers-guide.rst
@@ -108,7 +108,7 @@
is also used for diagnostic purposes
- ``_start`` and ``_end`` values must be based on the ``OEN_*`` values defined in
- `smcc.h`_
+ `smccc.h`_
- ``_type`` must be one of ``SMC_TYPE_FAST`` or ``SMC_TYPE_YIELD``
@@ -311,5 +311,5 @@
.. _services: ../services
.. _lib/psci: ../lib/psci
.. _runtime\_svc.h: ../include/common/runtime_svc.h
-.. _smcc.h: ../include/lib/smcc.h
+.. _smccc.h: ../include/lib/smccc.h
.. _std\_svc\_setup.c: ../services/std_svc/std_svc_setup.c
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 33f124a..5794855 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -38,7 +38,7 @@
RAM. For best performance, use a machine with a quad-core processor running at
2.6GHz with 16GB of RAM.
-The software has been tested on Ubuntu 14.04 LTS (64-bit). Packages used for
+The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
building the software were installed from that distribution unless otherwise
specified.
@@ -867,9 +867,12 @@
the project Makefile contains two targets, which both utilise the
``checkpatch.pl`` script that ships with the Linux source tree.
-To check the entire source tree, you must first download a copy of
-``checkpatch.pl`` (or the full Linux source), set the ``CHECKPATCH`` environment
-variable to point to the script and build the target checkcodebase:
+To check the entire source tree, you must first download copies of
+``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
+in the `Linux master tree`_ scripts directory, then set the ``CHECKPATCH``
+environment variable to point to ``checkpatch.pl`` (with the other 2 files in
+the same directory) and build the target
+checkcodebase:
::
@@ -1149,10 +1152,15 @@
Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
onwards. Before that release, pre-built binaries are only available for AArch64.
-Note: follow the full instructions for one platform before switching to a
+Note: Follow the full instructions for one platform before switching to a
different one. Mixing instructions for different platforms may result in
corrupted binaries.
+Note: The uboot image downloaded by the Linaro workspace script does not always
+match the uboot image packaged as BL33 in the corresponding fip file. It is
+recommended to use the version that is packaged in the fip file using the
+instructions below.
+
#. Clean the working directory
::
@@ -1177,11 +1185,11 @@
current working directory. The SCP\_BL2 image corresponds to
``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
- Note: the fiptool will complain if the images to be unpacked already
+ Note: The fiptool will complain if the images to be unpacked already
exist in the current directory. If that is the case, either delete those
files or use the ``--force`` option to overwrite.
- Note for AArch32, the instructions below assume that nt-fw.bin is a custom
+ Note: For AArch32, the instructions below assume that nt-fw.bin is a custom
Normal world boot loader that supports AArch32.
#. Build TF-A images and create a new FIP for FVP
@@ -1924,6 +1932,7 @@
.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
+.. _Linux master tree: <https://github.com/torvalds/linux/tree/master/>
.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
.. _here: psci-lib-integration-guide.rst
.. _Trusted Board Boot: trusted-board-boot.rst
diff --git a/drivers/arm/pl011/aarch64/pl011_console.S b/drivers/arm/pl011/aarch64/pl011_console.S
index 6f2510a..448501a 100644
--- a/drivers/arm/pl011/aarch64/pl011_console.S
+++ b/drivers/arm/pl011/aarch64/pl011_console.S
@@ -6,6 +6,7 @@
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
+#include <console_macros.S>
#include <pl011.h>
/*
diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h
index 6150b32..d12af22 100644
--- a/include/common/runtime_svc.h
+++ b/include/common/runtime_svc.h
@@ -8,7 +8,7 @@
#define __RUNTIME_SVC_H__
#include <bl_common.h> /* to include exception types */
-#include <smcc_helpers.h> /* to include SMCC definitions */
+#include <smccc_helpers.h> /* to include SMCCC definitions */
/*******************************************************************************
diff --git a/include/lib/aarch32/smcc_helpers.h b/include/lib/aarch32/smcc_helpers.h
index ed3b722..7f79f8f 100644
--- a/include/lib/aarch32/smcc_helpers.h
+++ b/include/lib/aarch32/smcc_helpers.h
@@ -7,159 +7,8 @@
#ifndef __SMCC_HELPERS_H__
#define __SMCC_HELPERS_H__
-#include <smcc.h>
+#if !ERROR_DEPRECATED
+#include <smccc_helpers.h>
+#endif
-/* These are offsets to registers in smc_ctx_t */
-#define SMC_CTX_GPREG_R0 0x0
-#define SMC_CTX_GPREG_R1 0x4
-#define SMC_CTX_GPREG_R2 0x8
-#define SMC_CTX_GPREG_R3 0xC
-#define SMC_CTX_GPREG_R4 0x10
-#define SMC_CTX_GPREG_R5 0x14
-#define SMC_CTX_SP_USR 0x34
-#define SMC_CTX_SPSR_MON 0x78
-#define SMC_CTX_SP_MON 0x7C
-#define SMC_CTX_LR_MON 0x80
-#define SMC_CTX_SCR 0x84
-#define SMC_CTX_PMCR 0x88
-#define SMC_CTX_SIZE 0x90
-
-#ifndef __ASSEMBLY__
-#include <cassert.h>
-#include <types.h>
-
-/*
- * The generic structure to save arguments and callee saved registers during
- * an SMC. Also this structure is used to store the result return values after
- * the completion of SMC service.
- */
-typedef struct smc_ctx {
- u_register_t r0;
- u_register_t r1;
- u_register_t r2;
- u_register_t r3;
- u_register_t r4;
- u_register_t r5;
- u_register_t r6;
- u_register_t r7;
- u_register_t r8;
- u_register_t r9;
- u_register_t r10;
- u_register_t r11;
- u_register_t r12;
- /* spsr_usr doesn't exist */
- u_register_t sp_usr;
- u_register_t lr_usr;
- u_register_t spsr_irq;
- u_register_t sp_irq;
- u_register_t lr_irq;
- u_register_t spsr_fiq;
- u_register_t sp_fiq;
- u_register_t lr_fiq;
- u_register_t spsr_svc;
- u_register_t sp_svc;
- u_register_t lr_svc;
- u_register_t spsr_abt;
- u_register_t sp_abt;
- u_register_t lr_abt;
- u_register_t spsr_und;
- u_register_t sp_und;
- u_register_t lr_und;
- u_register_t spsr_mon;
- /*
- * `sp_mon` will point to the C runtime stack in monitor mode. But prior
- * to exit from SMC, this will point to the `smc_ctx_t` so that
- * on next entry due to SMC, the `smc_ctx_t` can be easily accessed.
- */
- u_register_t sp_mon;
- u_register_t lr_mon;
- u_register_t scr;
- u_register_t pmcr;
- /*
- * The workaround for CVE-2017-5715 requires storing information in
- * the bottom 3 bits of the stack pointer. Add a padding field to
- * force the size of the struct to be a multiple of 8.
- */
- u_register_t pad;
-} smc_ctx_t __aligned(8);
-
-/*
- * Compile time assertions related to the 'smc_context' structure to
- * ensure that the assembler and the compiler view of the offsets of
- * the structure members is the same.
- */
-CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), \
- assert_smc_ctx_greg_r0_offset_mismatch);
-CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), \
- assert_smc_ctx_greg_r1_offset_mismatch);
-CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), \
- assert_smc_ctx_greg_r2_offset_mismatch);
-CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \
- assert_smc_ctx_greg_r3_offset_mismatch);
-CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), \
- assert_smc_ctx_greg_r4_offset_mismatch);
-CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), \
- assert_smc_ctx_sp_usr_offset_mismatch);
-CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), \
- assert_smc_ctx_lr_mon_offset_mismatch);
-CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), \
- assert_smc_ctx_spsr_mon_offset_mismatch);
-
-CASSERT((sizeof(smc_ctx_t) & 0x7) == 0, assert_smc_ctx_not_aligned);
-CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch);
-
-/* Convenience macros to return from SMC handler */
-#define SMC_RET0(_h) { \
- return (uintptr_t)(_h); \
-}
-#define SMC_RET1(_h, _r0) { \
- ((smc_ctx_t *)(_h))->r0 = (_r0); \
- SMC_RET0(_h); \
-}
-#define SMC_RET2(_h, _r0, _r1) { \
- ((smc_ctx_t *)(_h))->r1 = (_r1); \
- SMC_RET1(_h, (_r0)); \
-}
-#define SMC_RET3(_h, _r0, _r1, _r2) { \
- ((smc_ctx_t *)(_h))->r2 = (_r2); \
- SMC_RET2(_h, (_r0), (_r1)); \
-}
-#define SMC_RET4(_h, _r0, _r1, _r2, _r3) { \
- ((smc_ctx_t *)(_h))->r3 = (_r3); \
- SMC_RET3(_h, (_r0), (_r1), (_r2)); \
-}
-
-/* Return a UUID in the SMC return registers */
-#define SMC_UUID_RET(_h, _uuid) \
- SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \
- ((const uint32_t *) &(_uuid))[1], \
- ((const uint32_t *) &(_uuid))[2], \
- ((const uint32_t *) &(_uuid))[3])
-
-/*
- * Helper macro to retrieve the SMC parameters from smc_ctx_t.
- */
-#define get_smc_params_from_ctx(_hdl, _r1, _r2, _r3, _r4) { \
- _r1 = ((smc_ctx_t *)_hdl)->r1; \
- _r2 = ((smc_ctx_t *)_hdl)->r2; \
- _r3 = ((smc_ctx_t *)_hdl)->r3; \
- _r4 = ((smc_ctx_t *)_hdl)->r4; \
- }
-
-/* ------------------------------------------------------------------------
- * Helper APIs for setting and retrieving appropriate `smc_ctx_t`.
- * These functions need to implemented by the BL including this library.
- * ------------------------------------------------------------------------
- */
-
-/* Get the pointer to `smc_ctx_t` corresponding to the security state. */
-void *smc_get_ctx(unsigned int security_state);
-
-/* Set the next `smc_ctx_t` corresponding to the security state. */
-void smc_set_next_ctx(unsigned int security_state);
-
-/* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */
-void *smc_get_next_ctx(void);
-
-#endif /*__ASSEMBLY__*/
#endif /* __SMCC_HELPERS_H__ */
diff --git a/include/lib/aarch32/smcc_macros.S b/include/lib/aarch32/smcc_macros.S
index 93f211f..66f3d0e 100644
--- a/include/lib/aarch32/smcc_macros.S
+++ b/include/lib/aarch32/smcc_macros.S
@@ -1,199 +1,15 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SMCC_MACROS_S__
#define __SMCC_MACROS_S__
-#include <arch.h>
+#if !ERROR_DEPRECATED
+#include <smccc_macros.S>
-/*
- * Macro to save the General purpose registers (r0 - r12), the banked
- * spsr, lr, sp registers and the `scr` register to the SMC context on entry
- * due a SMC call. The `lr` of the current mode (monitor) is expected to be
- * already saved. The `sp` must point to the `smc_ctx_t` to save to.
- * Additionally, also save the 'pmcr' register as this is updated whilst
- * executing in the secure world.
- */
- .macro smcc_save_gp_mode_regs
- /* Save r0 - r12 in the SMC context */
- stm sp, {r0-r12}
- mov r0, sp
- add r0, r0, #SMC_CTX_SP_USR
-
-#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
- /* Must be in secure state to restore Monitor mode */
- ldcopr r4, SCR
- bic r2, r4, #SCR_NS_BIT
- stcopr r2, SCR
- isb
-
- cps #MODE32_sys
- stm r0!, {sp, lr}
-
- cps #MODE32_irq
- mrs r2, spsr
- stm r0!, {r2, sp, lr}
-
- cps #MODE32_fiq
- mrs r2, spsr
- stm r0!, {r2, sp, lr}
-
- cps #MODE32_svc
- mrs r2, spsr
- stm r0!, {r2, sp, lr}
-
- cps #MODE32_abt
- mrs r2, spsr
- stm r0!, {r2, sp, lr}
-
- cps #MODE32_und
- mrs r2, spsr
- stm r0!, {r2, sp, lr}
-
- /* lr_mon is already saved by caller */
- cps #MODE32_mon
- mrs r2, spsr
- stm r0!, {r2}
-
- stcopr r4, SCR
- isb
-#else
- /* Save the banked registers including the current SPSR and LR */
- mrs r4, sp_usr
- mrs r5, lr_usr
- mrs r6, spsr_irq
- mrs r7, sp_irq
- mrs r8, lr_irq
- mrs r9, spsr_fiq
- mrs r10, sp_fiq
- mrs r11, lr_fiq
- mrs r12, spsr_svc
- stm r0!, {r4-r12}
-
- mrs r4, sp_svc
- mrs r5, lr_svc
- mrs r6, spsr_abt
- mrs r7, sp_abt
- mrs r8, lr_abt
- mrs r9, spsr_und
- mrs r10, sp_und
- mrs r11, lr_und
- mrs r12, spsr
- stm r0!, {r4-r12}
- /* lr_mon is already saved by caller */
-
- ldcopr r4, SCR
+#define smcc_save_gp_mode_regs smccc_save_gp_mode_regs
#endif
- str r4, [sp, #SMC_CTX_SCR]
- ldcopr r4, PMCR
- str r4, [sp, #SMC_CTX_PMCR]
- .endm
-
-/*
- * Macro to restore the `smc_ctx_t`, which includes the General purpose
- * registers and banked mode registers, and exit from the monitor mode.
- * r0 must point to the `smc_ctx_t` to restore from.
- */
- .macro monitor_exit
- /*
- * Save the current sp and restore the smc context
- * pointer to sp which will be used for handling the
- * next SMC.
- */
- str sp, [r0, #SMC_CTX_SP_MON]
- mov sp, r0
-
- /*
- * Restore SCR first so that we access the right banked register
- * when the other mode registers are restored.
- */
- ldr r1, [r0, #SMC_CTX_SCR]
- stcopr r1, SCR
- isb
-
- /*
- * Restore the PMCR register.
- */
- ldr r1, [r0, #SMC_CTX_PMCR]
- stcopr r1, PMCR
-
- /* Restore the banked registers including the current SPSR */
- add r1, r0, #SMC_CTX_SP_USR
-
-#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
- /* Must be in secure state to restore Monitor mode */
- ldcopr r4, SCR
- bic r2, r4, #SCR_NS_BIT
- stcopr r2, SCR
- isb
-
- cps #MODE32_sys
- ldm r1!, {sp, lr}
-
- cps #MODE32_irq
- ldm r1!, {r2, sp, lr}
- msr spsr_fsxc, r2
-
- cps #MODE32_fiq
- ldm r1!, {r2, sp, lr}
- msr spsr_fsxc, r2
-
- cps #MODE32_svc
- ldm r1!, {r2, sp, lr}
- msr spsr_fsxc, r2
-
- cps #MODE32_abt
- ldm r1!, {r2, sp, lr}
- msr spsr_fsxc, r2
-
- cps #MODE32_und
- ldm r1!, {r2, sp, lr}
- msr spsr_fsxc, r2
-
- cps #MODE32_mon
- ldm r1!, {r2}
- msr spsr_fsxc, r2
-
- stcopr r4, SCR
- isb
-#else
- ldm r1!, {r4-r12}
- msr sp_usr, r4
- msr lr_usr, r5
- msr spsr_irq, r6
- msr sp_irq, r7
- msr lr_irq, r8
- msr spsr_fiq, r9
- msr sp_fiq, r10
- msr lr_fiq, r11
- msr spsr_svc, r12
-
- ldm r1!, {r4-r12}
- msr sp_svc, r4
- msr lr_svc, r5
- msr spsr_abt, r6
- msr sp_abt, r7
- msr lr_abt, r8
- msr spsr_und, r9
- msr sp_und, r10
- msr lr_und, r11
- /*
- * Use the `_fsxc` suffix explicitly to instruct the assembler
- * to update all the 32 bits of SPSR. Else, by default, the
- * assembler assumes `_fc` suffix which only modifies
- * f->[31:24] and c->[7:0] bits of SPSR.
- */
- msr spsr_fsxc, r12
-#endif
-
- /* Restore the LR */
- ldr lr, [r0, #SMC_CTX_LR_MON]
-
- /* Restore the rest of the general purpose registers */
- ldm r0, {r0-r12}
- eret
- .endm
#endif /* __SMCC_MACROS_S__ */
diff --git a/include/lib/aarch32/smccc_helpers.h b/include/lib/aarch32/smccc_helpers.h
new file mode 100644
index 0000000..240dd13
--- /dev/null
+++ b/include/lib/aarch32/smccc_helpers.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SMCCC_HELPERS_H__
+#define __SMCCC_HELPERS_H__
+
+#include <smccc.h>
+
+/* These are offsets to registers in smc_ctx_t */
+#define SMC_CTX_GPREG_R0 0x0
+#define SMC_CTX_GPREG_R1 0x4
+#define SMC_CTX_GPREG_R2 0x8
+#define SMC_CTX_GPREG_R3 0xC
+#define SMC_CTX_GPREG_R4 0x10
+#define SMC_CTX_GPREG_R5 0x14
+#define SMC_CTX_SP_USR 0x34
+#define SMC_CTX_SPSR_MON 0x78
+#define SMC_CTX_SP_MON 0x7C
+#define SMC_CTX_LR_MON 0x80
+#define SMC_CTX_SCR 0x84
+#define SMC_CTX_PMCR 0x88
+#define SMC_CTX_SIZE 0x90
+
+#ifndef __ASSEMBLY__
+#include <cassert.h>
+#include <types.h>
+
+/*
+ * The generic structure to save arguments and callee saved registers during
+ * an SMC. Also this structure is used to store the result return values after
+ * the completion of SMC service.
+ */
+typedef struct smc_ctx {
+ u_register_t r0;
+ u_register_t r1;
+ u_register_t r2;
+ u_register_t r3;
+ u_register_t r4;
+ u_register_t r5;
+ u_register_t r6;
+ u_register_t r7;
+ u_register_t r8;
+ u_register_t r9;
+ u_register_t r10;
+ u_register_t r11;
+ u_register_t r12;
+ /* spsr_usr doesn't exist */
+ u_register_t sp_usr;
+ u_register_t lr_usr;
+ u_register_t spsr_irq;
+ u_register_t sp_irq;
+ u_register_t lr_irq;
+ u_register_t spsr_fiq;
+ u_register_t sp_fiq;
+ u_register_t lr_fiq;
+ u_register_t spsr_svc;
+ u_register_t sp_svc;
+ u_register_t lr_svc;
+ u_register_t spsr_abt;
+ u_register_t sp_abt;
+ u_register_t lr_abt;
+ u_register_t spsr_und;
+ u_register_t sp_und;
+ u_register_t lr_und;
+ u_register_t spsr_mon;
+ /*
+ * `sp_mon` will point to the C runtime stack in monitor mode. But prior
+ * to exit from SMC, this will point to the `smc_ctx_t` so that
+ * on next entry due to SMC, the `smc_ctx_t` can be easily accessed.
+ */
+ u_register_t sp_mon;
+ u_register_t lr_mon;
+ u_register_t scr;
+ u_register_t pmcr;
+ /*
+ * The workaround for CVE-2017-5715 requires storing information in
+ * the bottom 3 bits of the stack pointer. Add a padding field to
+ * force the size of the struct to be a multiple of 8.
+ */
+ u_register_t pad;
+} smc_ctx_t __aligned(8);
+
+/*
+ * Compile time assertions related to the 'smc_context' structure to
+ * ensure that the assembler and the compiler view of the offsets of
+ * the structure members is the same.
+ */
+CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), \
+ assert_smc_ctx_greg_r0_offset_mismatch);
+CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), \
+ assert_smc_ctx_greg_r1_offset_mismatch);
+CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), \
+ assert_smc_ctx_greg_r2_offset_mismatch);
+CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \
+ assert_smc_ctx_greg_r3_offset_mismatch);
+CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), \
+ assert_smc_ctx_greg_r4_offset_mismatch);
+CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), \
+ assert_smc_ctx_sp_usr_offset_mismatch);
+CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), \
+ assert_smc_ctx_lr_mon_offset_mismatch);
+CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), \
+ assert_smc_ctx_spsr_mon_offset_mismatch);
+
+CASSERT((sizeof(smc_ctx_t) & 0x7) == 0, assert_smc_ctx_not_aligned);
+CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch);
+
+/* Convenience macros to return from SMC handler */
+#define SMC_RET0(_h) { \
+ return (uintptr_t)(_h); \
+}
+#define SMC_RET1(_h, _r0) { \
+ ((smc_ctx_t *)(_h))->r0 = (_r0); \
+ SMC_RET0(_h); \
+}
+#define SMC_RET2(_h, _r0, _r1) { \
+ ((smc_ctx_t *)(_h))->r1 = (_r1); \
+ SMC_RET1(_h, (_r0)); \
+}
+#define SMC_RET3(_h, _r0, _r1, _r2) { \
+ ((smc_ctx_t *)(_h))->r2 = (_r2); \
+ SMC_RET2(_h, (_r0), (_r1)); \
+}
+#define SMC_RET4(_h, _r0, _r1, _r2, _r3) { \
+ ((smc_ctx_t *)(_h))->r3 = (_r3); \
+ SMC_RET3(_h, (_r0), (_r1), (_r2)); \
+}
+
+/* Return a UUID in the SMC return registers */
+#define SMC_UUID_RET(_h, _uuid) \
+ SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \
+ ((const uint32_t *) &(_uuid))[1], \
+ ((const uint32_t *) &(_uuid))[2], \
+ ((const uint32_t *) &(_uuid))[3])
+
+/*
+ * Helper macro to retrieve the SMC parameters from smc_ctx_t.
+ */
+#define get_smc_params_from_ctx(_hdl, _r1, _r2, _r3, _r4) { \
+ _r1 = ((smc_ctx_t *)_hdl)->r1; \
+ _r2 = ((smc_ctx_t *)_hdl)->r2; \
+ _r3 = ((smc_ctx_t *)_hdl)->r3; \
+ _r4 = ((smc_ctx_t *)_hdl)->r4; \
+ }
+
+/* ------------------------------------------------------------------------
+ * Helper APIs for setting and retrieving appropriate `smc_ctx_t`.
+ * These functions need to implemented by the BL including this library.
+ * ------------------------------------------------------------------------
+ */
+
+/* Get the pointer to `smc_ctx_t` corresponding to the security state. */
+void *smc_get_ctx(unsigned int security_state);
+
+/* Set the next `smc_ctx_t` corresponding to the security state. */
+void smc_set_next_ctx(unsigned int security_state);
+
+/* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */
+void *smc_get_next_ctx(void);
+
+#endif /*__ASSEMBLY__*/
+
+#endif /* __SMCCC_HELPERS_H__ */
diff --git a/include/lib/aarch32/smccc_macros.S b/include/lib/aarch32/smccc_macros.S
new file mode 100644
index 0000000..fdb65e8
--- /dev/null
+++ b/include/lib/aarch32/smccc_macros.S
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __SMCCC_MACROS_S__
+#define __SMCCC_MACROS_S__
+
+#include <arch.h>
+
+/*
+ * Macro to save the General purpose registers (r0 - r12), the banked
+ * spsr, lr, sp registers and the `scr` register to the SMC context on entry
+ * due a SMC call. The `lr` of the current mode (monitor) is expected to be
+ * already saved. The `sp` must point to the `smc_ctx_t` to save to.
+ * Additionally, also save the 'pmcr' register as this is updated whilst
+ * executing in the secure world.
+ */
+ .macro smccc_save_gp_mode_regs
+ /* Save r0 - r12 in the SMC context */
+ stm sp, {r0-r12}
+ mov r0, sp
+ add r0, r0, #SMC_CTX_SP_USR
+
+#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
+ /* Must be in secure state to restore Monitor mode */
+ ldcopr r4, SCR
+ bic r2, r4, #SCR_NS_BIT
+ stcopr r2, SCR
+ isb
+
+ cps #MODE32_sys
+ stm r0!, {sp, lr}
+
+ cps #MODE32_irq
+ mrs r2, spsr
+ stm r0!, {r2, sp, lr}
+
+ cps #MODE32_fiq
+ mrs r2, spsr
+ stm r0!, {r2, sp, lr}
+
+ cps #MODE32_svc
+ mrs r2, spsr
+ stm r0!, {r2, sp, lr}
+
+ cps #MODE32_abt
+ mrs r2, spsr
+ stm r0!, {r2, sp, lr}
+
+ cps #MODE32_und
+ mrs r2, spsr
+ stm r0!, {r2, sp, lr}
+
+ /* lr_mon is already saved by caller */
+ cps #MODE32_mon
+ mrs r2, spsr
+ stm r0!, {r2}
+
+ stcopr r4, SCR
+ isb
+#else
+ /* Save the banked registers including the current SPSR and LR */
+ mrs r4, sp_usr
+ mrs r5, lr_usr
+ mrs r6, spsr_irq
+ mrs r7, sp_irq
+ mrs r8, lr_irq
+ mrs r9, spsr_fiq
+ mrs r10, sp_fiq
+ mrs r11, lr_fiq
+ mrs r12, spsr_svc
+ stm r0!, {r4-r12}
+
+ mrs r4, sp_svc
+ mrs r5, lr_svc
+ mrs r6, spsr_abt
+ mrs r7, sp_abt
+ mrs r8, lr_abt
+ mrs r9, spsr_und
+ mrs r10, sp_und
+ mrs r11, lr_und
+ mrs r12, spsr
+ stm r0!, {r4-r12}
+ /* lr_mon is already saved by caller */
+
+ ldcopr r4, SCR
+#endif
+ str r4, [sp, #SMC_CTX_SCR]
+ ldcopr r4, PMCR
+ str r4, [sp, #SMC_CTX_PMCR]
+ .endm
+
+/*
+ * Macro to restore the `smc_ctx_t`, which includes the General purpose
+ * registers and banked mode registers, and exit from the monitor mode.
+ * r0 must point to the `smc_ctx_t` to restore from.
+ */
+ .macro monitor_exit
+ /*
+ * Save the current sp and restore the smc context
+ * pointer to sp which will be used for handling the
+ * next SMC.
+ */
+ str sp, [r0, #SMC_CTX_SP_MON]
+ mov sp, r0
+
+ /*
+ * Restore SCR first so that we access the right banked register
+ * when the other mode registers are restored.
+ */
+ ldr r1, [r0, #SMC_CTX_SCR]
+ stcopr r1, SCR
+ isb
+
+ /*
+ * Restore the PMCR register.
+ */
+ ldr r1, [r0, #SMC_CTX_PMCR]
+ stcopr r1, PMCR
+
+ /* Restore the banked registers including the current SPSR */
+ add r1, r0, #SMC_CTX_SP_USR
+
+#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
+ /* Must be in secure state to restore Monitor mode */
+ ldcopr r4, SCR
+ bic r2, r4, #SCR_NS_BIT
+ stcopr r2, SCR
+ isb
+
+ cps #MODE32_sys
+ ldm r1!, {sp, lr}
+
+ cps #MODE32_irq
+ ldm r1!, {r2, sp, lr}
+ msr spsr_fsxc, r2
+
+ cps #MODE32_fiq
+ ldm r1!, {r2, sp, lr}
+ msr spsr_fsxc, r2
+
+ cps #MODE32_svc
+ ldm r1!, {r2, sp, lr}
+ msr spsr_fsxc, r2
+
+ cps #MODE32_abt
+ ldm r1!, {r2, sp, lr}
+ msr spsr_fsxc, r2
+
+ cps #MODE32_und
+ ldm r1!, {r2, sp, lr}
+ msr spsr_fsxc, r2
+
+ cps #MODE32_mon
+ ldm r1!, {r2}
+ msr spsr_fsxc, r2
+
+ stcopr r4, SCR
+ isb
+#else
+ ldm r1!, {r4-r12}
+ msr sp_usr, r4
+ msr lr_usr, r5
+ msr spsr_irq, r6
+ msr sp_irq, r7
+ msr lr_irq, r8
+ msr spsr_fiq, r9
+ msr sp_fiq, r10
+ msr lr_fiq, r11
+ msr spsr_svc, r12
+
+ ldm r1!, {r4-r12}
+ msr sp_svc, r4
+ msr lr_svc, r5
+ msr spsr_abt, r6
+ msr sp_abt, r7
+ msr lr_abt, r8
+ msr spsr_und, r9
+ msr sp_und, r10
+ msr lr_und, r11
+ /*
+ * Use the `_fsxc` suffix explicitly to instruct the assembler
+ * to update all the 32 bits of SPSR. Else, by default, the
+ * assembler assumes `_fc` suffix which only modifies
+ * f->[31:24] and c->[7:0] bits of SPSR.
+ */
+ msr spsr_fsxc, r12
+#endif
+
+ /* Restore the LR */
+ ldr lr, [r0, #SMC_CTX_LR_MON]
+
+ /* Restore the rest of the general purpose registers */
+ ldm r0, {r0-r12}
+ eret
+ .endm
+
+#endif /* __SMCCC_MACROS_S__ */
diff --git a/include/lib/aarch64/smcc_helpers.h b/include/lib/aarch64/smcc_helpers.h
index 62294d0..11300b7 100644
--- a/include/lib/aarch64/smcc_helpers.h
+++ b/include/lib/aarch64/smcc_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,84 +7,8 @@
#ifndef __SMCC_HELPERS_H__
#define __SMCC_HELPERS_H__
-#include <smcc.h>
+#if !ERROR_DEPRECATED
+#include <smccc_helpers.h>
+#endif
-#ifndef __ASSEMBLY__
-#include <context.h>
-
-/* Convenience macros to return from SMC handler */
-#define SMC_RET0(_h) { \
- return (uint64_t) (_h); \
-}
-#define SMC_RET1(_h, _x0) { \
- write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \
- SMC_RET0(_h); \
-}
-#define SMC_RET2(_h, _x0, _x1) { \
- write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X1), (_x1)); \
- SMC_RET1(_h, (_x0)); \
-}
-#define SMC_RET3(_h, _x0, _x1, _x2) { \
- write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \
- SMC_RET2(_h, (_x0), (_x1)); \
-}
-#define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \
- write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X3), (_x3)); \
- SMC_RET3(_h, (_x0), (_x1), (_x2)); \
-}
-#define SMC_RET5(_h, _x0, _x1, _x2, _x3, _x4) { \
- write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \
- SMC_RET4(_h, (_x0), (_x1), (_x2), (_x3)); \
-}
-#define SMC_RET6(_h, _x0, _x1, _x2, _x3, _x4, _x5) { \
- write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \
- SMC_RET5(_h, (_x0), (_x1), (_x2), (_x3), (_x4)); \
-}
-#define SMC_RET7(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6) { \
- write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X6), (_x6)); \
- SMC_RET6(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5)); \
-}
-#define SMC_RET8(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6, _x7) { \
- write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X7), (_x7)); \
- SMC_RET7(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5), (_x6)); \
-}
-
-/*
- * Convenience macros to access general purpose registers using handle provided
- * to SMC handler. These take the offset values defined in context.h
- */
-#define SMC_GET_GP(_h, _g) \
- read_ctx_reg((get_gpregs_ctx(_h)), (_g))
-#define SMC_SET_GP(_h, _g, _v) \
- write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v))
-
-/*
- * Convenience macros to access EL3 context registers using handle provided to
- * SMC handler. These take the offset values defined in context.h
- */
-#define SMC_GET_EL3(_h, _e) \
- read_ctx_reg((get_el3state_ctx(_h)), (_e))
-#define SMC_SET_EL3(_h, _e, _v) \
- write_ctx_reg((get_el3state_ctx(_h)), (_e), (_v))
-
-/* Return a UUID in the SMC return registers */
-#define SMC_UUID_RET(_h, _uuid) \
- SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \
- ((const uint32_t *) &(_uuid))[1], \
- ((const uint32_t *) &(_uuid))[2], \
- ((const uint32_t *) &(_uuid))[3])
-
-/*
- * Helper macro to retrieve the SMC parameters from cpu_context_t.
- */
-#define get_smc_params_from_ctx(_hdl, _x1, _x2, _x3, _x4) \
- do { \
- const gp_regs_t *regs = get_gpregs_ctx(_hdl); \
- _x1 = read_ctx_reg(regs, CTX_GPREG_X1); \
- _x2 = read_ctx_reg(regs, CTX_GPREG_X2); \
- _x3 = read_ctx_reg(regs, CTX_GPREG_X3); \
- _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \
- } while (0)
-
-#endif /*__ASSEMBLY__*/
#endif /* __SMCC_HELPERS_H__ */
diff --git a/include/lib/aarch64/smccc_helpers.h b/include/lib/aarch64/smccc_helpers.h
new file mode 100644
index 0000000..1b33a0d
--- /dev/null
+++ b/include/lib/aarch64/smccc_helpers.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SMCCC_HELPERS_H__
+#define __SMCCC_HELPERS_H__
+
+#include <smccc.h>
+
+#ifndef __ASSEMBLY__
+#include <context.h>
+
+/* Convenience macros to return from SMC handler */
+#define SMC_RET0(_h) { \
+ return (uint64_t) (_h); \
+}
+#define SMC_RET1(_h, _x0) { \
+ write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \
+ SMC_RET0(_h); \
+}
+#define SMC_RET2(_h, _x0, _x1) { \
+ write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X1), (_x1)); \
+ SMC_RET1(_h, (_x0)); \
+}
+#define SMC_RET3(_h, _x0, _x1, _x2) { \
+ write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \
+ SMC_RET2(_h, (_x0), (_x1)); \
+}
+#define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \
+ write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X3), (_x3)); \
+ SMC_RET3(_h, (_x0), (_x1), (_x2)); \
+}
+#define SMC_RET5(_h, _x0, _x1, _x2, _x3, _x4) { \
+ write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \
+ SMC_RET4(_h, (_x0), (_x1), (_x2), (_x3)); \
+}
+#define SMC_RET6(_h, _x0, _x1, _x2, _x3, _x4, _x5) { \
+ write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \
+ SMC_RET5(_h, (_x0), (_x1), (_x2), (_x3), (_x4)); \
+}
+#define SMC_RET7(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6) { \
+ write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X6), (_x6)); \
+ SMC_RET6(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5)); \
+}
+#define SMC_RET8(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6, _x7) { \
+ write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X7), (_x7)); \
+ SMC_RET7(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5), (_x6)); \
+}
+
+/*
+ * Convenience macros to access general purpose registers using handle provided
+ * to SMC handler. These take the offset values defined in context.h
+ */
+#define SMC_GET_GP(_h, _g) \
+ read_ctx_reg((get_gpregs_ctx(_h)), (_g))
+#define SMC_SET_GP(_h, _g, _v) \
+ write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v))
+
+/*
+ * Convenience macros to access EL3 context registers using handle provided to
+ * SMC handler. These take the offset values defined in context.h
+ */
+#define SMC_GET_EL3(_h, _e) \
+ read_ctx_reg((get_el3state_ctx(_h)), (_e))
+#define SMC_SET_EL3(_h, _e, _v) \
+ write_ctx_reg((get_el3state_ctx(_h)), (_e), (_v))
+
+/* Return a UUID in the SMC return registers */
+#define SMC_UUID_RET(_h, _uuid) \
+ SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \
+ ((const uint32_t *) &(_uuid))[1], \
+ ((const uint32_t *) &(_uuid))[2], \
+ ((const uint32_t *) &(_uuid))[3])
+
+/*
+ * Helper macro to retrieve the SMC parameters from cpu_context_t.
+ */
+#define get_smc_params_from_ctx(_hdl, _x1, _x2, _x3, _x4) \
+ do { \
+ const gp_regs_t *regs = get_gpregs_ctx(_hdl); \
+ _x1 = read_ctx_reg(regs, CTX_GPREG_X1); \
+ _x2 = read_ctx_reg(regs, CTX_GPREG_X2); \
+ _x3 = read_ctx_reg(regs, CTX_GPREG_X3); \
+ _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \
+ } while (0)
+
+#endif /*__ASSEMBLY__*/
+
+#endif /* __SMCCC_HELPERS_H__ */
diff --git a/include/lib/smcc.h b/include/lib/smcc.h
index 0a2d927..ed1da2c 100644
--- a/include/lib/smcc.h
+++ b/include/lib/smcc.h
@@ -7,103 +7,8 @@
#ifndef __SMCC_H__
#define __SMCC_H__
-#include <utils_def.h>
-
-/*******************************************************************************
- * Bit definitions inside the function id as per the SMC calling convention
- ******************************************************************************/
-#define FUNCID_TYPE_SHIFT U(31)
-#define FUNCID_CC_SHIFT U(30)
-#define FUNCID_OEN_SHIFT U(24)
-#define FUNCID_NUM_SHIFT U(0)
-
-#define FUNCID_TYPE_MASK U(0x1)
-#define FUNCID_CC_MASK U(0x1)
-#define FUNCID_OEN_MASK U(0x3f)
-#define FUNCID_NUM_MASK U(0xffff)
-
-#define FUNCID_TYPE_WIDTH U(1)
-#define FUNCID_CC_WIDTH U(1)
-#define FUNCID_OEN_WIDTH U(6)
-#define FUNCID_NUM_WIDTH U(16)
-
-#define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \
- FUNCID_CC_MASK)
-#define GET_SMC_TYPE(id) ((id >> FUNCID_TYPE_SHIFT) & \
- FUNCID_TYPE_MASK)
-
-#define SMC_64 U(1)
-#define SMC_32 U(0)
-#define SMC_OK U(0)
-#define SMC_UNK -1
-#define SMC_TYPE_FAST ULL(1)
#if !ERROR_DEPRECATED
-#define SMC_TYPE_STD ULL(0)
+#include <smccc.h>
#endif
-#define SMC_TYPE_YIELD U(0)
-#define SMC_PREEMPTED -2
-/*******************************************************************************
- * Owning entity number definitions inside the function id as per the SMC
- * calling convention
- ******************************************************************************/
-#define OEN_ARM_START U(0)
-#define OEN_ARM_END U(0)
-#define OEN_CPU_START U(1)
-#define OEN_CPU_END U(1)
-#define OEN_SIP_START U(2)
-#define OEN_SIP_END U(2)
-#define OEN_OEM_START U(3)
-#define OEN_OEM_END U(3)
-#define OEN_STD_START U(4) /* Standard Service Calls */
-#define OEN_STD_END U(4)
-#define OEN_TAP_START U(48) /* Trusted Applications */
-#define OEN_TAP_END U(49)
-#define OEN_TOS_START U(50) /* Trusted OS */
-#define OEN_TOS_END U(63)
-#define OEN_LIMIT U(64)
-#ifndef __ASSEMBLY__
-
-#include <cassert.h>
-#include <stdint.h>
-
-#define SMCCC_MAJOR_VERSION U(1)
-#define SMCCC_MINOR_VERSION U(1)
-
-#define MAKE_SMCCC_VERSION(_major, _minor) (((_major) << 16) | (_minor))
-
-/* Various flags passed to SMC handlers */
-#define SMC_FROM_SECURE (U(0) << 0)
-#define SMC_FROM_NON_SECURE (U(1) << 0)
-
-#define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE))
-#define is_caller_secure(_f) (!(is_caller_non_secure(_f)))
-
-/* The macro below is used to identify a Standard Service SMC call */
-#define is_std_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \
- FUNCID_OEN_MASK) == OEN_STD_START)
-
-/* The macro below is used to identify a Arm Architectural Service SMC call */
-#define is_arm_arch_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \
- FUNCID_OEN_MASK) == OEN_ARM_START)
-
-/* The macro below is used to identify a valid Fast SMC call */
-#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & U(0xff))) && \
- (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST))
-
-/*
- * Macro to define UUID for services. Apart from defining and initializing a
- * uuid_t structure, this macro verifies that the first word of the defined UUID
- * does not equal SMC_UNK. This is to ensure that the caller won't mistake the
- * returned UUID in x0 for an invalid SMC error return
- */
-#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \
- _n0, _n1, _n2, _n3, _n4, _n5) \
- CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
- static const uuid_t _name = { \
- _tl, _tm, _th, _cl, _ch, \
- { _n0, _n1, _n2, _n3, _n4, _n5 } \
- }
-
-#endif /*__ASSEMBLY__*/
#endif /* __SMCC_H__ */
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
new file mode 100644
index 0000000..d683420
--- /dev/null
+++ b/include/lib/smccc.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SMCCC_H__
+#define __SMCCC_H__
+
+#include <utils_def.h>
+
+/*******************************************************************************
+ * Bit definitions inside the function id as per the SMC calling convention
+ ******************************************************************************/
+#define FUNCID_TYPE_SHIFT U(31)
+#define FUNCID_CC_SHIFT U(30)
+#define FUNCID_OEN_SHIFT U(24)
+#define FUNCID_NUM_SHIFT U(0)
+
+#define FUNCID_TYPE_MASK U(0x1)
+#define FUNCID_CC_MASK U(0x1)
+#define FUNCID_OEN_MASK U(0x3f)
+#define FUNCID_NUM_MASK U(0xffff)
+
+#define FUNCID_TYPE_WIDTH U(1)
+#define FUNCID_CC_WIDTH U(1)
+#define FUNCID_OEN_WIDTH U(6)
+#define FUNCID_NUM_WIDTH U(16)
+
+#define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \
+ FUNCID_CC_MASK)
+#define GET_SMC_TYPE(id) ((id >> FUNCID_TYPE_SHIFT) & \
+ FUNCID_TYPE_MASK)
+
+#define SMC_64 U(1)
+#define SMC_32 U(0)
+#define SMC_OK U(0)
+#define SMC_UNK -1
+#define SMC_TYPE_FAST ULL(1)
+#if !ERROR_DEPRECATED
+#define SMC_TYPE_STD ULL(0)
+#endif
+#define SMC_TYPE_YIELD U(0)
+#define SMC_PREEMPTED -2
+/*******************************************************************************
+ * Owning entity number definitions inside the function id as per the SMC
+ * calling convention
+ ******************************************************************************/
+#define OEN_ARM_START U(0)
+#define OEN_ARM_END U(0)
+#define OEN_CPU_START U(1)
+#define OEN_CPU_END U(1)
+#define OEN_SIP_START U(2)
+#define OEN_SIP_END U(2)
+#define OEN_OEM_START U(3)
+#define OEN_OEM_END U(3)
+#define OEN_STD_START U(4) /* Standard Service Calls */
+#define OEN_STD_END U(4)
+#define OEN_TAP_START U(48) /* Trusted Applications */
+#define OEN_TAP_END U(49)
+#define OEN_TOS_START U(50) /* Trusted OS */
+#define OEN_TOS_END U(63)
+#define OEN_LIMIT U(64)
+
+#ifndef __ASSEMBLY__
+
+#include <cassert.h>
+#include <stdint.h>
+
+#define SMCCC_MAJOR_VERSION U(1)
+#define SMCCC_MINOR_VERSION U(1)
+
+#define MAKE_SMCCC_VERSION(_major, _minor) (((_major) << 16) | (_minor))
+
+/* Various flags passed to SMC handlers */
+#define SMC_FROM_SECURE (U(0) << 0)
+#define SMC_FROM_NON_SECURE (U(1) << 0)
+
+#define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE))
+#define is_caller_secure(_f) (!(is_caller_non_secure(_f)))
+
+/* The macro below is used to identify a Standard Service SMC call */
+#define is_std_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \
+ FUNCID_OEN_MASK) == OEN_STD_START)
+
+/* The macro below is used to identify a Arm Architectural Service SMC call */
+#define is_arm_arch_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \
+ FUNCID_OEN_MASK) == OEN_ARM_START)
+
+/* The macro below is used to identify a valid Fast SMC call */
+#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & U(0xff))) && \
+ (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST))
+
+/*
+ * Macro to define UUID for services. Apart from defining and initializing a
+ * uuid_t structure, this macro verifies that the first word of the defined UUID
+ * does not equal SMC_UNK. This is to ensure that the caller won't mistake the
+ * returned UUID in x0 for an invalid SMC error return
+ */
+#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \
+ _n0, _n1, _n2, _n3, _n4, _n5) \
+ CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
+ static const uuid_t _name = { \
+ _tl, _tm, _th, _cl, _ch, \
+ { _n0, _n1, _n2, _n3, _n4, _n5 } \
+ }
+
+#endif /*__ASSEMBLY__*/
+#endif /* __SMCCC_H__ */
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 76e440e..c784c22 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,7 +13,7 @@
#include <context_mgmt.h>
#include <platform.h>
#include <platform_def.h>
-#include <smcc_helpers.h>
+#include <smccc_helpers.h>
#include <string.h>
#include <utils.h>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index c6c2249..2608d1f 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,7 +15,7 @@
#include <platform.h>
#include <platform_def.h>
#include <pubsub_events.h>
-#include <smcc_helpers.h>
+#include <smccc_helpers.h>
#include <spe.h>
#include <string.h>
#include <sve.h>
diff --git a/lib/pmf/pmf_smc.c b/lib/pmf/pmf_smc.c
index 248c1fa..5cf193e 100644
--- a/lib/pmf/pmf_smc.c
+++ b/lib/pmf/pmf_smc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,7 @@
#include <debug.h>
#include <platform.h>
#include <pmf.h>
-#include <smcc_helpers.h>
+#include <smccc_helpers.h>
/*
* This function is responsible for handling all PMF SMC calls.
diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c
index 88cf5cb..d25d177 100644
--- a/lib/psci/psci_main.c
+++ b/lib/psci/psci_main.c
@@ -12,7 +12,7 @@
#include <platform.h>
#include <pmf.h>
#include <runtime_instr.h>
-#include <smcc.h>
+#include <smccc.h>
#include <string.h>
#include "psci_private.h"
diff --git a/lib/stdlib/puts.c b/lib/stdlib/puts.c
index 693a6bf..284cf8c 100644
--- a/lib/stdlib/puts.c
+++ b/lib/stdlib/puts.c
@@ -9,23 +9,17 @@
int puts(const char *s)
{
int count = 0;
- while(*s)
- {
- if (putchar(*s++) != EOF) {
- count++;
- } else {
- count = EOF;
- break;
- }
+ while(*s) {
+ if (putchar(*s++) == EOF)
+ return EOF;
+ count++;
}
/* According to the puts(3) manpage, the function should write a
* trailing newline.
*/
- if ((count != EOF) && (putchar('\n') != EOF))
- count++;
- else
- count = EOF;
+ if (putchar('\n') == EOF)
+ return EOF;
- return count;
+ return count + 1;
}
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index a8650be..cac9dfc 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -199,7 +199,7 @@
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
$(eval IMAGE := IMAGE_BL$(call uppercase,$(3)))
-$(OBJ): $(2) | bl$(3)_dirs
+$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
@echo " CC $$<"
$$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@
@@ -218,7 +218,7 @@
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
$(eval IMAGE := IMAGE_BL$(call uppercase,$(3)))
-$(OBJ): $(2) | bl$(3)_dirs
+$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
@echo " AS $$<"
$$(Q)$$(AS) $$(ASFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@
@@ -235,7 +235,7 @@
$(eval DEP := $(1).d)
-$(1): $(2) | bl$(3)_dirs
+$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
@echo " PP $$<"
$$(Q)$$(CPP) $$(CPPFLAGS) -P -D__ASSEMBLY__ -D__LINKER__ $(MAKE_DEP) -o $$@ $$<
@@ -374,7 +374,7 @@
$(eval DOBJ := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2))))
$(eval DEP := $(patsubst %.dtb,%.d,$(DOBJ)))
-$(DOBJ): $(2) | fdt_dirs
+$(DOBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | fdt_dirs
@echo " DTC $$<"
$$(Q)$$(DTC) $$(DTC_FLAGS) -d $(DEP) -o $$@ $$<
diff --git a/make_helpers/plat_helpers.mk b/make_helpers/plat_helpers.mk
index a2f383a..a7ae9a2 100644
--- a/make_helpers/plat_helpers.mk
+++ b/make_helpers/plat_helpers.mk
@@ -15,14 +15,14 @@
$(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform")
endif
- # PLATFORM_ROOT can be overridden for when building tools directly
- PLATFORM_ROOT ?= plat/
+ # TF_PLATFORM_ROOT can be overridden for when building tools directly
+ TF_PLATFORM_ROOT ?= plat/
PLAT_MAKEFILE := platform.mk
# Generate the platforms list by recursively searching for all directories
# under /plat containing a PLAT_MAKEFILE. Append each platform with a `|`
# char and strip out the final '|'.
- ALL_PLATFORM_MK_FILES := $(call rwildcard,${PLATFORM_ROOT},${PLAT_MAKEFILE})
+ ALL_PLATFORM_MK_FILES := $(call rwildcard,${TF_PLATFORM_ROOT},${PLAT_MAKEFILE})
ALL_PLATFORM_DIRS := $(patsubst %/,%,$(dir ${ALL_PLATFORM_MK_FILES}))
ALL_PLATFORMS := $(sort $(notdir ${ALL_PLATFORM_DIRS}))
diff --git a/plat/arm/board/fvp/aarch64/fvp_helpers.S b/plat/arm/board/fvp/aarch64/fvp_helpers.S
index 6ea4585..88fcdb1 100644
--- a/plat/arm/board/fvp/aarch64/fvp_helpers.S
+++ b/plat/arm/board/fvp/aarch64/fvp_helpers.S
@@ -178,19 +178,22 @@
ret
endfunc plat_is_my_cpu_primary
- /* -----------------------------------------------------
+ /* ---------------------------------------------------------------------
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
*
* Function to calculate the core position on FVP.
*
- * (ClusterId * FVP_MAX_CPUS_PER_CLUSTER) +
+ * (ClusterId * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) +
* (CPUId * FVP_MAX_PE_PER_CPU) +
* ThreadId
- * -----------------------------------------------------
+ *
+ * which can be simplified as:
+ *
+ * ((ClusterId * FVP_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_MAX_PE_PER_CPU)
+ * + ThreadId
+ * ---------------------------------------------------------------------
*/
func plat_arm_calc_core_pos
- mov x3, x0
-
/*
* Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
* look as if in a multi-threaded implementation.
@@ -205,9 +208,9 @@
ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/* Compute linear position */
- mov x4, #FVP_MAX_PE_PER_CPU
- madd x0, x1, x4, x0
- mov x5, #FVP_MAX_CPUS_PER_CLUSTER
- madd x0, x2, x5, x0
+ mov x4, #FVP_MAX_CPUS_PER_CLUSTER
+ madd x1, x2, x4, x1
+ mov x5, #FVP_MAX_PE_PER_CPU
+ madd x0, x1, x5, x0
ret
endfunc plat_arm_calc_core_pos
diff --git a/plat/arm/common/execution_state_switch.c b/plat/arm/common/execution_state_switch.c
index 8499db0..22d552a 100644
--- a/plat/arm/common/execution_state_switch.c
+++ b/plat/arm/common/execution_state_switch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,7 @@
#include <context_mgmt.h>
#include <plat_arm.h>
#include <psci.h>
-#include <smcc_helpers.h>
+#include <smccc_helpers.h>
#include <string.h>
#include <utils.h>
diff --git a/plat/nvidia/tegra/soc/t186/plat_smmu.c b/plat/nvidia/tegra/soc/t186/plat_smmu.c
index 4a8e1be..ead4c22 100644
--- a/plat/nvidia/tegra/soc/t186/plat_smmu.c
+++ b/plat/nvidia/tegra/soc/t186/plat_smmu.c
@@ -1,23 +1,7 @@
/*
- * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
#include <bl_common.h>
diff --git a/plat/qemu/aarch64/plat_helpers.S b/plat/qemu/aarch64/plat_helpers.S
index ed55379..ca5eec6 100644
--- a/plat/qemu/aarch64/plat_helpers.S
+++ b/plat/qemu/aarch64/plat_helpers.S
@@ -14,12 +14,13 @@
.globl platform_mem_init
.globl plat_qemu_calc_core_pos
.globl plat_crash_console_init
+#if MULTI_CONSOLE_API
.globl plat_crash_console_putc
+#endif /* MULTI_CONSOLE_API */
.globl plat_secondary_cold_boot_setup
.globl plat_get_my_entrypoint
.globl plat_is_my_cpu_primary
-
func plat_my_core_pos
mrs x0, mpidr_el1
b plat_qemu_calc_core_pos
@@ -96,10 +97,7 @@
* ---------------------------------------------
*/
func plat_crash_console_init
- mov_imm x0, PLAT_QEMU_CRASH_UART_BASE
- mov_imm x1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ
- mov_imm x2, PLAT_QEMU_CONSOLE_BAUDRATE
- b console_core_init
+ b qemu_crash_console_init
endfunc plat_crash_console_init
/* ---------------------------------------------
@@ -109,9 +107,10 @@
* Clobber list : x1, x2
* ---------------------------------------------
*/
+#if !MULTI_CONSOLE_API
func plat_crash_console_putc
mov_imm x1, PLAT_QEMU_CRASH_UART_BASE
b console_core_putc
endfunc plat_crash_console_putc
-
+#endif /* MULTI_CONSOLE_API */
diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index 5bfd48a..a9fbcd7 100644
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -47,8 +47,9 @@
$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
-PLAT_BL_COMMON_SOURCES := plat/qemu/qemu_common.c \
- drivers/arm/pl011/${ARCH}/pl011_console.S
+PLAT_BL_COMMON_SOURCES := plat/qemu/qemu_common.c \
+ plat/qemu/qemu_console.c \
+ drivers/arm/pl011/${ARCH}/pl011_console.S \
ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \
@@ -168,6 +169,7 @@
endif
SEPARATE_CODE_AND_RODATA := 1
+MULTI_CONSOLE_API := 1
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c
index 3f617e2..556aae5 100644
--- a/plat/qemu/qemu_bl1_setup.c
+++ b/plat/qemu/qemu_bl1_setup.c
@@ -8,7 +8,6 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
-#include <console.h>
#include <platform_def.h>
#include "qemu_private.h"
@@ -27,8 +26,7 @@
void bl1_early_platform_setup(void)
{
/* Initialize the console to provide early debug support */
- console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
- PLAT_QEMU_CONSOLE_BAUDRATE);
+ qemu_console_init();
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL_RAM_BASE;
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index 987c602..7650873 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -6,7 +6,6 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
-#include <console.h>
#include <debug.h>
#include <desc_image_load.h>
#include <optee_utils.h>
@@ -123,8 +122,7 @@
void bl2_early_platform_setup(meminfo_t *mem_layout)
{
/* Initialize the console to provide early debug support */
- console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
- PLAT_QEMU_CONSOLE_BAUDRATE);
+ qemu_console_init();
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c
index 6ded929..1e8b2ec 100644
--- a/plat/qemu/qemu_bl31_setup.c
+++ b/plat/qemu/qemu_bl31_setup.c
@@ -6,7 +6,6 @@
#include <assert.h>
#include <bl_common.h>
-#include <console.h>
#include <gic_common.h>
#include <gicv2.h>
#include <platform_def.h>
@@ -45,8 +44,7 @@
#endif
{
/* Initialize the console to provide early debug support */
- console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
- PLAT_QEMU_CONSOLE_BAUDRATE);
+ qemu_console_init();
#if LOAD_IMAGE_V2
/*
diff --git a/plat/qemu/qemu_console.c b/plat/qemu/qemu_console.c
new file mode 100644
index 0000000..9c02957
--- /dev/null
+++ b/plat/qemu/qemu_console.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <console.h>
+#include <pl011.h>
+#include <platform_def.h>
+
+static console_pl011_t console;
+static console_pl011_t crash_console;
+
+void qemu_console_init(void)
+{
+#if MULTI_CONSOLE_API
+ (void)console_pl011_register(PLAT_QEMU_BOOT_UART_BASE,
+ PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
+ PLAT_QEMU_CONSOLE_BAUDRATE, &console);
+#else
+ console_init(PLAT_QEMU_BOOT_UART_BASE,
+ PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
+ PLAT_QEMU_CONSOLE_BAUDRATE);
+#endif /* MULTI_CONSOLE_API */
+}
+
+void qemu_crash_console_init(void)
+{
+#if MULTI_CONSOLE_API
+ (void)console_pl011_register(PLAT_QEMU_CRASH_UART_BASE,
+ PLAT_QEMU_CRASH_UART_CLK_IN_HZ,
+ PLAT_QEMU_CONSOLE_BAUDRATE, &crash_console);
+#else
+ console_core_init(PLAT_QEMU_CRASH_UART_BASE,
+ PLAT_QEMU_CRASH_UART_CLK_IN_HZ,
+ PLAT_QEMU_CONSOLE_BAUDRATE);
+#endif /* MULTI_CONSOLE_API */
+}
diff --git a/plat/qemu/qemu_private.h b/plat/qemu/qemu_private.h
index 716440f..c66d0f9 100644
--- a/plat/qemu/qemu_private.h
+++ b/plat/qemu/qemu_private.h
@@ -34,4 +34,7 @@
int dt_add_psci_node(void *fdt);
int dt_add_psci_cpu_enable_methods(void *fdt);
+void qemu_console_init(void);
+void qemu_crash_console_init(void);
+
#endif /*__QEMU_PRIVATE_H*/
diff --git a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c
index d0e5986..f1a5e2b 100644
--- a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c
+++ b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <cdn_dp.h>
-#include <smcc.h>
+#include <smccc.h>
#include <stdlib.h>
#include <string.h>
diff --git a/readme.rst b/readme.rst
index 63b542d..94b1e63 100644
--- a/readme.rst
+++ b/readme.rst
@@ -1,21 +1,24 @@
-Trusted Firmware-A - version 1.4
+Trusted Firmware-A - version 1.5
================================
Trusted Firmware-A (TF-A) provides a reference implementation of secure world
-software for `Armv8-A`_, including a `Secure Monitor`_ executing at Exception
-Level 3 (EL3). It implements various Arm interface standards, such as:
+software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing
+at Exception Level 3 (EL3). It implements various Arm interface standards,
+such as:
- The `Power State Coordination Interface (PSCI)`_
- Trusted Board Boot Requirements (TBBR, Arm DEN0006C-1)
- `SMC Calling Convention`_
- `System Control and Management Interface`_
+- `Software Delegated Exception Interface (SDEI)`_
-As far as possible the code is designed for reuse or porting to other Armv8-A
-model and hardware platforms.
+Where possible, the code is designed for reuse or porting to other Armv7-A and
+Armv8-A model and hardware platforms.
Arm will continue development in collaboration with interested parties to
provide a full reference implementation of Secure Monitor code and Arm standards
-to the benefit of all developers working with Armv8-A TrustZone technology.
+to the benefit of all developers working with Armv7-A and Armv8-A TrustZone
+technology.
License
-------
@@ -37,7 +40,10 @@
project under the terms of the NCSA license (also known as the University of
Illinois/NCSA Open Source License).
-This Release
+- The zlib source code is licensed under the Zlib license, which is a
+ permissive license compatible with BSD-3-Clause.
+
+This release
------------
This release provides a suitable starting point for productization of secure
@@ -93,12 +99,30 @@
recovery mode), and packaging of the various firmware images into a
Firmware Image Package (FIP).
-- Pre-integration of TBB with the Arm TrustZone CryptoCell product, to take
- advantage of its hardware Root of Trust and crypto acceleration services.
+- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
+ its hardware Root of Trust and crypto acceleration services.
+
+- Reliability, Availability, and Serviceability (RAS) functionality, including
+
+ - A Secure Partition Manager (SPM) to manage Secure Partitions in
+ Secure-EL0, which can be used to implement simple management and
+ security services.
+
+ - An SDEI dispatcher to route interrupt-based SDEI events.
+
+ - An Exception Handling Framework (EHF) that allows dispatching of EL3
+ interrupts to their registered handlers, to facilitate firmware-first
+ error handling.
+
+- A dynamic configuration framework that enables each of the firmware images
+ to be configured at runtime if required by the platform. It also enables
+ loading of a hardware configuration (for example, a kernel device tree)
+ as part of the FIP, to be passed through the firmware stages.
- Support for alternative boot flows, for example to support platforms where
the EL3 Runtime Software is loaded using other firmware or a separate
- secure system processor.
+ secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
+ at EL3.
- Support for the GCC, LLVM and Arm Compiler 6 toolchains.
@@ -113,12 +137,13 @@
r0, r1 and r2 of the `Juno Arm Development Platform`_.
Various AArch64 builds of this release have been tested on the following Arm
-`FVP`_\ s (64-bit host machine only):
+Fixed Virtual Platforms (`FVP`_) without shifted affinities, and that do not
+support threaded CPU cores (64-bit host machine only):
-NOTE: Unless otherwise stated, the FVP Version is 11.0, Build 11.0.34.
+NOTE: Unless otherwise stated, the FVP Version is 11.2 Build 11.2.33.
- ``Foundation_Platform``
-- ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.5, Build 0.8.8502)
+- ``FVP_Base_AEMv8A-AEMv8A`` (and also Version 9.0, Build 0.8.9005)
- ``FVP_Base_Cortex-A35x4``
- ``FVP_Base_Cortex-A53x4``
- ``FVP_Base_Cortex-A57x4-A53x4``
@@ -127,44 +152,56 @@
- ``FVP_Base_Cortex-A72x4``
- ``FVP_Base_Cortex-A73x4-A53x4``
- ``FVP_Base_Cortex-A73x4``
-- ``FVP_CSS_SGM-775`` (Version 11.0, Build 11.0.36)
+
+Additionally, various AArch64 builds were tested on the following Arm `FVP`_ s
+with shifted affinities, supporting threaded CPU cores (64-bit host machine
+only).
+
+- ``FVP_Base_Cortex-A55x4-A75x4`` (Version 0.0, build 0.0.4395)
+- ``FVP_Base_Cortex-A55x4`` (Version 0.0, build 0.0.4395)
+- ``FVP_Base_Cortex-A75x4`` (Version 0.0, build 0.0.4395)
+- ``FVP_Base_RevC-2xAEMv8A``
Various AArch32 builds of this release has been tested on the following Arm
-`FVP`_\ s (64-bit host machine only):
+`FVP`_\ s without shifted affinities, and that do not support threaded CPU cores
+(64-bit host machine only):
-- ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.5, Build 0.8.8502)
+- ``FVP_Base_AEMv8A-AEMv8A``
- ``FVP_Base_Cortex-A32x4``
The Foundation FVP can be downloaded free of charge. The Base FVPs can be
licensed from Arm. See the `Arm FVP website`_.
-All the above platforms have been tested with `Linaro Release 17.04`_.
+All the above platforms have been tested with `Linaro Release 17.10`_.
This release also contains the following platform support:
-- HiKey and HiKey960 boards
+- HiKey, HiKey960 and Poplar boards
- MediaTek MT6795 and MT8173 SoCs
- NVidia T132, T186 and T210 SoCs
- QEMU emulator
+- Raspberry Pi 3 board
- RockChip RK3328, RK3368 and RK3399 SoCs
- Socionext UniPhier SoC family
- Xilinx Zynq UltraScale + MPSoC
-Still to Come
+Still to come
~~~~~~~~~~~~~
- More platform support.
+- Improved dynamic configuration support.
+
- Ongoing support for new architectural features, CPUs and System IP.
-- Ongoing support for new `PSCI`_, `SCMI`_ and TBBR features.
+- Ongoing support for new Arm system architecture specifications.
- Ongoing security hardening, optimization and quality improvements.
For a full list of detailed issues in the current code, please see the `Change
Log`_ and the `GitHub issue tracker`_.
-Getting Started
+Getting started
---------------
Get the TF-A source code from `GitHub`_.
@@ -175,7 +212,7 @@
See the `Firmware Design`_ for information on how the TF-A works.
See the `Porting Guide`_ as well for information about how to use this
-software on another Armv8-A platform.
+software on another Armv7-A or Armv8-A platform.
See the `Contributing Guidelines`_ for information on how to contribute to this
project and the `Acknowledgments`_ file for a list of contributors to the
@@ -195,17 +232,19 @@
*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
-.. _Armv8-A: http://www.arm.com/products/processors/armv8-architecture.php
+.. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile
.. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
.. _Power State Coordination Interface (PSCI): PSCI_
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
.. _System Control and Management Interface: SCMI_
.. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
+.. _Software Delegated Exception Interface (SDEI): SDEI_
+.. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
.. _Arm FVP website: FVP_
.. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms
-.. _Linaro Release 17.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease17.04
+.. _Linaro Release 17.10: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease17.10
.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
.. _NVidia Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
.. _Trusty Secure OS: https://source.android.com/security/trusty
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index f75a737..83d3625 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -8,8 +8,8 @@
#include <debug.h>
#include <errata_report.h>
#include <runtime_svc.h>
-#include <smcc.h>
-#include <smcc_helpers.h>
+#include <smccc.h>
+#include <smccc_helpers.h>
#include <workaround_cve_2017_5715.h>
static int32_t smccc_version(void)
diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c
index d6e5726..97f202c 100644
--- a/services/spd/trusty/trusty.c
+++ b/services/spd/trusty/trusty.c
@@ -451,7 +451,7 @@
uint32_t spsr;
ns_ep_info = bl31_plat_get_next_image_ep_info(NON_SECURE);
- if (!ep_info) {
+ if (ns_ep_info == NULL) {
NOTICE("Trusty: non-secure image missing.\n");
return -1;
}
diff --git a/services/std_svc/spm/spm_main.c b/services/std_svc/spm/spm_main.c
index d31fad6..6c4e1f0 100644
--- a/services/std_svc/spm/spm_main.c
+++ b/services/std_svc/spm/spm_main.c
@@ -14,8 +14,8 @@
#include <platform.h>
#include <runtime_svc.h>
#include <secure_partition.h>
-#include <smcc.h>
-#include <smcc_helpers.h>
+#include <smccc.h>
+#include <smccc_helpers.h>
#include <spinlock.h>
#include <spm_svc.h>
#include <utils.h>
diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c
index eae078e..41befe5 100644
--- a/services/std_svc/std_svc_setup.c
+++ b/services/std_svc/std_svc_setup.c
@@ -12,7 +12,7 @@
#include <runtime_instr.h>
#include <runtime_svc.h>
#include <sdei.h>
-#include <smcc_helpers.h>
+#include <smccc_helpers.h>
#include <spm_svc.h>
#include <std_svc.h>
#include <stdint.h>
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index 437b692..b0994b8 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -35,7 +35,7 @@
else
PLAT_MSG := ${PLAT}
-PLATFORM_ROOT := ../../plat/
+TF_PLATFORM_ROOT := ../../plat/
include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
PLAT_INCLUDE := $(wildcard ${PLAT_DIR}include)