diff --git a/Makefile b/Makefile
index 533cb8a..18c4873 100644
--- a/Makefile
+++ b/Makefile
@@ -45,7 +45,7 @@
 # Do not check the coding style on imported library files or documentation files
 INC_LIB_DIRS_TO_CHECK	:=	$(sort $(filter-out			\
 					include/lib/libfdt		\
-					include/lib/stdlib,		\
+					include/lib/libc,		\
 					$(wildcard include/lib/*)))
 INC_DIRS_TO_CHECK	:=	$(sort $(filter-out			\
 					include/lib,			\
@@ -53,7 +53,7 @@
 LIB_DIRS_TO_CHECK	:=	$(sort $(filter-out			\
 					lib/compiler-rt			\
 					lib/libfdt%			\
-					lib/stdlib,			\
+					lib/libc,			\
 					$(wildcard lib/*)))
 ROOT_DIRS_TO_CHECK	:=	$(sort $(filter-out			\
 					lib				\
@@ -172,7 +172,7 @@
 ASFLAGS_aarch32		=	$(march32-directive)
 ASFLAGS_aarch64		=	-march=armv8-a
 
-CPPFLAGS		=	${DEFINES} ${INCLUDES} -nostdinc		\
+CPPFLAGS		=	${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc		\
 				-Wmissing-include-dirs -Werror
 ASFLAGS			+=	$(CPPFLAGS) $(ASFLAGS_$(ARCH))			\
 				-D__ASSEMBLY__ -ffreestanding 			\
@@ -198,7 +198,7 @@
 # Common sources and include directories
 ################################################################################
 include lib/compiler-rt/compiler-rt.mk
-include lib/stdlib/stdlib.mk
+include lib/libc/libc.mk
 
 BL_COMMON_SOURCES	+=	common/bl_common.c			\
 				common/tf_log.c				\
@@ -211,8 +211,7 @@
 				plat/common/plat_log_common.c		\
 				plat/common/${ARCH}/plat_common.c	\
 				plat/common/${ARCH}/platform_helpers.S	\
-				${COMPILER_RT_SRCS}			\
-				${STDLIB_SRCS}
+				${COMPILER_RT_SRCS}
 
 INCLUDES		+=	-Iinclude				\
 				-Iinclude/bl1				\
@@ -506,6 +505,9 @@
 FIPTOOLPATH		?=	tools/fiptool
 FIPTOOL			?=	${FIPTOOLPATH}/fiptool${BIN_EXT}
 
+# Variables for use with ROMLIB
+ROMLIBPATH		?=	lib/romlib
+
 ################################################################################
 # Include BL specific makefiles
 ################################################################################
@@ -574,6 +576,7 @@
 $(eval $(call assert_boolean,SPIN_ON_BL1_EXIT))
 $(eval $(call assert_boolean,TRUSTED_BOARD_BOOT))
 $(eval $(call assert_boolean,USE_COHERENT_MEM))
+$(eval $(call assert_boolean,USE_ROMLIB))
 $(eval $(call assert_boolean,USE_TBBR_DEFS))
 $(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY))
 $(eval $(call assert_boolean,BL2_AT_EL3))
@@ -626,6 +629,7 @@
 $(eval $(call add_define,SPIN_ON_BL1_EXIT))
 $(eval $(call add_define,TRUSTED_BOARD_BOOT))
 $(eval $(call add_define,USE_COHERENT_MEM))
+$(eval $(call add_define,USE_ROMLIB))
 $(eval $(call add_define,USE_TBBR_DEFS))
 $(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY))
 $(eval $(call add_define,BL2_AT_EL3))
@@ -670,6 +674,9 @@
     CPPFLAGS		+= 	-Wno-error=deprecated-declarations -Wno-error=cpp
 endif
 
+$(eval $(call MAKE_LIB_DIRS))
+$(eval $(call MAKE_LIB,c))
+
 # Expand build macros for the different images
 ifeq (${NEED_BL1},yes)
 $(eval $(call MAKE_BL,1))
@@ -734,6 +741,7 @@
 	$(call SHELL_REMOVE_DIR,${BUILD_PLAT})
 	${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
 	${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean
+	${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
 
 realclean distclean:
 	@echo "  REALCLEAN"
@@ -741,11 +749,12 @@
 	$(call SHELL_DELETE_ALL, ${CURDIR}/cscope.*)
 	${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
 	${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean
+	${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
 
 checkcodebase:		locate-checkpatch
 	@echo "  CHECKING STYLE"
 	@if test -d .git ; then						\
-		git ls-files | grep -E -v 'libfdt|stdlib|docs|\.md' |	\
+		git ls-files | grep -E -v 'libfdt|libc|docs|\.md' |	\
 		while read GIT_FILE ;					\
 		do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ;	\
 		done ;							\
@@ -753,7 +762,7 @@
 		 find . -type f -not -iwholename "*.git*"		\
 		 -not -iwholename "*build*"				\
 		 -not -iwholename "*libfdt*"				\
-		 -not -iwholename "*stdlib*"				\
+		 -not -iwholename "*libc*"				\
 		 -not -iwholename "*docs*"				\
 		 -not -iwholename "*.md"				\
 		 -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ;	\
@@ -819,6 +828,10 @@
 ${FIPTOOL}:
 	${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${FIPTOOLPATH}
 
+.PHONY: libraries
+romlib.bin: libraries
+	${Q}${MAKE} BUILD_PLAT=${BUILD_PLAT} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all
+
 cscope:
 	@echo "  CSCOPE"
 	${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files
diff --git a/bl1/aarch32/bl1_exceptions.S b/bl1/aarch32/bl1_exceptions.S
index 1540542..9b001a9 100644
--- a/bl1/aarch32/bl1_exceptions.S
+++ b/bl1/aarch32/bl1_exceptions.S
@@ -116,7 +116,7 @@
 
 	/* Turn on the MMU */
 	mov	r0, #DISABLE_DCACHE
-	bl	enable_mmu_secure
+	bl	enable_mmu_svc_mon
 
 	/* Enable the data cache. */
 	ldcopr	r9, SCTLR
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index 41ee1a7..9a46a34 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -14,9 +14,7 @@
 				lib/el3_runtime/${ARCH}/context_mgmt.c	\
 				plat/common/plat_bl1_common.c		\
 				plat/common/${ARCH}/platform_up_stack.S \
-				${MBEDTLS_COMMON_SOURCES}		\
-				${MBEDTLS_CRYPTO_SOURCES}		\
-				${MBEDTLS_X509_SOURCES}
+				${MBEDTLS_SOURCES}
 
 ifeq (${ARCH},aarch64)
 BL1_SOURCES		+=	lib/el3_runtime/aarch64/context.S
diff --git a/bl2/bl2.mk b/bl2/bl2.mk
index a856fb7..7e33703 100644
--- a/bl2/bl2.mk
+++ b/bl2/bl2.mk
@@ -8,9 +8,7 @@
 				bl2/${ARCH}/bl2_arch_setup.c		\
 				lib/locks/exclusive/${ARCH}/spinlock.S	\
 				plat/common/${ARCH}/platform_up_stack.S	\
-				${MBEDTLS_COMMON_SOURCES}               \
-				${MBEDTLS_CRYPTO_SOURCES}		\
-				${MBEDTLS_X509_SOURCES}
+				${MBEDTLS_SOURCES}
 
 ifeq (${ARCH},aarch64)
 BL2_SOURCES		+=	common/aarch64/early_exceptions.S
diff --git a/bl2u/bl2u_main.c b/bl2u/bl2u_main.c
index a7e3fb9..b29d57e 100644
--- a/bl2u/bl2u_main.c
+++ b/bl2u/bl2u_main.c
@@ -17,6 +17,7 @@
 #include <platform_def.h>
 #include <stdint.h>
 
+
 /*******************************************************************************
  * This function is responsible to:
  * Load SCP_BL2U if platform has defined SCP_BL2U_BASE
diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c
index 81808b9..a6ee77a 100644
--- a/drivers/arm/cci/cci.c
+++ b/drivers/arm/cci/cci.c
@@ -5,6 +5,7 @@
  */
 
 #include <arch.h>
+#include <arch_helpers.h>
 #include <assert.h>
 #include <cci.h>
 #include <debug.h>
@@ -142,6 +143,12 @@
 		      SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG,
 		      DVM_EN_BIT | SNOOP_EN_BIT);
 
+	/*
+	 * Wait for the completion of the write to the Snoop Control Register
+	 * before testing the change_pending bit
+	 */
+	dsbish();
+
 	/* Wait for the dust to settle down */
 	while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
 		;
@@ -163,6 +170,12 @@
 		      SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG,
 		      ~(DVM_EN_BIT | SNOOP_EN_BIT));
 
+	/*
+	 * Wait for the completion of the write to the Snoop Control Register
+	 * before testing the change_pending bit
+	 */
+	dsbish();
+
 	/* Wait for the dust to settle down */
 	while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
 		;
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index bbe73fb..7cf6c76 100644
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -221,9 +221,10 @@
 	 * enabled. When the secondary CPU boots up, it initializes the
 	 * GICC/GICR interface with the caches disabled. Hence flush the
 	 * driver_data to ensure coherency. This is not required if the
-	 * platform has HW_ASSISTED_COHERENCY enabled.
+	 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
+	 * enabled.
 	 */
-#if !HW_ASSISTED_COHERENCY
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
 	flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data));
 	flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data));
 #endif
@@ -360,7 +361,7 @@
 	if (driver_data->target_masks[proc_num] == 0) {
 		driver_data->target_masks[proc_num] =
 			gicv2_get_cpuif_id(driver_data->gicd_base);
-#if !HW_ASSISTED_COHERENCY
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
 		/*
 		 * PEs only update their own masks. Primary updates it with
 		 * caches on. But because secondaries does it with caches off,
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 83d030a..40d14ab 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -147,9 +147,10 @@
 	 * enabled. When the secondary CPU boots up, it initializes the
 	 * GICC/GICR interface with the caches disabled. Hence flush the
 	 * driver data to ensure coherency. This is not required if the
-	 * platform has HW_ASSISTED_COHERENCY enabled.
+	 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
+	 * enabled.
 	 */
-#if !HW_ASSISTED_COHERENCY
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
 	flush_dcache_range((uintptr_t) &gicv3_driver_data,
 			sizeof(gicv3_driver_data));
 	flush_dcache_range((uintptr_t) gicv3_driver_data,
diff --git a/drivers/arm/sp805/sp805.c b/drivers/arm/sp805/sp805.c
index 98df7e2..aee9016 100644
--- a/drivers/arm/sp805/sp805.c
+++ b/drivers/arm/sp805/sp805.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,17 +10,17 @@
 
 /* Inline register access functions */
 
-static inline void sp805_write_wdog_load(uintptr_t base, unsigned long value)
+static inline void sp805_write_wdog_load(uintptr_t base, uint32_t value)
 {
 	mmio_write_32(base + SP805_WDOG_LOAD_OFF, value);
 }
 
-static inline void sp805_write_wdog_ctrl(uintptr_t base, unsigned long value)
+static inline void sp805_write_wdog_ctrl(uintptr_t base, uint32_t value)
 {
 	mmio_write_32(base + SP805_WDOG_CTR_OFF, value);
 }
 
-static inline void sp805_write_wdog_lock(uintptr_t base, unsigned long value)
+static inline void sp805_write_wdog_lock(uintptr_t base, uint32_t value)
 {
 	mmio_write_32(base + SP805_WDOG_LOCK_OFF, value);
 }
@@ -28,23 +28,23 @@
 
 /* Public API implementation */
 
-void sp805_start(uintptr_t base, unsigned long ticks)
+void sp805_start(uintptr_t base, unsigned int ticks)
 {
 	sp805_write_wdog_load(base, ticks);
 	sp805_write_wdog_ctrl(base, SP805_CTR_RESEN | SP805_CTR_INTEN);
 	/* Lock registers access */
-	sp805_write_wdog_lock(base, 0);
+	sp805_write_wdog_lock(base, 0U);
 }
 
 void sp805_stop(uintptr_t base)
 {
 	sp805_write_wdog_lock(base, WDOG_UNLOCK_KEY);
-	sp805_write_wdog_ctrl(base, 0);
+	sp805_write_wdog_ctrl(base, 0U);
 }
 
-void sp805_refresh(uintptr_t base, unsigned long ticks)
+void sp805_refresh(uintptr_t base, unsigned int ticks)
 {
 	sp805_write_wdog_lock(base, WDOG_UNLOCK_KEY);
 	sp805_write_wdog_load(base, ticks);
-	sp805_write_wdog_lock(base, 0);
+	sp805_write_wdog_lock(base, 0U);
 }
diff --git a/drivers/auth/mbedtls/mbedtls_common.c b/drivers/auth/mbedtls/mbedtls_common.c
index c048d00..64dc196 100644
--- a/drivers/auth/mbedtls/mbedtls_common.c
+++ b/drivers/auth/mbedtls/mbedtls_common.c
@@ -5,6 +5,7 @@
  */
 
 #include <debug.h>
+#include <stdlib.h>
 
 /* mbed TLS headers */
 #include <mbedtls/memory_buffer_alloc.h>
@@ -23,6 +24,12 @@
 #endif
 static unsigned char heap[MBEDTLS_HEAP_SIZE];
 
+static void cleanup(void)
+{
+	ERROR("EXIT from BL2\n");
+	panic();
+}
+
 /*
  * mbed TLS initialization function
  */
@@ -31,6 +38,9 @@
 	static int ready;
 
 	if (!ready) {
+		if (atexit(cleanup))
+			panic();
+
 		/* Initialize the mbed TLS heap */
 		mbedtls_memory_buffer_alloc_init(heap, MBEDTLS_HEAP_SIZE);
 
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index a5d19e6..71c496e 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -13,22 +13,86 @@
   $(error Error: MBEDTLS_DIR not set)
 endif
 
-INCLUDES		+=	-I${MBEDTLS_DIR}/include		\
-				-Iinclude/drivers/auth/mbedtls
+MBEDTLS_INC		=	-I${MBEDTLS_DIR}/include
+INCLUDES		+=     -Iinclude/drivers/auth/mbedtls
 
 # Specify mbed TLS configuration file
 MBEDTLS_CONFIG_FILE	:=	"<mbedtls_config.h>"
 $(eval $(call add_define,MBEDTLS_CONFIG_FILE))
 
-MBEDTLS_COMMON_SOURCES	:=	drivers/auth/mbedtls/mbedtls_common.c	\
-				$(addprefix ${MBEDTLS_DIR}/library/,	\
-				asn1parse.c 				\
-				asn1write.c 				\
-				memory_buffer_alloc.c			\
-				oid.c 					\
-				platform.c 				\
-				platform_util.c				\
-				rsa_internal.c				\
-				)
+MBEDTLS_SOURCES	+=		drivers/auth/mbedtls/mbedtls_common.c
+
+
+LIBMBEDTLS_SRCS		:= $(addprefix ${MBEDTLS_DIR}/library/,	\
+					asn1parse.c 				\
+					asn1write.c 				\
+					memory_buffer_alloc.c			\
+					oid.c 					\
+					platform.c 				\
+					platform_util.c				\
+					bignum.c				\
+					md.c					\
+					md_wrap.c				\
+					pk.c 					\
+					pk_wrap.c 				\
+					pkparse.c 				\
+					pkwrite.c 				\
+					sha256.c            			\
+					sha512.c            			\
+					ecdsa.c					\
+					ecp_curves.c				\
+					ecp.c					\
+					rsa.c					\
+					rsa_internal.c				\
+					x509.c 					\
+					x509_crt.c 				\
+					)
+
+# The platform may define the variable 'TF_MBEDTLS_KEY_ALG' to select the key
+# algorithm to use. If the variable is not defined, select it based on algorithm
+# used for key generation `KEY_ALG`. If `KEY_ALG` is not defined or is
+# defined to `rsa`/`rsa_1_5`, then set the variable to `rsa`.
+ifeq (${TF_MBEDTLS_KEY_ALG},)
+    ifeq (${KEY_ALG}, ecdsa)
+        TF_MBEDTLS_KEY_ALG		:=	ecdsa
+    else
+        TF_MBEDTLS_KEY_ALG		:=	rsa
+    endif
+endif
+
+# If MBEDTLS_KEY_ALG build flag is defined use it to set TF_MBEDTLS_KEY_ALG for
+# backward compatibility
+ifdef MBEDTLS_KEY_ALG
+    ifeq (${ERROR_DEPRECATED},1)
+        $(error "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
+    endif
+    $(warning "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
+    TF_MBEDTLS_KEY_ALG	:= ${MBEDTLS_KEY_ALG}
+endif
+
+ifeq (${HASH_ALG}, sha384)
+    TF_MBEDTLS_HASH_ALG_ID	:=	TF_MBEDTLS_SHA384
+else ifeq (${HASH_ALG}, sha512)
+   TF_MBEDTLS_HASH_ALG_ID	:=	TF_MBEDTLS_SHA512
+else
+    TF_MBEDTLS_HASH_ALG_ID	:=	TF_MBEDTLS_SHA256
+endif
+
+ifeq (${TF_MBEDTLS_KEY_ALG},ecdsa)
+    TF_MBEDTLS_KEY_ALG_ID	:=	TF_MBEDTLS_ECDSA
+else ifeq (${TF_MBEDTLS_KEY_ALG},rsa)
+    TF_MBEDTLS_KEY_ALG_ID	:=	TF_MBEDTLS_RSA
+else ifeq (${TF_MBEDTLS_KEY_ALG},rsa+ecdsa)
+    TF_MBEDTLS_KEY_ALG_ID	:=	TF_MBEDTLS_RSA_AND_ECDSA
+else
+    $(error "TF_MBEDTLS_KEY_ALG=${TF_MBEDTLS_KEY_ALG} not supported on mbed TLS")
+endif
+
+# Needs to be set to drive mbed TLS configuration correctly
+$(eval $(call add_define,TF_MBEDTLS_KEY_ALG_ID))
+$(eval $(call add_define,TF_MBEDTLS_HASH_ALG_ID))
+
+
+$(eval $(call MAKE_LIB,mbedtls))
 
 endif
diff --git a/drivers/auth/mbedtls/mbedtls_crypto.mk b/drivers/auth/mbedtls/mbedtls_crypto.mk
index 6b15e71..2a9fbbf 100644
--- a/drivers/auth/mbedtls/mbedtls_crypto.mk
+++ b/drivers/auth/mbedtls/mbedtls_crypto.mk
@@ -6,86 +6,6 @@
 
 include drivers/auth/mbedtls/mbedtls_common.mk
 
-# The platform may define the variable 'TF_MBEDTLS_KEY_ALG' to select the key
-# algorithm to use. If the variable is not defined, select it based on algorithm
-# used for key generation `KEY_ALG`. If `KEY_ALG` is not defined or is
-# defined to `rsa`/`rsa_1_5`, then set the variable to `rsa`.
-ifeq (${TF_MBEDTLS_KEY_ALG},)
-    ifeq (${KEY_ALG}, ecdsa)
-        TF_MBEDTLS_KEY_ALG		:=	ecdsa
-    else
-        TF_MBEDTLS_KEY_ALG		:=	rsa
-    endif
-endif
+MBEDTLS_SOURCES	+=		drivers/auth/mbedtls/mbedtls_crypto.c
 
-# If MBEDTLS_KEY_ALG build flag is defined use it to set TF_MBEDTLS_KEY_ALG for
-# backward compatibility
-ifdef MBEDTLS_KEY_ALG
-    ifeq (${ERROR_DEPRECATED},1)
-        $(error "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
-    endif
-    $(warning "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
-    TF_MBEDTLS_KEY_ALG	:= ${MBEDTLS_KEY_ALG}
-endif
 
-MBEDTLS_CRYPTO_SOURCES		:=	drivers/auth/mbedtls/mbedtls_crypto.c	\
-					$(addprefix ${MBEDTLS_DIR}/library/,	\
-					bignum.c				\
-					md.c					\
-					md_wrap.c				\
-					pk.c 					\
-					pk_wrap.c 				\
-					pkparse.c 				\
-					pkwrite.c 				\
-					)
-
-ifeq (${HASH_ALG}, sha384)
-    MBEDTLS_CRYPTO_SOURCES  += \
-					$(addprefix ${MBEDTLS_DIR}/library/,	\
-						sha256.c            \
-						sha512.c            \
-					)
-    TF_MBEDTLS_HASH_ALG_ID	:=	TF_MBEDTLS_SHA384
-else ifeq (${HASH_ALG}, sha512)
-    MBEDTLS_CRYPTO_SOURCES  += \
-					$(addprefix ${MBEDTLS_DIR}/library/,	\
-						sha256.c            \
-						sha512.c            \
-					)
-    TF_MBEDTLS_HASH_ALG_ID	:=	TF_MBEDTLS_SHA512
-else
-    MBEDTLS_CRYPTO_SOURCES  += \
-					$(addprefix ${MBEDTLS_DIR}/library/,	\
-						sha256.c            \
-					)
-    TF_MBEDTLS_HASH_ALG_ID	:=	TF_MBEDTLS_SHA256
-endif
-
-# Key algorithm specific files
-MBEDTLS_ECDSA_CRYPTO_SOURCES	+=	$(addprefix ${MBEDTLS_DIR}/library/,	\
-					ecdsa.c					\
-					ecp_curves.c				\
-					ecp.c					\
-					)
-
-MBEDTLS_RSA_CRYPTO_SOURCES	+=	$(addprefix ${MBEDTLS_DIR}/library/,	\
-					rsa.c					\
-					)
-
-ifeq (${TF_MBEDTLS_KEY_ALG},ecdsa)
-    MBEDTLS_CRYPTO_SOURCES	+=	$(MBEDTLS_ECDSA_CRYPTO_SOURCES)
-    TF_MBEDTLS_KEY_ALG_ID	:=	TF_MBEDTLS_ECDSA
-else ifeq (${TF_MBEDTLS_KEY_ALG},rsa)
-    MBEDTLS_CRYPTO_SOURCES	+=	$(MBEDTLS_RSA_CRYPTO_SOURCES)
-    TF_MBEDTLS_KEY_ALG_ID	:=	TF_MBEDTLS_RSA
-else ifeq (${TF_MBEDTLS_KEY_ALG},rsa+ecdsa)
-    MBEDTLS_CRYPTO_SOURCES	+=	$(MBEDTLS_ECDSA_CRYPTO_SOURCES)
-    MBEDTLS_CRYPTO_SOURCES	+=	$(MBEDTLS_RSA_CRYPTO_SOURCES)
-    TF_MBEDTLS_KEY_ALG_ID	:=	TF_MBEDTLS_RSA_AND_ECDSA
-else
-    $(error "TF_MBEDTLS_KEY_ALG=${TF_MBEDTLS_KEY_ALG} not supported on mbed TLS")
-endif
-
-# Needs to be set to drive mbed TLS configuration correctly
-$(eval $(call add_define,TF_MBEDTLS_KEY_ALG_ID))
-$(eval $(call add_define,TF_MBEDTLS_HASH_ALG_ID))
diff --git a/drivers/auth/mbedtls/mbedtls_x509.mk b/drivers/auth/mbedtls/mbedtls_x509.mk
index a6f72e6..a0557e2 100644
--- a/drivers/auth/mbedtls/mbedtls_x509.mk
+++ b/drivers/auth/mbedtls/mbedtls_x509.mk
@@ -6,8 +6,4 @@
 
 include drivers/auth/mbedtls/mbedtls_common.mk
 
-MBEDTLS_X509_SOURCES	:=	drivers/auth/mbedtls/mbedtls_x509_parser.c	\
-				$(addprefix ${MBEDTLS_DIR}/library/,		\
-				x509.c 						\
-				x509_crt.c 					\
-				)
+MBEDTLS_SOURCES	+=	drivers/auth/mbedtls/mbedtls_x509_parser.c
diff --git a/drivers/emmc/emmc.c b/drivers/emmc/emmc.c
deleted file mode 100644
index 92d1e87..0000000
--- a/drivers/emmc/emmc.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Defines a simple and generic interface to access eMMC device.
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <debug.h>
-#include <emmc.h>
-#include <errno.h>
-#include <string.h>
-#include <utils.h>
-
-static const emmc_ops_t *ops;
-static unsigned int emmc_ocr_value;
-static emmc_csd_t emmc_csd;
-static unsigned int emmc_flags;
-
-static int is_cmd23_enabled(void)
-{
-	return (!!(emmc_flags & EMMC_FLAG_CMD23));
-}
-
-static int emmc_device_state(void)
-{
-	emmc_cmd_t cmd;
-	int ret;
-
-	do {
-		zeromem(&cmd, sizeof(emmc_cmd_t));
-		cmd.cmd_idx = EMMC_CMD13;
-		cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
-		cmd.resp_type = EMMC_RESPONSE_R1;
-		ret = ops->send_cmd(&cmd);
-		assert(ret == 0);
-		assert((cmd.resp_data[0] & STATUS_SWITCH_ERROR) == 0);
-		/* Ignore improbable errors in release builds */
-		(void)ret;
-	} while ((cmd.resp_data[0] & STATUS_READY_FOR_DATA) == 0);
-	return EMMC_GET_STATE(cmd.resp_data[0]);
-}
-
-static void emmc_set_ext_csd(unsigned int ext_cmd, unsigned int value)
-{
-	emmc_cmd_t cmd;
-	int ret, state;
-
-	zeromem(&cmd, sizeof(emmc_cmd_t));
-	cmd.cmd_idx = EMMC_CMD6;
-	cmd.cmd_arg = EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) |
-		      EXTCSD_VALUE(value) | 1;
-	ret = ops->send_cmd(&cmd);
-	assert(ret == 0);
-
-	/* wait to exit PRG state */
-	do {
-		state = emmc_device_state();
-	} while (state == EMMC_STATE_PRG);
-	/* Ignore improbable errors in release builds */
-	(void)ret;
-}
-
-static void emmc_set_ios(int clk, int bus_width)
-{
-	int ret;
-
-	/* set IO speed & IO bus width */
-	if (emmc_csd.spec_vers == 4)
-		emmc_set_ext_csd(CMD_EXTCSD_BUS_WIDTH, bus_width);
-	ret = ops->set_ios(clk, bus_width);
-	assert(ret == 0);
-	/* Ignore improbable errors in release builds */
-	(void)ret;
-}
-
-static int emmc_enumerate(int clk, int bus_width)
-{
-	emmc_cmd_t cmd;
-	int ret, state;
-
-	ops->init();
-
-	/* CMD0: reset to IDLE */
-	zeromem(&cmd, sizeof(emmc_cmd_t));
-	cmd.cmd_idx = EMMC_CMD0;
-	ret = ops->send_cmd(&cmd);
-	assert(ret == 0);
-
-	while (1) {
-		/* CMD1: get OCR register */
-		zeromem(&cmd, sizeof(emmc_cmd_t));
-		cmd.cmd_idx = EMMC_CMD1;
-		cmd.cmd_arg = OCR_SECTOR_MODE | OCR_VDD_MIN_2V7 |
-			      OCR_VDD_MIN_1V7;
-		cmd.resp_type = EMMC_RESPONSE_R3;
-		ret = ops->send_cmd(&cmd);
-		assert(ret == 0);
-		emmc_ocr_value = cmd.resp_data[0];
-		if (emmc_ocr_value & OCR_POWERUP)
-			break;
-	}
-
-	/* CMD2: Card Identification */
-	zeromem(&cmd, sizeof(emmc_cmd_t));
-	cmd.cmd_idx = EMMC_CMD2;
-	cmd.resp_type = EMMC_RESPONSE_R2;
-	ret = ops->send_cmd(&cmd);
-	assert(ret == 0);
-
-	/* CMD3: Set Relative Address */
-	zeromem(&cmd, sizeof(emmc_cmd_t));
-	cmd.cmd_idx = EMMC_CMD3;
-	cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
-	cmd.resp_type = EMMC_RESPONSE_R1;
-	ret = ops->send_cmd(&cmd);
-	assert(ret == 0);
-
-	/* CMD9: CSD Register */
-	zeromem(&cmd, sizeof(emmc_cmd_t));
-	cmd.cmd_idx = EMMC_CMD9;
-	cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
-	cmd.resp_type = EMMC_RESPONSE_R2;
-	ret = ops->send_cmd(&cmd);
-	assert(ret == 0);
-	memcpy(&emmc_csd, &cmd.resp_data, sizeof(cmd.resp_data));
-
-	/* CMD7: Select Card */
-	zeromem(&cmd, sizeof(emmc_cmd_t));
-	cmd.cmd_idx = EMMC_CMD7;
-	cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
-	cmd.resp_type = EMMC_RESPONSE_R1;
-	ret = ops->send_cmd(&cmd);
-	assert(ret == 0);
-	/* wait to TRAN state */
-	do {
-		state = emmc_device_state();
-	} while (state != EMMC_STATE_TRAN);
-
-	emmc_set_ios(clk, bus_width);
-	return ret;
-}
-
-size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size)
-{
-	emmc_cmd_t cmd;
-	int ret;
-
-	assert((ops != 0) &&
-	       (ops->read != 0) &&
-	       ((buf & EMMC_BLOCK_MASK) == 0) &&
-	       ((size & EMMC_BLOCK_MASK) == 0));
-
-	inv_dcache_range(buf, size);
-	ret = ops->prepare(lba, buf, size);
-	assert(ret == 0);
-
-	if (is_cmd23_enabled()) {
-		zeromem(&cmd, sizeof(emmc_cmd_t));
-		/* set block count */
-		cmd.cmd_idx = EMMC_CMD23;
-		cmd.cmd_arg = size / EMMC_BLOCK_SIZE;
-		cmd.resp_type = EMMC_RESPONSE_R1;
-		ret = ops->send_cmd(&cmd);
-		assert(ret == 0);
-
-		zeromem(&cmd, sizeof(emmc_cmd_t));
-		cmd.cmd_idx = EMMC_CMD18;
-	} else {
-		if (size > EMMC_BLOCK_SIZE)
-			cmd.cmd_idx = EMMC_CMD18;
-		else
-			cmd.cmd_idx = EMMC_CMD17;
-	}
-	if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE)
-		cmd.cmd_arg = lba * EMMC_BLOCK_SIZE;
-	else
-		cmd.cmd_arg = lba;
-	cmd.resp_type = EMMC_RESPONSE_R1;
-	ret = ops->send_cmd(&cmd);
-	assert(ret == 0);
-
-	ret = ops->read(lba, buf, size);
-	assert(ret == 0);
-
-	/* wait buffer empty */
-	emmc_device_state();
-
-	if (is_cmd23_enabled() == 0) {
-		if (size > EMMC_BLOCK_SIZE) {
-			zeromem(&cmd, sizeof(emmc_cmd_t));
-			cmd.cmd_idx = EMMC_CMD12;
-			ret = ops->send_cmd(&cmd);
-			assert(ret == 0);
-		}
-	}
-	/* Ignore improbable errors in release builds */
-	(void)ret;
-	return size;
-}
-
-size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size)
-{
-	emmc_cmd_t cmd;
-	int ret;
-
-	assert((ops != 0) &&
-	       (ops->write != 0) &&
-	       ((buf & EMMC_BLOCK_MASK) == 0) &&
-	       ((size & EMMC_BLOCK_MASK) == 0));
-
-	clean_dcache_range(buf, size);
-	ret = ops->prepare(lba, buf, size);
-	assert(ret == 0);
-
-	if (is_cmd23_enabled()) {
-		/* set block count */
-		zeromem(&cmd, sizeof(emmc_cmd_t));
-		cmd.cmd_idx = EMMC_CMD23;
-		cmd.cmd_arg = size / EMMC_BLOCK_SIZE;
-		cmd.resp_type = EMMC_RESPONSE_R1;
-		ret = ops->send_cmd(&cmd);
-		assert(ret == 0);
-
-		zeromem(&cmd, sizeof(emmc_cmd_t));
-		cmd.cmd_idx = EMMC_CMD25;
-	} else {
-		zeromem(&cmd, sizeof(emmc_cmd_t));
-		if (size > EMMC_BLOCK_SIZE)
-			cmd.cmd_idx = EMMC_CMD25;
-		else
-			cmd.cmd_idx = EMMC_CMD24;
-	}
-	if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE)
-		cmd.cmd_arg = lba * EMMC_BLOCK_SIZE;
-	else
-		cmd.cmd_arg = lba;
-	cmd.resp_type = EMMC_RESPONSE_R1;
-	ret = ops->send_cmd(&cmd);
-	assert(ret == 0);
-
-	ret = ops->write(lba, buf, size);
-	assert(ret == 0);
-
-	/* wait buffer empty */
-	emmc_device_state();
-
-	if (is_cmd23_enabled() == 0) {
-		if (size > EMMC_BLOCK_SIZE) {
-			zeromem(&cmd, sizeof(emmc_cmd_t));
-			cmd.cmd_idx = EMMC_CMD12;
-			ret = ops->send_cmd(&cmd);
-			assert(ret == 0);
-		}
-	}
-	/* Ignore improbable errors in release builds */
-	(void)ret;
-	return size;
-}
-
-size_t emmc_erase_blocks(int lba, size_t size)
-{
-	emmc_cmd_t cmd;
-	int ret, state;
-
-	assert(ops != 0);
-	assert((size != 0) && ((size % EMMC_BLOCK_SIZE) == 0));
-
-	zeromem(&cmd, sizeof(emmc_cmd_t));
-	cmd.cmd_idx = EMMC_CMD35;
-	cmd.cmd_arg = lba;
-	cmd.resp_type = EMMC_RESPONSE_R1;
-	ret = ops->send_cmd(&cmd);
-	assert(ret == 0);
-
-	zeromem(&cmd, sizeof(emmc_cmd_t));
-	cmd.cmd_idx = EMMC_CMD36;
-	cmd.cmd_arg = lba + (size / EMMC_BLOCK_SIZE) - 1;
-	cmd.resp_type = EMMC_RESPONSE_R1;
-	ret = ops->send_cmd(&cmd);
-	assert(ret == 0);
-
-	zeromem(&cmd, sizeof(emmc_cmd_t));
-	cmd.cmd_idx = EMMC_CMD38;
-	cmd.resp_type = EMMC_RESPONSE_R1B;
-	ret = ops->send_cmd(&cmd);
-	assert(ret == 0);
-
-	/* wait to TRAN state */
-	do {
-		state = emmc_device_state();
-	} while (state != EMMC_STATE_TRAN);
-	/* Ignore improbable errors in release builds */
-	(void)ret;
-	return size;
-}
-
-static inline void emmc_rpmb_enable(void)
-{
-	emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
-			PART_CFG_BOOT_PARTITION1_ENABLE |
-			PART_CFG_PARTITION1_ACCESS);
-}
-
-static inline void emmc_rpmb_disable(void)
-{
-	emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
-			PART_CFG_BOOT_PARTITION1_ENABLE);
-}
-
-size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size)
-{
-	size_t size_read;
-
-	emmc_rpmb_enable();
-	size_read = emmc_read_blocks(lba, buf, size);
-	emmc_rpmb_disable();
-	return size_read;
-}
-
-size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size)
-{
-	size_t size_written;
-
-	emmc_rpmb_enable();
-	size_written = emmc_write_blocks(lba, buf, size);
-	emmc_rpmb_disable();
-	return size_written;
-}
-
-size_t emmc_rpmb_erase_blocks(int lba, size_t size)
-{
-	size_t size_erased;
-
-	emmc_rpmb_enable();
-	size_erased = emmc_erase_blocks(lba, size);
-	emmc_rpmb_disable();
-	return size_erased;
-}
-
-void emmc_init(const emmc_ops_t *ops_ptr, int clk, int width,
-	       unsigned int flags)
-{
-	assert((ops_ptr != 0) &&
-	       (ops_ptr->init != 0) &&
-	       (ops_ptr->send_cmd != 0) &&
-	       (ops_ptr->set_ios != 0) &&
-	       (ops_ptr->prepare != 0) &&
-	       (ops_ptr->read != 0) &&
-	       (ops_ptr->write != 0) &&
-	       (clk != 0) &&
-	       ((width == EMMC_BUS_WIDTH_1) ||
-		(width == EMMC_BUS_WIDTH_4) ||
-		(width == EMMC_BUS_WIDTH_8) ||
-		(width == EMMC_BUS_WIDTH_DDR_4) ||
-		(width == EMMC_BUS_WIDTH_DDR_8)));
-	ops = ops_ptr;
-	emmc_flags = flags;
-
-	emmc_enumerate(clk, width);
-}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 8fe3239..bf87612 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -9,6 +9,7 @@
 #include <arch_helpers.h>
 #include <assert.h>
 #include <debug.h>
+#include <delay_timer.h>
 #include <errno.h>
 #include <mmc.h>
 #include <stdbool.h>
@@ -23,7 +24,7 @@
 static const struct mmc_ops *ops;
 static unsigned int mmc_ocr_value;
 static struct mmc_csd_emmc mmc_csd;
-static unsigned char mmc_ext_csd[512] __aligned(4);
+static unsigned char mmc_ext_csd[512] __aligned(16);
 static unsigned int mmc_flags;
 static struct mmc_device_info *mmc_dev_info;
 static unsigned int rca;
@@ -220,7 +221,7 @@
 	unsigned int speed_idx;
 	unsigned int nb_blocks;
 	unsigned int freq_unit;
-	int ret;
+	int ret = 0;
 	struct mmc_csd_sd_v2 *csd_sd_v2;
 
 	switch (mmc_dev_info->mmc_dev_type) {
@@ -319,18 +320,12 @@
 
 static int sd_send_op_cond(void)
 {
-	int retries = SEND_OP_COND_MAX_RETRIES;
+	int n;
 	unsigned int resp_data[4];
 
-	do {
+	for (n = 0; n < SEND_OP_COND_MAX_RETRIES; n++) {
 		int ret;
 
-		if (retries == 0) {
-			ERROR("ACMD41 failed after %d retries\n",
-			      SEND_OP_COND_MAX_RETRIES);
-			return -EIO;
-		}
-
 		/* CMD55: Application Specific Command */
 		ret = mmc_send_cmd(MMC_CMD(55), 0, MMC_RESPONSE_R(1), NULL);
 		if (ret != 0) {
@@ -344,25 +339,29 @@
 			return ret;
 		}
 
-		retries--;
-	} while ((resp_data[0] & OCR_POWERUP) == 0U);
+		if ((resp_data[0] & OCR_POWERUP) != 0U) {
+			mmc_ocr_value = resp_data[0];
 
-	mmc_ocr_value = resp_data[0];
+			if ((mmc_ocr_value & OCR_HCS) != 0U) {
+				mmc_dev_info->mmc_dev_type = MMC_IS_SD_HC;
+			} else {
+				mmc_dev_info->mmc_dev_type = MMC_IS_SD;
+			}
 
-	if ((mmc_ocr_value & OCR_HCS) != 0U) {
-		mmc_dev_info->mmc_dev_type = MMC_IS_SD_HC;
-	} else {
-		mmc_dev_info->mmc_dev_type = MMC_IS_SD;
+			return 0;
+		}
+
+		mdelay(1);
 	}
 
-	return 0;
+	ERROR("ACMD41 failed after %d retries\n", SEND_OP_COND_MAX_RETRIES);
+
+	return -EIO;
 }
 
-static int mmc_send_op_cond(void)
+static int mmc_reset_to_idle(void)
 {
 	int ret;
-	int retries = SEND_OP_COND_MAX_RETRIES;
-	unsigned int resp_data[4];
 
 	/* CMD0: reset to IDLE */
 	ret = mmc_send_cmd(MMC_CMD(0), 0, 0, NULL);
@@ -370,14 +369,19 @@
 		return ret;
 	}
 
-	do {
-		if (retries == 0) {
-			ERROR("CMD1 failed after %d retries\n",
-			      SEND_OP_COND_MAX_RETRIES);
-			return -EIO;
-		}
+	mdelay(2);
 
-		/* CMD1: get OCR register (SEND_OP_COND) */
+	return 0;
+}
+
+static int mmc_send_op_cond(void)
+{
+	int ret, n;
+	unsigned int resp_data[4];
+
+	mmc_reset_to_idle();
+
+	for (n = 0; n < SEND_OP_COND_MAX_RETRIES; n++) {
 		ret = mmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE |
 				   OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7,
 				   MMC_RESPONSE_R(3), &resp_data[0]);
@@ -385,12 +389,17 @@
 			return ret;
 		}
 
-		retries--;
-	} while ((resp_data[0] & OCR_POWERUP) == 0U);
+		if ((resp_data[0] & OCR_POWERUP) != 0U) {
+			mmc_ocr_value = resp_data[0];
+			return 0;
+		}
 
-	mmc_ocr_value = resp_data[0];
+		mdelay(1);
+	}
 
-	return 0;
+	ERROR("CMD1 failed after %d retries\n", SEND_OP_COND_MAX_RETRIES);
+
+	return -EIO;
 }
 
 static int mmc_enumerate(unsigned int clk, unsigned int bus_width)
@@ -400,20 +409,18 @@
 
 	ops->init();
 
-	/* CMD0: reset to IDLE */
-	ret = mmc_send_cmd(MMC_CMD(0), 0, 0, NULL);
-	if (ret != 0) {
-		return ret;
-	}
+	mmc_reset_to_idle();
 
-	/* CMD8: Send Interface Condition Command */
-	ret = mmc_send_cmd(MMC_CMD(8), VHS_2_7_3_6_V | CMD8_CHECK_PATTERN,
-			   MMC_RESPONSE_R(7), &resp_data[0]);
-
-	if ((ret == 0) && ((resp_data[0] & 0xffU) == CMD8_CHECK_PATTERN)) {
-		ret = sd_send_op_cond();
-	} else {
+	if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
 		ret = mmc_send_op_cond();
+	} else {
+		/* CMD8: Send Interface Condition Command */
+		ret = mmc_send_cmd(MMC_CMD(8), VHS_2_7_3_6_V | CMD8_CHECK_PATTERN,
+				   MMC_RESPONSE_R(7), &resp_data[0]);
+
+		if ((ret == 0) && ((resp_data[0] & 0xffU) == CMD8_CHECK_PATTERN)) {
+			ret = sd_send_op_cond();
+		}
 	}
 	if (ret != 0) {
 		return ret;
@@ -466,15 +473,15 @@
 		}
 	} while (ret != MMC_STATE_TRAN);
 
-	ret = mmc_fill_device_info();
+	ret = mmc_set_ios(clk, bus_width);
 	if (ret != 0) {
 		return ret;
 	}
 
-	return mmc_set_ios(clk, bus_width);
+	return mmc_fill_device_info();
 }
 
-size_t mmc_read_blocks(unsigned int lba, uintptr_t buf, size_t size)
+size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size)
 {
 	int ret;
 	unsigned int cmd_idx, cmd_arg;
@@ -541,7 +548,7 @@
 	return size;
 }
 
-size_t mmc_write_blocks(unsigned int lba, const uintptr_t buf, size_t size)
+size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size)
 {
 	int ret;
 	unsigned int cmd_idx, cmd_arg;
@@ -608,7 +615,7 @@
 	return size;
 }
 
-size_t mmc_erase_blocks(unsigned int lba, size_t size)
+size_t mmc_erase_blocks(int lba, size_t size)
 {
 	int ret;
 
@@ -654,7 +661,7 @@
 			PART_CFG_BOOT_PARTITION1_ENABLE);
 }
 
-size_t mmc_rpmb_read_blocks(unsigned int lba, uintptr_t buf, size_t size)
+size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size)
 {
 	size_t size_read;
 
@@ -665,7 +672,7 @@
 	return size_read;
 }
 
-size_t mmc_rpmb_write_blocks(unsigned int lba, const uintptr_t buf, size_t size)
+size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size)
 {
 	size_t size_written;
 
@@ -676,7 +683,7 @@
 	return size_written;
 }
 
-size_t mmc_rpmb_erase_blocks(unsigned int lba, size_t size)
+size_t mmc_rpmb_erase_blocks(int lba, size_t size)
 {
 	size_t size_erased;
 
diff --git a/drivers/synopsys/emmc/dw_mmc.c b/drivers/synopsys/emmc/dw_mmc.c
index 156c2b4..b0b0a3f 100644
--- a/drivers/synopsys/emmc/dw_mmc.c
+++ b/drivers/synopsys/emmc/dw_mmc.c
@@ -10,8 +10,8 @@
 #include <debug.h>
 #include <delay_timer.h>
 #include <dw_mmc.h>
-#include <emmc.h>
 #include <errno.h>
+#include <mmc.h>
 #include <mmio.h>
 #include <string.h>
 
@@ -107,6 +107,8 @@
 
 #define DWMMC_8BIT_MODE			(1 << 6)
 
+#define DWMMC_ADDRESS_MASK		U(0x0f)
+
 #define TIMEOUT				100000
 
 struct dw_idmac_desc {
@@ -117,13 +119,13 @@
 };
 
 static void dw_init(void);
-static int dw_send_cmd(emmc_cmd_t *cmd);
-static int dw_set_ios(int clk, int width);
+static int dw_send_cmd(struct mmc_cmd *cmd);
+static int dw_set_ios(unsigned int clk, unsigned int width);
 static int dw_prepare(int lba, uintptr_t buf, size_t size);
 static int dw_read(int lba, uintptr_t buf, size_t size);
 static int dw_write(int lba, uintptr_t buf, size_t size);
 
-static const emmc_ops_t dw_mmc_ops = {
+static const struct mmc_ops dw_mmc_ops = {
 	.init		= dw_init,
 	.send_cmd	= dw_send_cmd,
 	.set_ios	= dw_set_ios,
@@ -187,7 +189,7 @@
 	unsigned int data;
 	uintptr_t base;
 
-	assert((dw_params.reg_base & EMMC_BLOCK_MASK) == 0);
+	assert((dw_params.reg_base & MMC_BLOCK_MASK) == 0);
 
 	base = dw_params.reg_base;
 	mmio_write_32(base + DWMMC_PWREN, 1);
@@ -203,7 +205,7 @@
 	mmio_write_32(base + DWMMC_INTMASK, 0);
 	mmio_write_32(base + DWMMC_TMOUT, ~0);
 	mmio_write_32(base + DWMMC_IDINTEN, ~0);
-	mmio_write_32(base + DWMMC_BLKSIZ, EMMC_BLOCK_SIZE);
+	mmio_write_32(base + DWMMC_BLKSIZ, MMC_BLOCK_SIZE);
 	mmio_write_32(base + DWMMC_BYTCNT, 256 * 1024);
 	mmio_write_32(base + DWMMC_DEBNCE, 0x00ffffff);
 	mmio_write_32(base + DWMMC_BMOD, BMOD_SWRESET);
@@ -215,11 +217,11 @@
 	mmio_write_32(base + DWMMC_BMOD, data);
 
 	udelay(100);
-	dw_set_clk(EMMC_BOOT_CLK_RATE);
+	dw_set_clk(MMC_BOOT_CLK_RATE);
 	udelay(100);
 }
 
-static int dw_send_cmd(emmc_cmd_t *cmd)
+static int dw_send_cmd(struct mmc_cmd *cmd)
 {
 	unsigned int op, data, err_mask;
 	uintptr_t base;
@@ -230,22 +232,22 @@
 	base = dw_params.reg_base;
 
 	switch (cmd->cmd_idx) {
-	case EMMC_CMD0:
+	case 0:
 		op = CMD_SEND_INIT;
 		break;
-	case EMMC_CMD12:
+	case 12:
 		op = CMD_STOP_ABORT_CMD;
 		break;
-	case EMMC_CMD13:
+	case 13:
 		op = CMD_WAIT_PRVDATA_COMPLETE;
 		break;
-	case EMMC_CMD8:
-	case EMMC_CMD17:
-	case EMMC_CMD18:
+	case 8:
+	case 17:
+	case 18:
 		op = CMD_DATA_TRANS_EXPECT | CMD_WAIT_PRVDATA_COMPLETE;
 		break;
-	case EMMC_CMD24:
-	case EMMC_CMD25:
+	case 24:
+	case 25:
 		op = CMD_WRITE | CMD_DATA_TRANS_EXPECT |
 		     CMD_WAIT_PRVDATA_COMPLETE;
 		break;
@@ -257,11 +259,11 @@
 	switch (cmd->resp_type) {
 	case 0:
 		break;
-	case EMMC_RESPONSE_R2:
+	case MMC_RESPONSE_R(2):
 		op |= CMD_RESP_EXPECT | CMD_CHECK_RESP_CRC |
 		      CMD_RESP_LEN;
 		break;
-	case EMMC_RESPONSE_R3:
+	case MMC_RESPONSE_R(3):
 		op |= CMD_RESP_EXPECT;
 		break;
 	default:
@@ -307,16 +309,16 @@
 	return 0;
 }
 
-static int dw_set_ios(int clk, int width)
+static int dw_set_ios(unsigned int clk, unsigned int width)
 {
 	switch (width) {
-	case EMMC_BUS_WIDTH_1:
+	case MMC_BUS_WIDTH_1:
 		mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_1BIT);
 		break;
-	case EMMC_BUS_WIDTH_4:
+	case MMC_BUS_WIDTH_4:
 		mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_4BIT);
 		break;
-	case EMMC_BUS_WIDTH_8:
+	case MMC_BUS_WIDTH_8:
 		mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_8BIT);
 		break;
 	default:
@@ -333,12 +335,14 @@
 	int desc_cnt, i, last;
 	uintptr_t base;
 
-	assert(((buf & EMMC_BLOCK_MASK) == 0) &&
-	       ((size % EMMC_BLOCK_SIZE) == 0) &&
+	assert(((buf & DWMMC_ADDRESS_MASK) == 0) &&
+	       ((size % MMC_BLOCK_SIZE) == 0) &&
 	       (dw_params.desc_size > 0) &&
-	       ((dw_params.reg_base & EMMC_BLOCK_MASK) == 0) &&
-	       ((dw_params.desc_base & EMMC_BLOCK_MASK) == 0) &&
-	       ((dw_params.desc_size & EMMC_BLOCK_MASK) == 0));
+	       ((dw_params.reg_base & MMC_BLOCK_MASK) == 0) &&
+	       ((dw_params.desc_base & MMC_BLOCK_MASK) == 0) &&
+	       ((dw_params.desc_size & MMC_BLOCK_MASK) == 0));
+
+	flush_dcache_range(buf, size);
 
 	desc_cnt = (size + DWMMC_DMA_MAX_BUFFER_SIZE - 1) /
 		   DWMMC_DMA_MAX_BUFFER_SIZE;
@@ -367,7 +371,7 @@
 	(desc + last)->des3 = 0;
 
 	mmio_write_32(base + DWMMC_DBADDR, dw_params.desc_base);
-	clean_dcache_range(dw_params.desc_base,
+	flush_dcache_range(dw_params.desc_base,
 			   desc_cnt * DWMMC_DMA_MAX_BUFFER_SIZE);
 
 	return 0;
@@ -383,19 +387,19 @@
 	return 0;
 }
 
-void dw_mmc_init(dw_mmc_params_t *params)
+void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info)
 {
 	assert((params != 0) &&
-	       ((params->reg_base & EMMC_BLOCK_MASK) == 0) &&
-	       ((params->desc_base & EMMC_BLOCK_MASK) == 0) &&
-	       ((params->desc_size & EMMC_BLOCK_MASK) == 0) &&
+	       ((params->reg_base & MMC_BLOCK_MASK) == 0) &&
+	       ((params->desc_base & MMC_BLOCK_MASK) == 0) &&
+	       ((params->desc_size & MMC_BLOCK_MASK) == 0) &&
 	       (params->desc_size > 0) &&
 	       (params->clk_rate > 0) &&
-	       ((params->bus_width == EMMC_BUS_WIDTH_1) ||
-		(params->bus_width == EMMC_BUS_WIDTH_4) ||
-		(params->bus_width == EMMC_BUS_WIDTH_8)));
+	       ((params->bus_width == MMC_BUS_WIDTH_1) ||
+		(params->bus_width == MMC_BUS_WIDTH_4) ||
+		(params->bus_width == MMC_BUS_WIDTH_8)));
 
 	memcpy(&dw_params, params, sizeof(dw_mmc_params_t));
-	emmc_init(&dw_mmc_ops, params->clk_rate, params->bus_width,
-		  params->flags);
+	mmc_init(&dw_mmc_ops, params->clk_rate, params->bus_width,
+		 params->flags, info);
 }
diff --git a/include/common/romlib.h b/include/common/romlib.h
new file mode 100644
index 0000000..81a6f5c
--- /dev/null
+++ b/include/common/romlib.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ROMLIB_H_
+
+#define ROMLIB_MAJOR   0
+#define ROMLIB_MINOR   1
+#define ROMLIB_VERSION ((ROMLIB_MAJOR << 8) | ROMLIB_MINOR)
+
+int rom_lib_init(int version);
+
+#endif
diff --git a/include/drivers/arm/sp805.h b/include/drivers/arm/sp805.h
index f00bcba..e7714a3 100644
--- a/include/drivers/arm/sp805.h
+++ b/include/drivers/arm/sp805.h
@@ -1,23 +1,25 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __SP805_H__
-#define __SP805_H__
+#ifndef SP805_H
+#define SP805_H
+
+#include <utils_def.h>
 
 /* SP805 register offset */
-#define SP805_WDOG_LOAD_OFF		0x000
-#define SP805_WDOG_CTR_OFF		0x008
-#define SP805_WDOG_LOCK_OFF		0xc00
+#define SP805_WDOG_LOAD_OFF		UL(0x000)
+#define SP805_WDOG_CTR_OFF		UL(0x008)
+#define SP805_WDOG_LOCK_OFF		UL(0xc00)
 
 /* Magic word to unlock the wd registers */
-#define WDOG_UNLOCK_KEY			0x1ACCE551
+#define WDOG_UNLOCK_KEY			U(0x1ACCE551)
 
 /* Register field definitions */
-#define SP805_CTR_RESEN			(1 << 1)
-#define SP805_CTR_INTEN			(1 << 0)
+#define SP805_CTR_RESEN			(U(1) << 1)
+#define SP805_CTR_INTEN			(U(1) << 0)
 
 #ifndef __ASSEMBLY__
 
@@ -25,10 +27,10 @@
 
 /* Public high level API */
 
-void sp805_start(uintptr_t base, unsigned long ticks);
+void sp805_start(uintptr_t base, unsigned int ticks);
 void sp805_stop(uintptr_t base);
-void sp805_refresh(uintptr_t base, unsigned long ticks);
+void sp805_refresh(uintptr_t base, unsigned int ticks);
 
 #endif /* __ASSEMBLY__ */
 
-#endif /* __SP805_H__ */
+#endif /* SP805_H */
diff --git a/include/drivers/console.h b/include/drivers/console.h
index 6e7ebbf..f9ed2e5 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -39,9 +39,9 @@
 	 * fields of the struct to 64 bits in AArch64 and 32 bits in AArch32
 	 */
 	u_register_t flags;
-	int (*putc)(int character, struct console *console);
-	int (*getc)(struct console *console);
-	int (*flush)(struct console *console);
+	int (*const putc)(int character, struct console *console);
+	int (*const getc)(struct console *console);
+	int (*const flush)(struct console *console);
 	/* Additional private driver data may follow here. */
 } console_t;
 #include <console_assertions.h> /* offset macro assertions for console_t */
diff --git a/include/drivers/emmc.h b/include/drivers/emmc.h
deleted file mode 100644
index 286c014..0000000
--- a/include/drivers/emmc.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __EMMC_H__
-#define __EMMC_H__
-
-#include <stdint.h>
-
-#define EMMC_BLOCK_SIZE			512
-#define EMMC_BLOCK_MASK			(EMMC_BLOCK_SIZE - 1)
-#define EMMC_BOOT_CLK_RATE		(400 * 1000)
-
-#define EMMC_CMD0			0
-#define EMMC_CMD1			1
-#define EMMC_CMD2			2
-#define EMMC_CMD3			3
-#define EMMC_CMD6			6
-#define EMMC_CMD7			7
-#define EMMC_CMD8			8
-#define EMMC_CMD9			9
-#define EMMC_CMD12			12
-#define EMMC_CMD13			13
-#define EMMC_CMD17			17
-#define EMMC_CMD18			18
-#define EMMC_CMD21			21
-#define EMMC_CMD23			23
-#define EMMC_CMD24			24
-#define EMMC_CMD25			25
-#define EMMC_CMD35			35
-#define EMMC_CMD36			36
-#define EMMC_CMD38			38
-
-#define OCR_POWERUP			(1 << 31)
-#define OCR_BYTE_MODE			(0 << 29)
-#define OCR_SECTOR_MODE			(2 << 29)
-#define OCR_ACCESS_MODE_MASK		(3 << 29)
-#define OCR_VDD_MIN_2V7			(0x1ff << 15)
-#define OCR_VDD_MIN_2V0			(0x7f << 8)
-#define OCR_VDD_MIN_1V7			(1 << 7)
-
-#define EMMC_RESPONSE_R1		1
-#define EMMC_RESPONSE_R1B		1
-#define EMMC_RESPONSE_R2		4
-#define EMMC_RESPONSE_R3		1
-#define EMMC_RESPONSE_R4		1
-#define EMMC_RESPONSE_R5		1
-
-#define EMMC_FIX_RCA			6	/* > 1 */
-#define RCA_SHIFT_OFFSET		16
-
-#define CMD_EXTCSD_PARTITION_CONFIG	179
-#define CMD_EXTCSD_BUS_WIDTH		183
-#define CMD_EXTCSD_HS_TIMING		185
-
-#define PART_CFG_BOOT_PARTITION1_ENABLE	(1 << 3)
-#define PART_CFG_PARTITION1_ACCESS	(1 << 0)
-
-/* values in EXT CSD register */
-#define EMMC_BUS_WIDTH_1		0
-#define EMMC_BUS_WIDTH_4		1
-#define EMMC_BUS_WIDTH_8		2
-#define EMMC_BUS_WIDTH_DDR_4		5
-#define EMMC_BUS_WIDTH_DDR_8		6
-#define EMMC_BOOT_MODE_BACKWARD		(0 << 3)
-#define EMMC_BOOT_MODE_HS_TIMING	(1 << 3)
-#define EMMC_BOOT_MODE_DDR		(2 << 3)
-
-#define EXTCSD_SET_CMD			(0 << 24)
-#define EXTCSD_SET_BITS			(1 << 24)
-#define EXTCSD_CLR_BITS			(2 << 24)
-#define EXTCSD_WRITE_BYTES		(3 << 24)
-#define EXTCSD_CMD(x)			(((x) & 0xff) << 16)
-#define EXTCSD_VALUE(x)			(((x) & 0xff) << 8)
-
-#define STATUS_CURRENT_STATE(x)		(((x) & 0xf) << 9)
-#define STATUS_READY_FOR_DATA		(1 << 8)
-#define STATUS_SWITCH_ERROR		(1 << 7)
-#define EMMC_GET_STATE(x)		(((x) >> 9) & 0xf)
-#define EMMC_STATE_IDLE			0
-#define EMMC_STATE_READY		1
-#define EMMC_STATE_IDENT		2
-#define EMMC_STATE_STBY			3
-#define EMMC_STATE_TRAN			4
-#define EMMC_STATE_DATA			5
-#define EMMC_STATE_RCV			6
-#define EMMC_STATE_PRG			7
-#define EMMC_STATE_DIS			8
-#define EMMC_STATE_BTST			9
-#define EMMC_STATE_SLP			10
-
-#define EMMC_FLAG_CMD23			(1 << 0)
-
-typedef struct emmc_cmd {
-	unsigned int	cmd_idx;
-	unsigned int	cmd_arg;
-	unsigned int	resp_type;
-	unsigned int	resp_data[4];
-} emmc_cmd_t;
-
-typedef struct emmc_ops {
-	void (*init)(void);
-	int (*send_cmd)(emmc_cmd_t *cmd);
-	int (*set_ios)(int clk, int width);
-	int (*prepare)(int lba, uintptr_t buf, size_t size);
-	int (*read)(int lba, uintptr_t buf, size_t size);
-	int (*write)(int lba, const uintptr_t buf, size_t size);
-} emmc_ops_t;
-
-typedef struct emmc_csd {
-	unsigned int 	    not_used:		1;
-	unsigned int   	    crc:			7;
-	unsigned int   	    ecc:			2;
-	unsigned int   	    file_format:		2;
-	unsigned int   	    tmp_write_protect:	1;
-	unsigned int   	    perm_write_protect:	1;
-	unsigned int   	    copy:			1;
-	unsigned int   	    file_format_grp:	1;
-
-	unsigned int 		reserved_1:		5;
-	unsigned int 		write_bl_partial:	1;
-	unsigned int 		write_bl_len:		4;
-	unsigned int 		r2w_factor:		3;
-	unsigned int 		default_ecc:		2;
-	unsigned int 		wp_grp_enable:		1;
-
-	unsigned int		wp_grp_size:		5;
-	unsigned int		erase_grp_mult:		5;
-	unsigned int		erase_grp_size:		5;
-	unsigned int		c_size_mult:		3;
-	unsigned int		vdd_w_curr_max:		3;
-	unsigned int		vdd_w_curr_min:		3;
-	unsigned int		vdd_r_curr_max:		3;
-	unsigned int		vdd_r_curr_min:		3;
-	unsigned int		c_size_low:		2;
-
-	unsigned int		c_size_high:		10;
-	unsigned int		reserved_2:		2;
-	unsigned int		dsr_imp:		1;
-	unsigned int		read_blk_misalign:	1;
-	unsigned int		write_blk_misalign:	1;
-	unsigned int		read_bl_partial:	1;
-	unsigned int		read_bl_len:		4;
-	unsigned int		ccc:			12;
-
-	unsigned int		tran_speed:		8;
-	unsigned int		nsac:			8;
-	unsigned int		taac:			8;
-	unsigned int		reserved_3:		2;
-	unsigned int		spec_vers:		4;
-	unsigned int		csd_structure:		2;
-} emmc_csd_t;
-
-size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size);
-size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size);
-size_t emmc_erase_blocks(int lba, size_t size);
-size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
-size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
-size_t emmc_rpmb_erase_blocks(int lba, size_t size);
-void emmc_init(const emmc_ops_t *ops, int clk, int bus_width,
-	       unsigned int flags);
-
-#endif	/* __EMMC_H__ */
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
index 65f4bbd..0a513bd 100644
--- a/include/drivers/mmc.h
+++ b/include/drivers/mmc.h
@@ -208,13 +208,12 @@
 	enum mmc_device_type	mmc_dev_type;	/* Type of MMC */
 };
 
-size_t mmc_read_blocks(unsigned int lba, uintptr_t buf, size_t size);
-size_t mmc_write_blocks(unsigned int lba, const uintptr_t buf, size_t size);
-size_t mmc_erase_blocks(unsigned int lba, size_t size);
-size_t mmc_rpmb_read_blocks(unsigned int lba, uintptr_t buf, size_t size);
-size_t mmc_rpmb_write_blocks(unsigned int lba, const uintptr_t buf,
-			     size_t size);
-size_t mmc_rpmb_erase_blocks(unsigned int lba, size_t size);
+size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size);
+size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size);
+size_t mmc_erase_blocks(int lba, size_t size);
+size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
+size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
+size_t mmc_rpmb_erase_blocks(int lba, size_t size);
 int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
 	     unsigned int width, unsigned int flags,
 	     struct mmc_device_info *device_info);
diff --git a/include/drivers/synopsys/dw_mmc.h b/include/drivers/synopsys/dw_mmc.h
index 4e6b348..1ec8d1d 100644
--- a/include/drivers/synopsys/dw_mmc.h
+++ b/include/drivers/synopsys/dw_mmc.h
@@ -7,6 +7,8 @@
 #ifndef __DW_MMC_H__
 #define __DW_MMC_H__
 
+#include <mmc.h>
+
 typedef struct dw_mmc_params {
 	uintptr_t	reg_base;
 	uintptr_t	desc_base;
@@ -16,6 +18,6 @@
 	unsigned int	flags;
 } dw_mmc_params_t;
 
-void dw_mmc_init(dw_mmc_params_t *params);
+void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info);
 
 #endif	/* __DW_MMC_H__ */
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h
index a536649..6f0949b 100644
--- a/include/lib/aarch32/arch.h
+++ b/include/lib/aarch32/arch.h
@@ -313,6 +313,28 @@
 #define TTBCR_T0SZ_SHIFT	U(0)
 #define TTBCR_T0SZ_MASK		U(0x7)
 
+/*
+ * HTCR definitions
+ */
+#define HTCR_RES1			((U(1) << 31) | (U(1) << 23))
+
+#define HTCR_SH0_NON_SHAREABLE		(U(0x0) << 12)
+#define HTCR_SH0_OUTER_SHAREABLE	(U(0x2) << 12)
+#define HTCR_SH0_INNER_SHAREABLE	(U(0x3) << 12)
+
+#define HTCR_RGN0_OUTER_NC	(U(0x0) << 10)
+#define HTCR_RGN0_OUTER_WBA	(U(0x1) << 10)
+#define HTCR_RGN0_OUTER_WT	(U(0x2) << 10)
+#define HTCR_RGN0_OUTER_WBNA	(U(0x3) << 10)
+
+#define HTCR_RGN0_INNER_NC	(U(0x0) << 8)
+#define HTCR_RGN0_INNER_WBA	(U(0x1) << 8)
+#define HTCR_RGN0_INNER_WT	(U(0x2) << 8)
+#define HTCR_RGN0_INNER_WBNA	(U(0x3) << 8)
+
+#define HTCR_T0SZ_SHIFT		U(0)
+#define HTCR_T0SZ_MASK		U(0x7)
+
 #define MODE_RW_SHIFT		U(0x4)
 #define MODE_RW_MASK		U(0x1)
 #define MODE_RW_32		U(0x1)
@@ -433,6 +455,7 @@
 #define TLBIMVA		p15, 0, c8, c7, 1
 #define TLBIMVAA	p15, 0, c8, c7, 3
 #define TLBIMVAAIS	p15, 0, c8, c3, 3
+#define TLBIMVAHIS	p15, 4, c8, c3, 1
 #define BPIALLIS	p15, 0, c7, c1, 6
 #define BPIALL		p15, 0, c7, c5, 6
 #define ICIALLU		p15, 0, c7, c5, 0
@@ -448,6 +471,8 @@
 #define CLIDR		p15, 1, c0, c0, 1
 #define CSSELR		p15, 2, c0, c0, 0
 #define CCSIDR		p15, 1, c0, c0, 0
+#define HTCR		p15, 4, c2, c0, 2
+#define HMAIR0		p15, 4, c10, c2, 0
 #define DBGOSDLR	p14, 0, c1, c3, 4
 
 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
@@ -487,6 +512,7 @@
 #define CNTVOFF_64	p15, 4, c14
 #define VTTBR_64	p15, 6, c2
 #define CNTPCT_64	p15, 0, c14
+#define HTTBR_64	p15, 4, c2
 
 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
 #define ICC_SGI1R_EL1_64	p15, 0, c12
diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h
index beae5d0..aa68bcb 100644
--- a/include/lib/aarch32/arch_helpers.h
+++ b/include/lib/aarch32/arch_helpers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -300,6 +300,7 @@
 DEFINE_TLBIOP_PARAM_FUNC(mva, TLBIMVA)
 DEFINE_TLBIOP_PARAM_FUNC(mvaa, TLBIMVAA)
 DEFINE_TLBIOP_PARAM_FUNC(mvaais, TLBIMVAAIS)
+DEFINE_TLBIOP_PARAM_FUNC(mvahis, TLBIMVAHIS)
 
 /*
  * BPI operation prototypes.
@@ -320,6 +321,10 @@
 #define IS_IN_SECURE() \
 	(GET_NS_BIT(read_scr()) == 0)
 
+#define IS_IN_HYP()	(GET_M32(read_cpsr()) == MODE32_hyp)
+#define IS_IN_SVC()	(GET_M32(read_cpsr()) == MODE32_svc)
+#define IS_IN_MON()	(GET_M32(read_cpsr()) == MODE32_mon)
+#define IS_IN_EL2()	IS_IN_HYP()
  /*
   * If EL3 is AArch32, then secure PL1 and monitor mode correspond to EL3
   */
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 397013e..c9619f6 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -364,7 +364,9 @@
  * TCR defintions
  */
 #define TCR_EL3_RES1		((U(1) << 31) | (U(1) << 23))
+#define TCR_EL2_RES1		((ULL(1) << 31) | (ULL(1) << 23))
 #define TCR_EL1_IPS_SHIFT	U(32)
+#define TCR_EL2_PS_SHIFT	U(16)
 #define TCR_EL3_PS_SHIFT	U(16)
 
 #define TCR_TxSZ_MIN		ULL(16)
diff --git a/include/lib/stdlib/assert.h b/include/lib/libc/assert.h
similarity index 100%
rename from include/lib/stdlib/assert.h
rename to include/lib/libc/assert.h
diff --git a/include/lib/stdlib/inttypes.h b/include/lib/libc/inttypes.h
similarity index 100%
rename from include/lib/stdlib/inttypes.h
rename to include/lib/libc/inttypes.h
diff --git a/include/lib/stdlib/machine/_inttypes.h b/include/lib/libc/machine/_inttypes.h
similarity index 100%
rename from include/lib/stdlib/machine/_inttypes.h
rename to include/lib/libc/machine/_inttypes.h
diff --git a/include/lib/stdlib/machine/_limits.h b/include/lib/libc/machine/_limits.h
similarity index 100%
rename from include/lib/stdlib/machine/_limits.h
rename to include/lib/libc/machine/_limits.h
diff --git a/include/lib/stdlib/machine/_stdint.h b/include/lib/libc/machine/_stdint.h
similarity index 100%
rename from include/lib/stdlib/machine/_stdint.h
rename to include/lib/libc/machine/_stdint.h
diff --git a/include/lib/stdlib/machine/_types.h b/include/lib/libc/machine/_types.h
similarity index 100%
rename from include/lib/stdlib/machine/_types.h
rename to include/lib/libc/machine/_types.h
diff --git a/include/lib/stdlib/machine/endian.h b/include/lib/libc/machine/endian.h
similarity index 100%
rename from include/lib/stdlib/machine/endian.h
rename to include/lib/libc/machine/endian.h
diff --git a/include/lib/libc/stdbool.h b/include/lib/libc/stdbool.h
new file mode 100644
index 0000000..e39aef7
--- /dev/null
+++ b/include/lib/libc/stdbool.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STDBOOL_H
+#define STDBOOL_H
+
+#define bool	_Bool
+
+#define true	1
+#define false	0
+
+#define __bool_true_false_are_defined	1
+
+#endif /* STDBOOL_H */
diff --git a/include/lib/stdlib/stddef.h b/include/lib/libc/stddef.h
similarity index 100%
rename from include/lib/stdlib/stddef.h
rename to include/lib/libc/stddef.h
diff --git a/include/lib/stdlib/stdio.h b/include/lib/libc/stdio.h
similarity index 100%
rename from include/lib/stdlib/stdio.h
rename to include/lib/libc/stdio.h
diff --git a/include/lib/stdlib/stdlib.h b/include/lib/libc/stdlib.h
similarity index 100%
rename from include/lib/stdlib/stdlib.h
rename to include/lib/libc/stdlib.h
diff --git a/include/lib/stdlib/string.h b/include/lib/libc/string.h
similarity index 100%
rename from include/lib/stdlib/string.h
rename to include/lib/libc/string.h
diff --git a/include/lib/stdlib/strings.h b/include/lib/libc/strings.h
similarity index 100%
rename from include/lib/stdlib/strings.h
rename to include/lib/libc/strings.h
diff --git a/include/lib/stdlib/sys/_null.h b/include/lib/libc/sys/_null.h
similarity index 100%
rename from include/lib/stdlib/sys/_null.h
rename to include/lib/libc/sys/_null.h
diff --git a/include/lib/stdlib/sys/_stdint.h b/include/lib/libc/sys/_stdint.h
similarity index 100%
rename from include/lib/stdlib/sys/_stdint.h
rename to include/lib/libc/sys/_stdint.h
diff --git a/include/lib/stdlib/sys/_timespec.h b/include/lib/libc/sys/_timespec.h
similarity index 100%
rename from include/lib/stdlib/sys/_timespec.h
rename to include/lib/libc/sys/_timespec.h
diff --git a/include/lib/stdlib/sys/_types.h b/include/lib/libc/sys/_types.h
similarity index 100%
rename from include/lib/stdlib/sys/_types.h
rename to include/lib/libc/sys/_types.h
diff --git a/include/lib/stdlib/sys/cdefs.h b/include/lib/libc/sys/cdefs.h
similarity index 100%
rename from include/lib/stdlib/sys/cdefs.h
rename to include/lib/libc/sys/cdefs.h
diff --git a/include/lib/stdlib/sys/ctype.h b/include/lib/libc/sys/ctype.h
similarity index 100%
rename from include/lib/stdlib/sys/ctype.h
rename to include/lib/libc/sys/ctype.h
diff --git a/include/lib/stdlib/sys/endian.h b/include/lib/libc/sys/endian.h
similarity index 100%
rename from include/lib/stdlib/sys/endian.h
rename to include/lib/libc/sys/endian.h
diff --git a/include/lib/stdlib/sys/errno.h b/include/lib/libc/sys/errno.h
similarity index 100%
rename from include/lib/stdlib/sys/errno.h
rename to include/lib/libc/sys/errno.h
diff --git a/include/lib/stdlib/sys/limits.h b/include/lib/libc/sys/limits.h
similarity index 100%
rename from include/lib/stdlib/sys/limits.h
rename to include/lib/libc/sys/limits.h
diff --git a/include/lib/stdlib/sys/stdarg.h b/include/lib/libc/sys/stdarg.h
similarity index 100%
rename from include/lib/stdlib/sys/stdarg.h
rename to include/lib/libc/sys/stdarg.h
diff --git a/include/lib/stdlib/sys/stdint.h b/include/lib/libc/sys/stdint.h
similarity index 100%
rename from include/lib/stdlib/sys/stdint.h
rename to include/lib/libc/sys/stdint.h
diff --git a/include/lib/stdlib/sys/timespec.h b/include/lib/libc/sys/timespec.h
similarity index 100%
rename from include/lib/stdlib/sys/timespec.h
rename to include/lib/libc/sys/timespec.h
diff --git a/include/lib/stdlib/sys/types.h b/include/lib/libc/sys/types.h
similarity index 100%
rename from include/lib/stdlib/sys/types.h
rename to include/lib/libc/sys/types.h
diff --git a/include/lib/stdlib/time.h b/include/lib/libc/time.h
similarity index 100%
rename from include/lib/stdlib/time.h
rename to include/lib/libc/time.h
diff --git a/include/lib/stdlib/xlocale/_strings.h b/include/lib/libc/xlocale/_strings.h
similarity index 100%
rename from include/lib/stdlib/xlocale/_strings.h
rename to include/lib/libc/xlocale/_strings.h
diff --git a/include/lib/stdlib/xlocale/_time.h b/include/lib/libc/xlocale/_time.h
similarity index 100%
rename from include/lib/stdlib/xlocale/_time.h
rename to include/lib/libc/xlocale/_time.h
diff --git a/include/lib/stdlib/stdbool.h b/include/lib/stdlib/stdbool.h
deleted file mode 100644
index 48070c1..0000000
--- a/include/lib/stdlib/stdbool.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2000 Jeroen Ruigrok van der Werven <asmodai@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef __bool_true_false_are_defined
-#define	__bool_true_false_are_defined	1
-
-#ifndef __cplusplus
-
-#define	false	0
-#define	true	1
-
-#define	bool	_Bool
-#if __STDC_VERSION__ < 199901L && __GNUC__ < 3 && !defined(__INTEL_COMPILER)
-typedef	int	_Bool;
-#endif
-
-#endif /* !__cplusplus */
-#endif /* __bool_true_false_are_defined */
diff --git a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
index 808589a..37f3b53 100644
--- a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
+++ b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __XLAT_TABLES_AARCH32_H__
-#define __XLAT_TABLES_AARCH32_H__
+#ifndef XLAT_TABLES_AARCH32_H
+#define XLAT_TABLES_AARCH32_H
 
 #include <arch.h>
 #include <utils_def.h>
@@ -24,7 +24,7 @@
  * The define below specifies the first table level that allows block
  * descriptors.
  */
-#if PAGE_SIZE != (4 * 1024)
+#if PAGE_SIZE != PAGE_SIZE_4KB
 #error "Invalid granule size. AArch32 supports 4KB pages only."
 #endif
 
@@ -43,8 +43,8 @@
  * [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
  * information, Section G4.6.5
  */
-#define MIN_VIRT_ADDR_SPACE_SIZE	(ULL(1) << (32 - TTBCR_TxSZ_MAX))
-#define MAX_VIRT_ADDR_SPACE_SIZE	(ULL(1) << (32 - TTBCR_TxSZ_MIN))
+#define MIN_VIRT_ADDR_SPACE_SIZE	(ULL(1) << (U(32) - TTBCR_TxSZ_MAX))
+#define MAX_VIRT_ADDR_SPACE_SIZE	(ULL(1) << (U(32) - TTBCR_TxSZ_MIN))
 
 /*
  * Here we calculate the initial lookup level from the value of the given
@@ -66,7 +66,8 @@
  * valid. Therefore, the caller is expected to check it is the case using the
  * CHECK_VIRT_ADDR_SPACE_SIZE() macro first.
  */
-#define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_size)			\
-	(((_virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) ? 1 : 2)
+#define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_sz)			\
+	(((_virt_addr_space_sz) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) ?	\
+	 U(1) : U(2))
 
-#endif /* __XLAT_TABLES_AARCH32_H__ */
+#endif /* XLAT_TABLES_AARCH32_H */
diff --git a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
index ad48a35..91ca8e4 100644
--- a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
+++ b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __XLAT_TABLES_AARCH64_H__
-#define __XLAT_TABLES_AARCH64_H__
+#ifndef XLAT_TABLES_AARCH64_H
+#define XLAT_TABLES_AARCH64_H
 
 #include <arch.h>
 #include <utils_def.h>
@@ -30,9 +30,9 @@
  * The define below specifies the first table level that allows block
  * descriptors.
  */
-#if PAGE_SIZE == (4 * 1024)
+#if PAGE_SIZE == PAGE_SIZE_4KB
 # define MIN_LVL_BLOCK_DESC	U(1)
-#elif PAGE_SIZE == (16 * 1024) || PAGE_SIZE == (64 * 1024)
+#elif (PAGE_SIZE == PAGE_SIZE_16KB) || (PAGE_SIZE == PAGE_SIZE_64KB)
 # define MIN_LVL_BLOCK_DESC	U(2)
 #endif
 
@@ -50,8 +50,8 @@
  * information:
  * Page 1730: 'Input address size', 'For all translation stages'.
  */
-#define MIN_VIRT_ADDR_SPACE_SIZE	(ULL(1) << (64 - TCR_TxSZ_MAX))
-#define MAX_VIRT_ADDR_SPACE_SIZE	(ULL(1) << (64 - TCR_TxSZ_MIN))
+#define MIN_VIRT_ADDR_SPACE_SIZE	(ULL(1) << (U(64) - TCR_TxSZ_MAX))
+#define MAX_VIRT_ADDR_SPACE_SIZE	(ULL(1) << (U(64) - TCR_TxSZ_MIN))
 
 /*
  * Here we calculate the initial lookup level from the value of the given
@@ -74,10 +74,10 @@
  * valid. Therefore, the caller is expected to check it is the case using the
  * CHECK_VIRT_ADDR_SPACE_SIZE() macro first.
  */
-#define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_size)				\
-	(((_virt_addr_space_size) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT))		\
-	? 0									\
-	 : (((_virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT))	\
-	 ? 1 : 2))
+#define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_sz)		\
+	(((_virt_addr_space_sz) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT))	\
+	? 0U								\
+	 : (((_virt_addr_space_sz) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT))	\
+	 ? 1U : 2U))
 
-#endif /* __XLAT_TABLES_AARCH64_H__ */
+#endif /* XLAT_TABLES_AARCH64_H */
diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h
index a290a92..e1d0227 100644
--- a/include/lib/xlat_tables/xlat_mmu_helpers.h
+++ b/include/lib/xlat_tables/xlat_mmu_helpers.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __XLAT_MMU_HELPERS_H__
-#define __XLAT_MMU_HELPERS_H__
+#ifndef XLAT_MMU_HELPERS_H
+#define XLAT_MMU_HELPERS_H
 
 /*
  * The following flags are passed to enable_mmu_xxx() to override the default
@@ -52,6 +52,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <stdbool.h>
+#include <stdint.h>
 #include <sys/types.h>
 
 /*
@@ -65,21 +67,30 @@
 
 #ifdef AARCH32
 /* AArch32 specific translation table API */
+#if !ERROR_DEPRECATED
 void enable_mmu_secure(unsigned int flags);
-
 void enable_mmu_direct(unsigned int flags);
+#endif
+
+void enable_mmu_svc_mon(unsigned int flags);
+void enable_mmu_hyp(unsigned int flags);
+
+void enable_mmu_direct_svc_mon(unsigned int flags);
+void enable_mmu_direct_hyp(unsigned int flags);
 #else
 /* AArch64 specific translation table APIs */
 void enable_mmu_el1(unsigned int flags);
+void enable_mmu_el2(unsigned int flags);
 void enable_mmu_el3(unsigned int flags);
 
 void enable_mmu_direct_el1(unsigned int flags);
+void enable_mmu_direct_el2(unsigned int flags);
 void enable_mmu_direct_el3(unsigned int flags);
 #endif /* AARCH32 */
 
-int xlat_arch_is_granule_size_supported(size_t size);
+bool xlat_arch_is_granule_size_supported(size_t size);
 size_t xlat_arch_get_max_supported_granule_size(void);
 
 #endif /* __ASSEMBLY__ */
 
-#endif /* __XLAT_MMU_HELPERS_H__ */
+#endif /* XLAT_MMU_HELPERS_H */
diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h
index c017e19..4097c76 100644
--- a/include/lib/xlat_tables/xlat_tables.h
+++ b/include/lib/xlat_tables/xlat_tables.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __XLAT_TABLES_H__
-#define __XLAT_TABLES_H__
+#ifndef XLAT_TABLES_H
+#define XLAT_TABLES_H
 
 #include <xlat_tables_defs.h>
 
@@ -92,4 +92,4 @@
 void mmap_add(const mmap_region_t *mm);
 
 #endif /*__ASSEMBLY__*/
-#endif /* __XLAT_TABLES_H__ */
+#endif /* XLAT_TABLES_H */
diff --git a/include/lib/xlat_tables/xlat_tables_arch.h b/include/lib/xlat_tables/xlat_tables_arch.h
index af8c463..251b020 100644
--- a/include/lib/xlat_tables/xlat_tables_arch.h
+++ b/include/lib/xlat_tables/xlat_tables_arch.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __XLAT_TABLES_ARCH_H__
-#define __XLAT_TABLES_ARCH_H__
+#ifndef XLAT_TABLES_ARCH_H
+#define XLAT_TABLES_ARCH_H
 
 #ifdef AARCH32
 #include "aarch32/xlat_tables_aarch32.h"
@@ -21,8 +21,8 @@
  * limits. Not that these limits are different for AArch32 and AArch64.
  */
 #define CHECK_VIRT_ADDR_SPACE_SIZE(size)			\
-	(((unsigned long long)(size) >= MIN_VIRT_ADDR_SPACE_SIZE) &&		\
-	((unsigned long long)(size) <= MAX_VIRT_ADDR_SPACE_SIZE) &&		\
+	(((unsigned long long)(size) >= MIN_VIRT_ADDR_SPACE_SIZE) &&	\
+	((unsigned long long)(size) <= MAX_VIRT_ADDR_SPACE_SIZE) &&	\
 	IS_POWER_OF_TWO(size))
 
 /*
@@ -40,4 +40,4 @@
 	((addr_space_size) >>						\
 		XLAT_ADDR_SHIFT(GET_XLAT_TABLE_LEVEL_BASE(addr_space_size)))
 
-#endif /* __XLAT_TABLES_ARCH_H__ */
+#endif /* XLAT_TABLES_ARCH_H */
diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h
index c9d5417..d260c3e 100644
--- a/include/lib/xlat_tables/xlat_tables_defs.h
+++ b/include/lib/xlat_tables/xlat_tables_defs.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __XLAT_TABLES_DEFS_H__
-#define __XLAT_TABLES_DEFS_H__
+#ifndef XLAT_TABLES_DEFS_H
+#define XLAT_TABLES_DEFS_H
 
 #include <arch.h>
 #include <utils_def.h>
@@ -24,6 +24,10 @@
 #define TWO_MB_INDEX(x)		((x) >> TWO_MB_SHIFT)
 #define FOUR_KB_INDEX(x)	((x) >> FOUR_KB_SHIFT)
 
+#define PAGE_SIZE_4KB		U(4096)
+#define PAGE_SIZE_16KB		U(16384)
+#define PAGE_SIZE_64KB		U(65536)
+
 #define INVALID_DESC		U(0x0)
 /*
  * A block descriptor points to a region of memory bigger than the granule size
@@ -66,8 +70,8 @@
  */
 #define PAGE_SIZE_SHIFT		FOUR_KB_SHIFT
 #define PAGE_SIZE		(U(1) << PAGE_SIZE_SHIFT)
-#define PAGE_SIZE_MASK		(PAGE_SIZE - 1)
-#define IS_PAGE_ALIGNED(addr)	(((addr) & PAGE_SIZE_MASK) == 0)
+#define PAGE_SIZE_MASK		(PAGE_SIZE - U(1))
+#define IS_PAGE_ALIGNED(addr)	(((addr) & PAGE_SIZE_MASK) == U(0))
 
 #define XLAT_ENTRY_SIZE_SHIFT	U(3) /* Each MMU table entry is 8 bytes (1 << 3) */
 #define XLAT_ENTRY_SIZE		(U(1) << XLAT_ENTRY_SIZE_SHIFT)
@@ -80,7 +84,7 @@
 /* Values for number of entries in each MMU translation table */
 #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
 #define XLAT_TABLE_ENTRIES	(U(1) << XLAT_TABLE_ENTRIES_SHIFT)
-#define XLAT_TABLE_ENTRIES_MASK	(XLAT_TABLE_ENTRIES - 1)
+#define XLAT_TABLE_ENTRIES_MASK	(XLAT_TABLE_ENTRIES - U(1))
 
 /* Values to convert a memory address to an index into a translation table */
 #define L3_XLAT_ADDRESS_SHIFT	PAGE_SIZE_SHIFT
@@ -90,9 +94,9 @@
 #define XLAT_ADDR_SHIFT(level)	(PAGE_SIZE_SHIFT + \
 		  ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
 
-#define XLAT_BLOCK_SIZE(level)	((u_register_t)1 << XLAT_ADDR_SHIFT(level))
+#define XLAT_BLOCK_SIZE(level)	(UL(1) << XLAT_ADDR_SHIFT(level))
 /* Mask to get the bits used to index inside a block of a certain level */
-#define XLAT_BLOCK_MASK(level)	(XLAT_BLOCK_SIZE(level) - 1)
+#define XLAT_BLOCK_MASK(level)	(XLAT_BLOCK_SIZE(level) - UL(1))
 /* Mask to get the address bits common to a block of a certain table level*/
 #define XLAT_ADDR_MASK(level)	(~XLAT_BLOCK_MASK(level))
 /*
@@ -111,13 +115,13 @@
  * when stage 1 translations can only support one VA range.
  */
 #define AP2_SHIFT			U(0x7)
-#define AP2_RO				U(0x1)
-#define AP2_RW				U(0x0)
+#define AP2_RO				ULL(0x1)
+#define AP2_RW				ULL(0x0)
 
 #define AP1_SHIFT			U(0x6)
-#define AP1_ACCESS_UNPRIVILEGED		U(0x1)
-#define AP1_NO_ACCESS_UNPRIVILEGED	U(0x0)
-#define AP1_RES1			U(0x1)
+#define AP1_ACCESS_UNPRIVILEGED		ULL(0x1)
+#define AP1_NO_ACCESS_UNPRIVILEGED	ULL(0x0)
+#define AP1_RES1			ULL(0x1)
 
 /*
  * The following definitions must all be passed to the LOWER_ATTRS() macro to
@@ -129,9 +133,9 @@
 #define AP_NO_ACCESS_UNPRIVILEGED	(AP1_NO_ACCESS_UNPRIVILEGED << 4)
 #define AP_ONE_VA_RANGE_RES1		(AP1_RES1 << 4)
 #define NS				(U(0x1) << 3)
-#define ATTR_NON_CACHEABLE_INDEX	U(0x2)
-#define ATTR_DEVICE_INDEX		U(0x1)
-#define ATTR_IWBWA_OWBWA_NTR_INDEX	U(0x0)
+#define ATTR_NON_CACHEABLE_INDEX	ULL(0x2)
+#define ATTR_DEVICE_INDEX		ULL(0x1)
+#define ATTR_IWBWA_OWBWA_NTR_INDEX	ULL(0x0)
 #define LOWER_ATTRS(x)			(((x) & U(0xfff)) << 2)
 
 /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h
index 2e5aba5..52c4dc6 100644
--- a/include/lib/xlat_tables/xlat_tables_v2.h
+++ b/include/lib/xlat_tables/xlat_tables_v2.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __XLAT_TABLES_V2_H__
-#define __XLAT_TABLES_V2_H__
+#ifndef XLAT_TABLES_V2_H
+#define XLAT_TABLES_V2_H
 
 #include <xlat_tables_defs.h>
 #include <xlat_tables_v2_helpers.h>
@@ -27,7 +27,7 @@
 
 /* Helper macro to define an mmap_region_t. */
 #define MAP_REGION(_pa, _va, _sz, _attr)	\
-	_MAP_REGION_FULL_SPEC(_pa, _va, _sz, _attr, REGION_DEFAULT_GRANULARITY)
+	MAP_REGION_FULL_SPEC(_pa, _va, _sz, _attr, REGION_DEFAULT_GRANULARITY)
 
 /* Helper macro to define an mmap_region_t with an identity mapping. */
 #define MAP_REGION_FLAT(_adr, _sz, _attr)			\
@@ -44,7 +44,7 @@
  * equivalent to the MAP_REGION() macro.
  */
 #define MAP_REGION2(_pa, _va, _sz, _attr, _gr)			\
-	_MAP_REGION_FULL_SPEC(_pa, _va, _sz, _attr, _gr)
+	MAP_REGION_FULL_SPEC(_pa, _va, _sz, _attr, _gr)
 
 /*
  * Shifts and masks to access fields of an mmap attribute
@@ -125,6 +125,7 @@
  * library to detect it at runtime.
  */
 #define EL1_EL0_REGIME		1
+#define EL2_REGIME		2
 #define EL3_REGIME		3
 #define EL_REGIME_INVALID	-1
 
@@ -163,7 +164,7 @@
  */
 #define REGISTER_XLAT_CONTEXT(_ctx_name, _mmap_count, _xlat_tables_count, \
 			_virt_addr_space_size, _phy_addr_space_size)	\
-	_REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, (_mmap_count),	\
+	REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, (_mmap_count),	\
 					 (_xlat_tables_count),		\
 					 (_virt_addr_space_size),	\
 					 (_phy_addr_space_size),	\
@@ -183,7 +184,7 @@
 #define REGISTER_XLAT_CONTEXT2(_ctx_name, _mmap_count, _xlat_tables_count, \
 			_virt_addr_space_size, _phy_addr_space_size,	\
 			_xlat_regime, _section_name)			\
-	_REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, (_mmap_count),	\
+	REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, (_mmap_count),	\
 					 (_xlat_tables_count),		\
 					 (_virt_addr_space_size),	\
 					 (_phy_addr_space_size),	\
@@ -296,14 +297,15 @@
  * translation tables are not modified by any other code while this function is
  * executing.
  */
-int change_mem_attributes(xlat_ctx_t *ctx, uintptr_t base_va, size_t size,
-			  uint32_t attr);
+int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
+				   size_t size, uint32_t attr);
+int xlat_change_mem_attributes(uintptr_t base_va, size_t size, uint32_t attr);
 
 /*
  * Query the memory attributes of a memory page in a set of translation tables.
  *
  * Return 0 on success, a negative error code on error.
- * On success, the attributes are stored into *attributes.
+ * On success, the attributes are stored into *attr.
  *
  * ctx
  *   Translation context to work on.
@@ -311,11 +313,12 @@
  *   Virtual address of the page to get the attributes of.
  *   There are no alignment restrictions on this address. The attributes of the
  *   memory page it lies within are returned.
- * attributes
+ * attr
  *   Output parameter where to store the attributes of the targeted memory page.
  */
-int get_mem_attributes(const xlat_ctx_t *ctx, uintptr_t base_va,
-		       uint32_t *attributes);
+int xlat_get_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
+				uint32_t *attr);
+int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr);
 
 #endif /*__ASSEMBLY__*/
-#endif /* __XLAT_TABLES_V2_H__ */
+#endif /* XLAT_TABLES_V2_H */
diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h
index 82d96e7..fa89958 100644
--- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h
+++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h
@@ -9,10 +9,10 @@
  * used outside of this library code.
  */
 
-#ifndef __XLAT_TABLES_V2_HELPERS_H__
-#define __XLAT_TABLES_V2_HELPERS_H__
+#ifndef XLAT_TABLES_V2_HELPERS_H
+#define XLAT_TABLES_V2_HELPERS_H
 
-#ifndef __XLAT_TABLES_V2_H__
+#ifndef XLAT_TABLES_V2_H
 #error "Do not include this header file directly. Include xlat_tables_v2.h instead."
 #endif
 
@@ -20,6 +20,7 @@
 
 #include <cassert.h>
 #include <platform_def.h>
+#include <stdbool.h>
 #include <stddef.h>
 #include <xlat_tables_arch.h>
 #include <xlat_tables_defs.h>
@@ -32,7 +33,7 @@
  * the fields of the structure but its parameter list is not guaranteed to
  * remain stable as we add members to mmap_region_t.
  */
-#define _MAP_REGION_FULL_SPEC(_pa, _va, _sz, _attr, _gr)	\
+#define MAP_REGION_FULL_SPEC(_pa, _va, _sz, _attr, _gr)		\
 	{							\
 		.base_pa = (_pa),				\
 		.base_va = (_va),				\
@@ -58,7 +59,7 @@
 	 * null entry.
 	 */
 	struct mmap_region *mmap;
-	unsigned int mmap_num;
+	int mmap_num;
 
 	/*
 	 * Array of finer-grain translation tables.
@@ -66,7 +67,7 @@
 	 * contain both level-2 and level-3 entries.
 	 */
 	uint64_t (*tables)[XLAT_TABLE_ENTRIES];
-	unsigned int tables_num;
+	int tables_num;
 	/*
 	 * Keep track of how many regions are mapped in each table. The base
 	 * table can't be unmapped so it isn't needed to keep track of it.
@@ -75,7 +76,7 @@
 	int *tables_mapped_regions;
 #endif /* PLAT_XLAT_TABLES_DYNAMIC */
 
-	unsigned int next_table;
+	int next_table;
 
 	/*
 	 * Base translation table. It doesn't need to have the same amount of
@@ -95,8 +96,8 @@
 	/* Level of the base translation table. */
 	unsigned int base_level;
 
-	/* Set to 1 when the translation tables are initialized. */
-	unsigned int initialized;
+	/* Set to true when the translation tables are initialized. */
+	bool initialized;
 
 	/*
 	 * Translation regime managed by this xlat_ctx_t. It should be one of
@@ -106,60 +107,60 @@
 };
 
 #if PLAT_XLAT_TABLES_DYNAMIC
-#define _ALLOC_DYNMAP_STRUCT(_ctx_name, _xlat_tables_count)		\
+#define XLAT_ALLOC_DYNMAP_STRUCT(_ctx_name, _xlat_tables_count)		\
 	static int _ctx_name##_mapped_regions[_xlat_tables_count];
 
-#define _REGISTER_DYNMAP_STRUCT(_ctx_name)				\
+#define XLAT_REGISTER_DYNMAP_STRUCT(_ctx_name)				\
 	.tables_mapped_regions = _ctx_name##_mapped_regions,
 #else
-#define _ALLOC_DYNMAP_STRUCT(_ctx_name, _xlat_tables_count)		\
+#define XLAT_ALLOC_DYNMAP_STRUCT(_ctx_name, _xlat_tables_count)		\
 	/* do nothing */
 
-#define _REGISTER_DYNMAP_STRUCT(_ctx_name)				\
+#define XLAT_REGISTER_DYNMAP_STRUCT(_ctx_name)				\
 	/* do nothing */
 #endif /* PLAT_XLAT_TABLES_DYNAMIC */
 
-#define _REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, _mmap_count, _xlat_tables_count,	\
-			_virt_addr_space_size, _phy_addr_space_size,		\
-			_xlat_regime, _section_name)				\
-	CASSERT(CHECK_VIRT_ADDR_SPACE_SIZE(_virt_addr_space_size),		\
-		assert_invalid_virtual_addr_space_size_for_##_ctx_name);	\
-										\
-	CASSERT(CHECK_PHY_ADDR_SPACE_SIZE(_phy_addr_space_size),		\
-		assert_invalid_physical_addr_space_sizefor_##_ctx_name);	\
-										\
-	static mmap_region_t _ctx_name##_mmap[_mmap_count + 1];			\
-										\
-	static uint64_t _ctx_name##_xlat_tables[_xlat_tables_count]		\
-		[XLAT_TABLE_ENTRIES]						\
-		__aligned(XLAT_TABLE_SIZE) __section(_section_name);		\
-										\
-	static uint64_t _ctx_name##_base_xlat_table				\
-		[GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size)]		\
-		__aligned(GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size)	\
-			* sizeof(uint64_t));					\
-										\
-	_ALLOC_DYNMAP_STRUCT(_ctx_name, _xlat_tables_count)			\
-										\
-	static xlat_ctx_t _ctx_name##_xlat_ctx = {				\
-		.va_max_address = (_virt_addr_space_size) - 1,			\
-		.pa_max_address = (_phy_addr_space_size) - 1,			\
-		.mmap = _ctx_name##_mmap,					\
-		.mmap_num = (_mmap_count),					\
-		.base_level = GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_size),	\
-		.base_table = _ctx_name##_base_xlat_table,			\
-		.base_table_entries =						\
-			GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size),	\
-		.tables = _ctx_name##_xlat_tables,				\
-		.tables_num = _xlat_tables_count,				\
-		 _REGISTER_DYNMAP_STRUCT(_ctx_name)				\
-		.xlat_regime = (_xlat_regime),					\
-		.max_pa = 0,							\
-		.max_va = 0,							\
-		.next_table = 0,						\
-		.initialized = 0,						\
+#define REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, _mmap_count,		\
+			_xlat_tables_count, _virt_addr_space_size,	\
+			_phy_addr_space_size, _xlat_regime, _section_name)\
+	CASSERT(CHECK_VIRT_ADDR_SPACE_SIZE(_virt_addr_space_size),	\
+		assert_invalid_virtual_addr_space_size_for_##_ctx_name);\
+									\
+	CASSERT(CHECK_PHY_ADDR_SPACE_SIZE(_phy_addr_space_size),	\
+		assert_invalid_physical_addr_space_sizefor_##_ctx_name);\
+									\
+	static mmap_region_t _ctx_name##_mmap[_mmap_count + 1];		\
+									\
+	static uint64_t _ctx_name##_xlat_tables[_xlat_tables_count]	\
+		[XLAT_TABLE_ENTRIES]					\
+		__aligned(XLAT_TABLE_SIZE) __section(_section_name);	\
+									\
+	static uint64_t _ctx_name##_base_xlat_table			\
+		[GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size)]	\
+		__aligned(GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size)\
+			* sizeof(uint64_t));				\
+									\
+	XLAT_ALLOC_DYNMAP_STRUCT(_ctx_name, _xlat_tables_count)		\
+									\
+	static xlat_ctx_t _ctx_name##_xlat_ctx = {			\
+		.va_max_address = (_virt_addr_space_size) - 1UL,	\
+		.pa_max_address = (_phy_addr_space_size) - 1ULL,	\
+		.mmap = _ctx_name##_mmap,				\
+		.mmap_num = (_mmap_count),				\
+		.base_level = GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_size),\
+		.base_table = _ctx_name##_base_xlat_table,		\
+		.base_table_entries =					\
+			GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size),\
+		.tables = _ctx_name##_xlat_tables,			\
+		.tables_num = _xlat_tables_count,			\
+		 XLAT_REGISTER_DYNMAP_STRUCT(_ctx_name)			\
+		.xlat_regime = (_xlat_regime),				\
+		.max_pa = 0U,						\
+		.max_va = 0U,						\
+		.next_table = 0,					\
+		.initialized = false,					\
 	}
 
 #endif /*__ASSEMBLY__*/
 
-#endif /* __XLAT_TABLES_V2_HELPERS_H__ */
+#endif /* XLAT_TABLES_V2_HELPERS_H */
diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h
index c3ae564..a388ed9 100644
--- a/include/plat/arm/board/common/board_arm_def.h
+++ b/include/plat/arm/board/common/board_arm_def.h
@@ -71,9 +71,12 @@
 #elif defined(IMAGE_BL32)
 # define PLAT_ARM_MMAP_ENTRIES		8
 # define MAX_XLAT_TABLES		5
-#else
+#elif !USE_ROMLIB
 # define PLAT_ARM_MMAP_ENTRIES		11
 # define MAX_XLAT_TABLES		5
+#else
+# define PLAT_ARM_MMAP_ENTRIES		12
+# define MAX_XLAT_TABLES		6
 #endif
 
 /*
@@ -83,6 +86,18 @@
 #define PLAT_ARM_MAX_BL1_RW_SIZE	0xB000
 
 /*
+ * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
+ */
+
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0x1000
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	0xe000
+#else
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	0
+#endif
+
+/*
  * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
  * little space for growth.
  */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 9a661d7..5da8cdb 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -241,16 +241,25 @@
 						ARM_EL3_TZC_DRAM1_SIZE,	\
 						MT_MEMORY | MT_RW | MT_SECURE)
 
+/*
+ * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
+ * otherwise one region is defined containing both.
+ */
 #if SEPARATE_CODE_AND_RODATA
-#define ARM_MAP_BL_CODE			MAP_REGION_FLAT(			\
+#define ARM_MAP_BL_RO			MAP_REGION_FLAT(			\
 						BL_CODE_BASE,			\
 						BL_CODE_END - BL_CODE_BASE,	\
-						MT_CODE | MT_SECURE)
-#define ARM_MAP_BL_RO_DATA		MAP_REGION_FLAT(			\
+						MT_CODE | MT_SECURE),		\
+					MAP_REGION_FLAT(			\
 						BL_RO_DATA_BASE,		\
 						BL_RO_DATA_END			\
 							- BL_RO_DATA_BASE,	\
 						MT_RO_DATA | MT_SECURE)
+#else
+#define ARM_MAP_BL_RO			MAP_REGION_FLAT(			\
+						BL_CODE_BASE,			\
+						BL_CODE_END - BL_CODE_BASE,	\
+						MT_CODE | MT_SECURE)
 #endif
 #if USE_COHERENT_MEM
 #define ARM_MAP_BL_COHERENT_RAM		MAP_REGION_FLAT(			\
@@ -259,16 +268,23 @@
 							- BL_COHERENT_RAM_BASE, \
 						MT_DEVICE | MT_RW | MT_SECURE)
 #endif
+#if USE_ROMLIB
+#define ARM_MAP_ROMLIB_CODE		MAP_REGION_FLAT(			\
+						ROMLIB_RO_BASE,			\
+						ROMLIB_RO_LIMIT	- ROMLIB_RO_BASE,\
+						MT_CODE | MT_SECURE)
+
+#define ARM_MAP_ROMLIB_DATA		MAP_REGION_FLAT(			\
+						ROMLIB_RW_BASE,			\
+						ROMLIB_RW_END	- ROMLIB_RW_BASE,\
+						MT_MEMORY | MT_RW | MT_SECURE)
+#endif
 
 /*
- * The number of regions like RO(code), coherent and data required by
+ * The max number of regions like RO(code), coherent and data required by
  * different BL stages which need to be mapped in the MMU.
  */
-#if USE_COHERENT_MEM
 # define ARM_BL_REGIONS			4
-#else
-# define ARM_BL_REGIONS			3
-#endif
 
 #define MAX_MMAP_REGIONS		(PLAT_ARM_MMAP_ENTRIES +	\
 					 ARM_BL_REGIONS)
@@ -341,14 +357,23 @@
  ******************************************************************************/
 #define BL1_RO_BASE			PLAT_ARM_TRUSTED_ROM_BASE
 #define BL1_RO_LIMIT			(PLAT_ARM_TRUSTED_ROM_BASE	\
-					 + PLAT_ARM_TRUSTED_ROM_SIZE)
+					 + (PLAT_ARM_TRUSTED_ROM_SIZE - \
+					    PLAT_ARM_MAX_ROMLIB_RO_SIZE))
 /*
  * Put BL1 RW at the top of the Trusted SRAM.
  */
 #define BL1_RW_BASE			(ARM_BL_RAM_BASE +		\
 						ARM_BL_RAM_SIZE -	\
-						PLAT_ARM_MAX_BL1_RW_SIZE)
-#define BL1_RW_LIMIT			(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+						(PLAT_ARM_MAX_BL1_RW_SIZE +\
+						 PLAT_ARM_MAX_ROMLIB_RW_SIZE))
+#define BL1_RW_LIMIT			(ARM_BL_RAM_BASE + 		\
+					    (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE))
+
+#define ROMLIB_RO_BASE			BL1_RO_LIMIT
+#define ROMLIB_RO_LIMIT			(PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE)
+
+#define ROMLIB_RW_BASE			(BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
+#define ROMLIB_RW_END			(ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)
 
 /*******************************************************************************
  * BL2 specific defines.
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 506bed3..1af4dd1 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -72,6 +72,8 @@
 void arm_setup_page_tables(const mmap_region_t bl_regions[],
 			   const mmap_region_t plat_regions[]);
 
+void arm_setup_romlib(void);
+
 #if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
 /*
  * Use this macro to instantiate lock before it is used in below
diff --git a/lib/stdlib/abort.c b/lib/libc/abort.c
similarity index 100%
rename from lib/stdlib/abort.c
rename to lib/libc/abort.c
diff --git a/lib/stdlib/assert.c b/lib/libc/assert.c
similarity index 100%
rename from lib/stdlib/assert.c
rename to lib/libc/assert.c
diff --git a/lib/libc/exit.c b/lib/libc/exit.c
new file mode 100644
index 0000000..b2fde9c
--- /dev/null
+++ b/lib/libc/exit.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+
+static void (*exitfun)(void);
+
+void exit(int status)
+{
+	if (exitfun)
+		(*exitfun)();
+	for (;;)
+		;
+}
+
+int atexit(void (*fun)(void))
+{
+	if (exitfun)
+		return -1;
+	exitfun = fun;
+
+	return 0;
+}
diff --git a/lib/stdlib/stdlib.mk b/lib/libc/libc.mk
similarity index 77%
rename from lib/stdlib/stdlib.mk
rename to lib/libc/libc.mk
index 8211623..ded3d74 100644
--- a/lib/stdlib/stdlib.mk
+++ b/lib/libc/libc.mk
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-STDLIB_SRCS	:=	$(addprefix lib/stdlib/,	\
+LIBC_SRCS	:=	$(addprefix lib/libc/,	\
 			abort.c				\
 			assert.c			\
 			exit.c				\
@@ -21,5 +21,5 @@
 			subr_prf.c			\
 			timingsafe_bcmp.c)
 
-INCLUDES	+=	-Iinclude/lib/stdlib		\
-			-Iinclude/lib/stdlib/sys
+INCLUDES	+=	-Iinclude/lib/libc		\
+			-Iinclude/lib/libc/sys
diff --git a/lib/stdlib/mem.c b/lib/libc/mem.c
similarity index 100%
rename from lib/stdlib/mem.c
rename to lib/libc/mem.c
diff --git a/lib/stdlib/printf.c b/lib/libc/printf.c
similarity index 100%
rename from lib/stdlib/printf.c
rename to lib/libc/printf.c
diff --git a/lib/stdlib/putchar.c b/lib/libc/putchar.c
similarity index 100%
rename from lib/stdlib/putchar.c
rename to lib/libc/putchar.c
diff --git a/lib/stdlib/puts.c b/lib/libc/puts.c
similarity index 100%
rename from lib/stdlib/puts.c
rename to lib/libc/puts.c
diff --git a/lib/stdlib/sscanf.c b/lib/libc/sscanf.c
similarity index 100%
rename from lib/stdlib/sscanf.c
rename to lib/libc/sscanf.c
diff --git a/lib/stdlib/strchr.c b/lib/libc/strchr.c
similarity index 100%
rename from lib/stdlib/strchr.c
rename to lib/libc/strchr.c
diff --git a/lib/stdlib/strcmp.c b/lib/libc/strcmp.c
similarity index 100%
rename from lib/stdlib/strcmp.c
rename to lib/libc/strcmp.c
diff --git a/lib/stdlib/strlen.c b/lib/libc/strlen.c
similarity index 100%
rename from lib/stdlib/strlen.c
rename to lib/libc/strlen.c
diff --git a/lib/stdlib/strncmp.c b/lib/libc/strncmp.c
similarity index 100%
rename from lib/stdlib/strncmp.c
rename to lib/libc/strncmp.c
diff --git a/lib/stdlib/strnlen.c b/lib/libc/strnlen.c
similarity index 100%
rename from lib/stdlib/strnlen.c
rename to lib/libc/strnlen.c
diff --git a/lib/stdlib/subr_prf.c b/lib/libc/subr_prf.c
similarity index 100%
rename from lib/stdlib/subr_prf.c
rename to lib/libc/subr_prf.c
diff --git a/lib/stdlib/timingsafe_bcmp.c b/lib/libc/timingsafe_bcmp.c
similarity index 100%
rename from lib/stdlib/timingsafe_bcmp.c
rename to lib/libc/timingsafe_bcmp.c
diff --git a/lib/libfdt/libfdt.mk b/lib/libfdt/libfdt.mk
index d03dde2..1cbbd78 100644
--- a/lib/libfdt/libfdt.mk
+++ b/lib/libfdt/libfdt.mk
@@ -15,3 +15,5 @@
 			fdt_wip.c)			\
 
 INCLUDES	+=	-Iinclude/lib/libfdt
+
+$(eval $(call MAKE_LIB,fdt))
diff --git a/lib/psci/aarch32/psci_helpers.S b/lib/psci/aarch32/psci_helpers.S
index a29a29c..63d7e70 100644
--- a/lib/psci/aarch32/psci_helpers.S
+++ b/lib/psci/aarch32/psci_helpers.S
@@ -91,28 +91,6 @@
 	stcopr	r0, SCTLR
 	isb
 
-#if PLAT_XLAT_TABLES_DYNAMIC
-	/* ---------------------------------------------
-	 * During warm boot the MMU is enabled with data
-	 * cache disabled, then the interconnect is set
-	 * up and finally the data cache is enabled.
-	 *
-	 * During this period, if another CPU modifies
-	 * the translation tables, the MMU table walker
-	 * may read the old entries. This is only a
-	 * problem for dynamic regions, the warm boot
-	 * code isn't affected because it is static.
-	 *
-	 * Invalidate all TLB entries loaded while the
-	 * CPU wasn't coherent with the rest of the
-	 * system.
-	 * ---------------------------------------------
-	 */
-	stcopr	r0, TLBIALL
-	dsb	ish
-	isb
-#endif
-
 	pop	{r12, pc}
 endfunc psci_do_pwrup_cache_maintenance
 
diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S
index d37ca76..06d6636 100644
--- a/lib/psci/aarch64/psci_helpers.S
+++ b/lib/psci/aarch64/psci_helpers.S
@@ -115,28 +115,6 @@
 	msr	sctlr_el3, x0
 	isb
 
-#if PLAT_XLAT_TABLES_DYNAMIC
-	/* ---------------------------------------------
-	 * During warm boot the MMU is enabled with data
-	 * cache disabled, then the interconnect is set
-	 * up and finally the data cache is enabled.
-	 *
-	 * During this period, if another CPU modifies
-	 * the translation tables, the MMU table walker
-	 * may read the old entries. This is only a
-	 * problem for dynamic regions, the warm boot
-	 * code isn't affected because it is static.
-	 *
-	 * Invalidate all TLB entries loaded while the
-	 * CPU wasn't coherent with the rest of the
-	 * system.
-	 * ---------------------------------------------
-	 */
-	tlbi	alle3
-	dsb	ish
-	isb
-#endif
-
 	ldp	x29, x30, [sp], #16
 	ret
 endfunc psci_do_pwrup_cache_maintenance
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 59c9c68..ec74a8c 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -267,7 +267,7 @@
 static plat_local_state_t get_non_cpu_pd_node_local_state(
 		unsigned int parent_idx)
 {
-#if !USE_COHERENT_MEM || !HW_ASSISTED_COHERENCY
+#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY)
 	flush_dcache_range(
 			(uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
 			sizeof(psci_non_cpu_pd_nodes[parent_idx]));
@@ -283,7 +283,7 @@
 		plat_local_state_t state)
 {
 	psci_non_cpu_pd_nodes[parent_idx].local_state = state;
-#if !USE_COHERENT_MEM || !HW_ASSISTED_COHERENCY
+#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY)
 	flush_dcache_range(
 			(uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
 			sizeof(psci_non_cpu_pd_nodes[parent_idx]));
diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c
index 6a35ff6..fd822bc 100644
--- a/lib/psci/psci_main.c
+++ b/lib/psci/psci_main.c
@@ -82,7 +82,7 @@
 	}
 
 	/* Fast path for CPU standby.*/
-	if (is_cpu_standby_req(is_power_down_state, target_pwrlvl) != 0) {
+	if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
 		if  (psci_plat_pm_ops->cpu_standby == NULL)
 			return PSCI_E_INVALID_PARAMS;
 
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index 2ea9f76..82b951d 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -14,6 +14,7 @@
 #include <cpu_data.h>
 #include <psci.h>
 #include <spinlock.h>
+#include <stdbool.h>
 
 /*
  * The PSCI capability which are provided by the generic code but does not
@@ -93,10 +94,10 @@
 }
 
 /* Helper function to identify a CPU standby request in PSCI Suspend call */
-static inline int is_cpu_standby_req(unsigned int is_power_down_state,
-				     unsigned int retn_lvl)
+static inline bool is_cpu_standby_req(unsigned int is_power_down_state,
+				      unsigned int retn_lvl)
 {
-	return ((is_power_down_state == 0U) && (retn_lvl == 0U)) ? 1 : 0;
+	return (is_power_down_state == 0U) && (retn_lvl == 0U);
 }
 
 /*******************************************************************************
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
new file mode 100644
index 0000000..46b9206
--- /dev/null
+++ b/lib/romlib/Makefile
@@ -0,0 +1,71 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+AS          = $(CROSS_COMPILE)as
+LD          = $(CROSS_COMPILE)ld
+OC          = $(CROSS_COMPILE)objcopy
+CPP         = $(CROSS_COMPILE)cpp
+BUILD_DIR   = ../../$(BUILD_PLAT)/romlib
+LIB_DIR     = ../../$(BUILD_PLAT)/lib
+WRAPPER_DIR = ../../$(BUILD_PLAT)/libwrapper
+LIBS        = -lmbedtls -lfdt -lc
+INC         = $(INCLUDES:-I%=-I../../%)
+PPFLAGS     = $(INC) $(DEFINES) -P -D__ASSEMBLY__ -D__LINKER__ -MD -MP -MT $(BUILD_DIR)/romlib.ld
+OBJS        = $(BUILD_DIR)/jmptbl.o $(BUILD_DIR)/init.o
+
+V ?= 0
+ifeq ($(V),0)
+  Q := @
+else
+  Q :=
+endif
+
+ifeq ($(DEBUG),1)
+   CFLAGS  := -g
+   LDFLAGS := -g
+endif
+
+
+.PHONY: all clean distclean
+
+all: $(BUILD_DIR)/romlib.bin $(LIB_DIR)/libwrappers.a
+
+%.o: %.s
+	@echo "  AS      $@"
+	$(Q)$(AS) $(ASFLAGS) -o $@ $<
+
+$(BUILD_DIR)/%.o: %.s
+	@echo "  AS      $@"
+	$(Q)$(AS) $(ASFLAGS) -o $@ $<
+
+$(BUILD_DIR)/romlib.ld: romlib.ld.S
+	@echo "  PP      $@"
+	$(Q)$(CPP) $(PPFLAGS) -o $@ romlib.ld.S
+
+$(BUILD_DIR)/romlib.elf: $(OBJS) $(BUILD_DIR)/romlib.ld
+	@echo "  LD      $@"
+	$(Q)$(LD) -T $(BUILD_DIR)/romlib.ld -L$(LIB_DIR) $(LDFLAGS) -o $@ $(OBJS) $(LIBS)
+
+$(BUILD_DIR)/romlib.bin: $(BUILD_DIR)/romlib.elf
+	@echo "  BIN     $@"
+	$(Q)$(OC) -O binary $(BUILD_DIR)/romlib.elf $@
+
+$(WRAPPER_DIR)/jmpvar.s: $(BUILD_DIR)/romlib.elf
+	@echo "  VAR     $@"
+	$(Q)./genvar.sh -o $@ $(BUILD_DIR)/romlib.elf
+
+$(LIB_DIR)/libwrappers.a: jmptbl.i $(WRAPPER_DIR)/jmpvar.o
+	@echo "  AR      $@"
+	$(Q)./genwrappers.sh -b $(WRAPPER_DIR) -o $@ jmptbl.i
+
+$(BUILD_DIR)/jmptbl.s: jmptbl.i
+	@echo "  TBL     $@"
+	$(Q)./gentbl.sh -o $@ jmptbl.i
+
+clean:
+	@rm -f $(BUILD_DIR)/*
+
+-include $(BUILD_DIR)/romlib.d
diff --git a/lib/romlib/gentbl.sh b/lib/romlib/gentbl.sh
new file mode 100755
index 0000000..0695f6e
--- /dev/null
+++ b/lib/romlib/gentbl.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+set -e
+
+output=jmptbl.s
+
+for i
+do
+	case $i in
+	-o)
+		output=$2
+		shift 2
+		;;
+	--)
+		shift
+		break
+		;;
+	-*)
+		echo usage: gentbl.sh [-o output]  file ... >&2
+		exit 1
+		;;
+	esac
+done
+
+tmp=`mktemp`
+trap "rm -f $tmp" EXIT INT QUIT
+
+rm -f $output
+
+awk -v OFS="\n" '
+BEGIN {print "\t.text",
+             "\t.globl\tjmptbl",
+             "jmptbl:"}
+      {sub(/[:blank:]*#.*/,"")}
+!/^$/ {print "\tb\t" $3}' "$@" > $tmp
+
+mv $tmp $output
diff --git a/lib/romlib/genvar.sh b/lib/romlib/genvar.sh
new file mode 100755
index 0000000..a3e2cdf
--- /dev/null
+++ b/lib/romlib/genvar.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+set -e
+
+output=jmpvar.s
+for i
+do
+	case $i in
+	-o)
+		output=$2
+		shift 2
+		;;
+	--)
+		shift
+		break
+		;;
+	-*)
+		echo usage: genvar.sh [-o output] file... >&2
+		;;
+	esac
+done
+
+tmp=`mktemp`
+trap "rm -f $tmp" EXIT INT QUIT
+
+nm -a "$@" |
+awk -v OFS="\n" '
+$3 == ".text" {print "\t.data",
+                     "\t.globl\tjmptbl",
+                     "\t.align\t4",
+                     "jmptbl:\t.quad\t0x" $1}' > $tmp
+
+mv $tmp $output
diff --git a/lib/romlib/genwrappers.sh b/lib/romlib/genwrappers.sh
new file mode 100755
index 0000000..bcf670b
--- /dev/null
+++ b/lib/romlib/genwrappers.sh
@@ -0,0 +1,52 @@
+#!/bin/sh
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+set -e
+
+build=.
+out=output.a
+
+for i
+do
+	case $i in
+	-o)
+		out=$2
+		shift 2
+		;;
+	-b)
+		build=$2
+		shift 2
+		;;
+	--)
+		shift
+		break
+		;;
+	-*)
+		echo usage: genwrappers.sh [-o output] [-b dir] file ... >&2
+		exit 1
+		;;
+	esac
+done
+
+awk  '{sub(/[:blank:]*#.*/,"")}
+!/^$/ {print $1*4, $2, $3}' "$@" |
+while read idx lib sym
+do
+	file=$build/${lib}_$sym
+
+	cat <<EOF > $file.s
+	.globl	$sym
+$sym:
+	ldr	x17, =jmptbl
+	ldr	x17, [x17]
+	mov	x16, $idx
+	add	x16, x16, x17
+	br	x16
+EOF
+
+	${CROSS_COMPILE}as -o $file.o $file.s
+done
+
+${CROSS_COMPILE}ar -rc $out $build/*.o
diff --git a/lib/romlib/init.s b/lib/romlib/init.s
new file mode 100644
index 0000000..5cf2aca
--- /dev/null
+++ b/lib/romlib/init.s
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+	.globl	rom_lib_init
+	.extern	__DATA_RAM_START__, __DATA_ROM_START__, __DATA_SIZE__
+	.extern	memset, memcpy
+
+rom_lib_init:
+	cmp	w0, #1
+	mov	w0, #0
+	b.le	1f
+	ret
+
+1:	stp	x29, x30, [sp, #-16]!
+	adrp	x0, __DATA_RAM_START__
+	ldr	x1,= __DATA_ROM_START__
+	ldr	x2, =__DATA_SIZE__
+	bl	memcpy
+
+	ldr	x0, =__BSS_START__
+	mov	x1, #0
+	ldr	x2, =__BSS_SIZE__
+	bl	memset
+	ldp	x29, x30, [sp], #16
+
+	mov	w0, #1
+	ret
diff --git a/lib/romlib/jmptbl.i b/lib/romlib/jmptbl.i
new file mode 100644
index 0000000..338cd8a
--- /dev/null
+++ b/lib/romlib/jmptbl.i
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+0	rom	rom_lib_init
+1	fdt	fdt_getprop_namelen
+2	fdt	fdt_setprop_inplace
+3	fdt	fdt_check_header
+4	fdt	fdt_node_offset_by_compatible
+5	mbedtls	mbedtls_asn1_get_alg
+6	mbedtls	mbedtls_asn1_get_alg_null
+7	mbedtls	mbedtls_asn1_get_bitstring_null
+8	mbedtls	mbedtls_asn1_get_bool
+9	mbedtls	mbedtls_asn1_get_int
+10	mbedtls	mbedtls_asn1_get_tag
+11	mbedtls	mbedtls_free
+12	mbedtls	mbedtls_md
+13	mbedtls	mbedtls_md_get_size
+14	mbedtls	mbedtls_memory_buffer_alloc_init
+15	mbedtls	mbedtls_oid_get_md_alg
+16	mbedtls	mbedtls_oid_get_numeric_string
+17	mbedtls	mbedtls_oid_get_pk_alg
+18	mbedtls	mbedtls_oid_get_sig_alg
+19	mbedtls	mbedtls_pk_free
+20	mbedtls	mbedtls_pk_init
+21	mbedtls	mbedtls_pk_parse_subpubkey
+22	mbedtls	mbedtls_pk_verify_ext
+23	mbedtls	mbedtls_platform_set_snprintf
+24	mbedtls	mbedtls_x509_get_rsassa_pss_params
+25	mbedtls	mbedtls_x509_get_sig_alg
+26	mbedtls	mbedtls_md_info_from_type
+27	c	exit
+28	c	atexit
diff --git a/lib/romlib/romlib.ld.S b/lib/romlib/romlib.ld.S
new file mode 100644
index 0000000..8f0bc62
--- /dev/null
+++ b/lib/romlib/romlib.ld.S
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+#include <xlat_tables_defs.h>
+
+MEMORY {
+	ROM (rx): ORIGIN = ROMLIB_RO_BASE, LENGTH = ROMLIB_RO_LIMIT - ROMLIB_RO_BASE
+	RAM (rwx): ORIGIN = ROMLIB_RW_BASE, LENGTH = ROMLIB_RW_END - ROMLIB_RW_BASE
+}
+
+OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
+OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
+ENTRY(jmptbl)
+
+SECTIONS
+{
+	. = ROMLIB_RO_BASE;
+	.text : {
+		*jmptbl.o(.text)
+		*(.text*)
+		*(.rodata*)
+	} >ROM
+
+	__DATA_ROM_START__ = LOADADDR(.data);
+
+	.data : {
+		__DATA_RAM_START__ = .;
+		*(.data*)
+		__DATA_RAM_END__ = .;
+	} >RAM AT>ROM
+
+	__DATA_SIZE__ = SIZEOF(.data);
+
+	.bss : {
+		__BSS_START__ = .;
+		*(.bss*)
+		__BSS_END__ = .;
+	 } >RAM
+	__BSS_SIZE__ = SIZEOF(.bss);
+}
diff --git a/lib/stdlib/exit.c b/lib/stdlib/exit.c
deleted file mode 100644
index afc3f93..0000000
--- a/lib/stdlib/exit.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <debug.h>
-#include <stdlib.h>
-
-void exit(int v)
-{
-	ERROR("EXIT\n");
-	panic();
-}
diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c
index dd63939..033e237 100644
--- a/lib/xlat_tables/aarch32/xlat_tables.c
+++ b/lib/xlat_tables/aarch32/xlat_tables.c
@@ -13,7 +13,7 @@
 #include <xlat_tables.h>
 #include "../xlat_tables_private.h"
 
-#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)
+#if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)
 #error ARMv7 target does not support LPAE MMU descriptors
 #endif
 
@@ -34,16 +34,16 @@
 }
 #endif /* ENABLE_ASSERTIONS */
 
-int xlat_arch_current_el(void)
+unsigned int xlat_arch_current_el(void)
 {
 	/*
 	 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System,
 	 * SVC, Abort, UND, IRQ and FIQ modes) execute at EL3.
 	 */
-	return 3;
+	return 3U;
 }
 
-uint64_t xlat_arch_get_xn_desc(int el __unused)
+uint64_t xlat_arch_get_xn_desc(unsigned int el __unused)
 {
 	return UPPER_ATTRS(XN);
 }
@@ -53,25 +53,37 @@
 	unsigned long long max_pa;
 	uintptr_t max_va;
 	print_mmap();
-	init_xlation_table(0, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
+	init_xlation_table(0U, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
 						&max_va, &max_pa);
 
-	assert(max_va <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
-	assert(max_pa <= PLAT_PHY_ADDR_SPACE_SIZE - 1);
-	assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <= get_max_supported_pa());
+	assert(max_va <= (PLAT_VIRT_ADDR_SPACE_SIZE - 1U));
+	assert(max_pa <= (PLAT_PHY_ADDR_SPACE_SIZE - 1U));
+	assert((PLAT_PHY_ADDR_SPACE_SIZE - 1U) <= get_max_supported_pa());
 }
 
 /*******************************************************************************
  * Function for enabling the MMU in Secure PL1, assuming that the
  * page-tables have already been created.
  ******************************************************************************/
+#if !ERROR_DEPRECATED
 void enable_mmu_secure(unsigned int flags)
 {
+	enable_mmu_svc_mon(flags);
+}
+
+void enable_mmu_direct(unsigned int flags)
+{
+	enable_mmu_direct_svc_mon(flags);
+}
+#endif
+
+void enable_mmu_svc_mon(unsigned int flags)
+{
 	unsigned int mair0, ttbcr, sctlr;
 	uint64_t ttbr0;
 
 	assert(IS_IN_SECURE());
-	assert((read_sctlr() & SCTLR_M_BIT) == 0);
+	assert((read_sctlr() & SCTLR_M_BIT) == 0U);
 
 	/* Set attributes in the right indices of the MAIR */
 	mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
@@ -87,18 +99,18 @@
 	/*
 	 * Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1.
 	 */
-	if (flags & XLAT_TABLE_NC) {
+	int t0sz = 32 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE);
+
+	if ((flags & XLAT_TABLE_NC) != 0U) {
 		/* Inner & outer non-cacheable non-shareable. */
 		ttbcr = TTBCR_EAE_BIT |
 			TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
-			TTBCR_RGN0_INNER_NC |
-			(32 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE));
+			TTBCR_RGN0_INNER_NC | (uint32_t) t0sz;
 	} else {
 		/* Inner & outer WBWA & shareable. */
 		ttbcr = TTBCR_EAE_BIT |
 			TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
-			TTBCR_RGN0_INNER_WBA |
-			(32 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE));
+			TTBCR_RGN0_INNER_WBA | (uint32_t) t0sz;
 	}
 	ttbcr |= TTBCR_EPD1_BIT;
 	write_ttbcr(ttbcr);
@@ -106,7 +118,7 @@
 	/* Set TTBR0 bits as well */
 	ttbr0 = (uintptr_t) base_xlation_table;
 	write64_ttbr0(ttbr0);
-	write64_ttbr1(0);
+	write64_ttbr1(0U);
 
 	/*
 	 * Ensure all translation table writes have drained
@@ -120,7 +132,7 @@
 	sctlr = read_sctlr();
 	sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;
 
-	if (flags & DISABLE_DCACHE)
+	if ((flags & DISABLE_DCACHE) != 0U)
 		sctlr &= ~SCTLR_C_BIT;
 	else
 		sctlr |= SCTLR_C_BIT;
@@ -131,7 +143,7 @@
 	isb();
 }
 
-void enable_mmu_direct(unsigned int flags)
+void enable_mmu_direct_svc_mon(unsigned int flags)
 {
-	enable_mmu_secure(flags);
+	enable_mmu_svc_mon(flags);
 }
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
index 5717516..d88d7b1 100644
--- a/lib/xlat_tables/aarch64/xlat_tables.c
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -31,26 +31,26 @@
 					unsigned long long max_addr)
 {
 	/* Physical address can't exceed 48 bits */
-	assert((max_addr & ADDR_MASK_48_TO_63) == 0);
+	assert((max_addr & ADDR_MASK_48_TO_63) == 0U);
 
 	/* 48 bits address */
-	if (max_addr & ADDR_MASK_44_TO_47)
+	if ((max_addr & ADDR_MASK_44_TO_47) != 0U)
 		return TCR_PS_BITS_256TB;
 
 	/* 44 bits address */
-	if (max_addr & ADDR_MASK_42_TO_43)
+	if ((max_addr & ADDR_MASK_42_TO_43) != 0U)
 		return TCR_PS_BITS_16TB;
 
 	/* 42 bits address */
-	if (max_addr & ADDR_MASK_40_TO_41)
+	if ((max_addr & ADDR_MASK_40_TO_41) != 0U)
 		return TCR_PS_BITS_4TB;
 
 	/* 40 bits address */
-	if (max_addr & ADDR_MASK_36_TO_39)
+	if ((max_addr & ADDR_MASK_36_TO_39) != 0U)
 		return TCR_PS_BITS_1TB;
 
 	/* 36 bits address */
-	if (max_addr & ADDR_MASK_32_TO_35)
+	if ((max_addr & ADDR_MASK_32_TO_35) != 0U)
 		return TCR_PS_BITS_64GB;
 
 	return TCR_PS_BITS_4GB;
@@ -78,21 +78,21 @@
 }
 #endif /* ENABLE_ASSERTIONS */
 
-int xlat_arch_current_el(void)
+unsigned int xlat_arch_current_el(void)
 {
-	int el = GET_EL(read_CurrentEl());
+	unsigned int el = (unsigned int)GET_EL(read_CurrentEl());
 
-	assert(el > 0);
+	assert(el > 0U);
 
 	return el;
 }
 
-uint64_t xlat_arch_get_xn_desc(int el)
+uint64_t xlat_arch_get_xn_desc(unsigned int el)
 {
-	if (el == 3) {
+	if (el == 3U) {
 		return UPPER_ATTRS(XN);
 	} else {
-		assert(el == 1);
+		assert(el == 1U);
 		return UPPER_ATTRS(PXN);
 	}
 }
@@ -102,12 +102,12 @@
 	unsigned long long max_pa;
 	uintptr_t max_va;
 	print_mmap();
-	init_xlation_table(0, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
+	init_xlation_table(0U, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
 			   &max_va, &max_pa);
 
-	assert(max_va <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
-	assert(max_pa <= PLAT_PHY_ADDR_SPACE_SIZE - 1);
-	assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <= get_max_supported_pa());
+	assert(max_va <= (PLAT_VIRT_ADDR_SPACE_SIZE - 1U));
+	assert(max_pa <= (PLAT_PHY_ADDR_SPACE_SIZE - 1U));
+	assert((PLAT_PHY_ADDR_SPACE_SIZE - 1U) <= get_max_supported_pa());
 
 	tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
 }
@@ -129,7 +129,7 @@
 		uint32_t sctlr;						\
 									\
 		assert(IS_IN_EL(_el));					\
-		assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0);	\
+		assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0U);	\
 									\
 		/* Set attributes in the right indices of the MAIR */	\
 		mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);	\
@@ -144,16 +144,18 @@
 									\
 		/* Set TCR bits as well. */				\
 		/* Set T0SZ to (64 - width of virtual address space) */	\
-		if (flags & XLAT_TABLE_NC) {				\
+		int t0sz = 64 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE);\
+									\
+		if ((flags & XLAT_TABLE_NC) != 0U) {			\
 			/* Inner & outer non-cacheable non-shareable. */\
 			tcr = TCR_SH_NON_SHAREABLE |			\
 				TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC |	\
-				(64 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE));\
+				(uint64_t) t0sz;			\
 		} else {						\
 			/* Inner & outer WBWA & shareable. */		\
 			tcr = TCR_SH_INNER_SHAREABLE |			\
 				TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA |	\
-				(64 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE));\
+				(uint64_t) t0sz;			\
 		}							\
 		tcr |= _tcr_extra;					\
 		write_tcr_el##_el(tcr);					\
@@ -172,7 +174,7 @@
 		sctlr = read_sctlr_el##_el();				\
 		sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;			\
 									\
-		if (flags & DISABLE_DCACHE)				\
+		if ((flags & DISABLE_DCACHE) != 0U)			\
 			sctlr &= ~SCTLR_C_BIT;				\
 		else							\
 			sctlr |= SCTLR_C_BIT;				\
diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c
index ce6e341..65d3f0f 100644
--- a/lib/xlat_tables/xlat_tables_common.c
+++ b/lib/xlat_tables/xlat_tables_common.c
@@ -11,6 +11,7 @@
 #include <common_def.h>
 #include <debug.h>
 #include <platform_def.h>
+#include <stdbool.h>
 #include <string.h>
 #include <types.h>
 #include <utils.h>
@@ -32,6 +33,7 @@
 #endif
 
 #define UNSET_DESC	~0ULL
+#define MT_UNKNOWN	~0U
 
 static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
 			__aligned(XLAT_TABLE_SIZE) __section("xlat_table");
@@ -55,7 +57,7 @@
 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
 	debug_print("mmap:\n");
 	mmap_region_t *mm = mmap;
-	while (mm->size) {
+	while (mm->size != 0U) {
 		debug_print(" VA:%p  PA:0x%llx  size:0x%zx  attr:0x%x\n",
 				(void *)mm->base_va, mm->base_pa,
 				mm->size, mm->attr);
@@ -69,37 +71,37 @@
 		     size_t size, unsigned int attr)
 {
 	mmap_region_t *mm = mmap;
-	mmap_region_t *mm_last = mm + ARRAY_SIZE(mmap) - 1;
-	unsigned long long end_pa = base_pa + size - 1;
-	uintptr_t end_va = base_va + size - 1;
+	const mmap_region_t *mm_last = mm + ARRAY_SIZE(mmap) - 1U;
+	unsigned long long end_pa = base_pa + size - 1U;
+	uintptr_t end_va = base_va + size - 1U;
 
 	assert(IS_PAGE_ALIGNED(base_pa));
 	assert(IS_PAGE_ALIGNED(base_va));
 	assert(IS_PAGE_ALIGNED(size));
 
-	if (!size)
+	if (size == 0U)
 		return;
 
 	assert(base_pa < end_pa); /* Check for overflows */
 	assert(base_va < end_va);
 
 	assert((base_va + (uintptr_t)size - (uintptr_t)1) <=
-					(PLAT_VIRT_ADDR_SPACE_SIZE - 1));
+					(PLAT_VIRT_ADDR_SPACE_SIZE - 1U));
 	assert((base_pa + (unsigned long long)size - 1ULL) <=
-					(PLAT_PHY_ADDR_SPACE_SIZE - 1));
+					(PLAT_PHY_ADDR_SPACE_SIZE - 1U));
 
 #if ENABLE_ASSERTIONS
 
 	/* Check for PAs and VAs overlaps with all other regions */
 	for (mm = mmap; mm->size; ++mm) {
 
-		uintptr_t mm_end_va = mm->base_va + mm->size - 1;
+		uintptr_t mm_end_va = mm->base_va + mm->size - 1U;
 
 		/*
 		 * Check if one of the regions is completely inside the other
 		 * one.
 		 */
-		int fully_overlapped_va =
+		bool fully_overlapped_va =
 			((base_va >= mm->base_va) && (end_va <= mm_end_va)) ||
 			((mm->base_va >= base_va) && (mm_end_va <= end_va));
 
@@ -122,10 +124,10 @@
 			unsigned long long mm_end_pa =
 						     mm->base_pa + mm->size - 1;
 
-			int separated_pa =
-				(end_pa < mm->base_pa) || (base_pa > mm_end_pa);
-			int separated_va =
-				(end_va < mm->base_va) || (base_va > mm_end_va);
+			bool separated_pa = (end_pa < mm->base_pa) ||
+				(base_pa > mm_end_pa);
+			bool separated_va = (end_va < mm->base_va) ||
+				(base_va > mm_end_va);
 
 			assert(separated_va && separated_pa);
 		}
@@ -136,7 +138,7 @@
 #endif /* ENABLE_ASSERTIONS */
 
 	/* Find correct place in mmap to insert new region */
-	while (mm->base_va < base_va && mm->size)
+	while ((mm->base_va < base_va) && (mm->size != 0U))
 		++mm;
 
 	/*
@@ -154,10 +156,10 @@
 		++mm;
 
 	/* Make room for new region by moving other regions up by one place */
-	memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
+	(void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
 
 	/* Check we haven't lost the empty sentinal from the end of the array */
-	assert(mm_last->size == 0);
+	assert(mm_last->size == 0U);
 
 	mm->base_pa = base_pa;
 	mm->base_va = base_va;
@@ -172,9 +174,12 @@
 
 void mmap_add(const mmap_region_t *mm)
 {
-	while (mm->size) {
-		mmap_add_region(mm->base_pa, mm->base_va, mm->size, mm->attr);
-		++mm;
+	const mmap_region_t *mm_cursor = mm;
+
+	while (mm_cursor->size != 0U) {
+		mmap_add_region(mm_cursor->base_pa, mm_cursor->base_va,
+				mm_cursor->size, mm_cursor->attr);
+		mm_cursor++;
 	}
 }
 
@@ -185,7 +190,7 @@
 	int mem_type;
 
 	/* Make sure that the granularity is fine enough to map this address. */
-	assert((addr_pa & XLAT_BLOCK_MASK(level)) == 0);
+	assert((addr_pa & XLAT_BLOCK_MASK(level)) == 0U);
 
 	desc = addr_pa;
 	/*
@@ -193,8 +198,8 @@
 	 * rest.
 	 */
 	desc |= (level == XLAT_TABLE_LEVEL_MAX) ? PAGE_DESC : BLOCK_DESC;
-	desc |= (attr & MT_NS) ? LOWER_ATTRS(NS) : 0;
-	desc |= (attr & MT_RW) ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO);
+	desc |= ((attr & MT_NS) != 0U) ? LOWER_ATTRS(NS) : 0U;
+	desc |= ((attr & MT_RW) != 0U) ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO);
 	/*
 	 * Always set the access flag, as this library assumes access flag
 	 * faults aren't managed.
@@ -239,7 +244,7 @@
 		 * For read-only memory, rely on the MT_EXECUTE/MT_EXECUTE_NEVER
 		 * attribute to figure out the value of the XN bit.
 		 */
-		if ((attr & MT_RW) || (attr & MT_EXECUTE_NEVER)) {
+		if (((attr & MT_RW) != 0U) || ((attr & MT_EXECUTE_NEVER) != 0U)) {
 			desc |= execute_never_mask;
 		}
 
@@ -253,9 +258,9 @@
 
 	debug_print((mem_type == MT_MEMORY) ? "MEM" :
 		((mem_type == MT_NON_CACHEABLE) ? "NC" : "DEV"));
-	debug_print(attr & MT_RW ? "-RW" : "-RO");
-	debug_print(attr & MT_NS ? "-NS" : "-S");
-	debug_print(attr & MT_EXECUTE_NEVER ? "-XN" : "-EXEC");
+	debug_print(((attr & MT_RW) != 0U) ? "-RW" : "-RO");
+	debug_print(((attr & MT_NS) != 0U) ? "-NS" : "-S");
+	debug_print(((attr & MT_EXECUTE_NEVER) != 0U) ? "-XN" : "-EXEC");
 	return desc;
 }
 
@@ -265,14 +270,14 @@
  *
  * On success, this function returns 0.
  * If there are partial overlaps (meaning that a smaller size is needed) or if
- * the region can't be found in the given area, it returns -1. In this case the
- * value pointed by attr should be ignored by the caller.
+ * the region can't be found in the given area, it returns MT_UNKNOWN. In this
+ * case the value pointed by attr should be ignored by the caller.
  */
-static int mmap_region_attr(mmap_region_t *mm, uintptr_t base_va,
-			    size_t size, unsigned int *attr)
+static unsigned int mmap_region_attr(const mmap_region_t *mm, uintptr_t base_va,
+				     size_t size, unsigned int *attr)
 {
 	/* Don't assume that the area is contained in the first region */
-	int ret = -1;
+	unsigned int ret = MT_UNKNOWN;
 
 	/*
 	 * Get attributes from last (innermost) region that contains the
@@ -289,26 +294,26 @@
 	 * in region 2. The loop shouldn't stop at region 2 as inner regions
 	 * have priority over outer regions, it should stop at region 5.
 	 */
-	for (;; ++mm) {
+	for ( ; ; ++mm) {
 
-		if (!mm->size)
+		if (mm->size == 0U)
 			return ret; /* Reached end of list */
 
-		if (mm->base_va > base_va + size - 1)
+		if (mm->base_va > (base_va + size - 1U))
 			return ret; /* Next region is after area so end */
 
-		if (mm->base_va + mm->size - 1 < base_va)
+		if ((mm->base_va + mm->size - 1U) < base_va)
 			continue; /* Next region has already been overtaken */
 
-		if (!ret && mm->attr == *attr)
+		if ((ret == 0U) && (mm->attr == *attr))
 			continue; /* Region doesn't override attribs so skip */
 
-		if (mm->base_va > base_va ||
-			mm->base_va + mm->size - 1 < base_va + size - 1)
-			return -1; /* Region doesn't fully cover our area */
+		if ((mm->base_va > base_va) ||
+			((mm->base_va + mm->size - 1U) < (base_va + size - 1U)))
+			return MT_UNKNOWN; /* Region doesn't fully cover area */
 
 		*attr = mm->attr;
-		ret = 0;
+		ret = 0U;
 	}
 	return ret;
 }
@@ -318,7 +323,8 @@
 					uint64_t *table,
 					unsigned int level)
 {
-	assert(level >= XLAT_TABLE_LEVEL_MIN && level <= XLAT_TABLE_LEVEL_MAX);
+	assert((level >= XLAT_TABLE_LEVEL_MIN) &&
+	       (level <= XLAT_TABLE_LEVEL_MAX));
 
 	unsigned int level_size_shift =
 		       L0_XLAT_ADDRESS_SHIFT - level * XLAT_TABLE_ENTRIES_SHIFT;
@@ -331,10 +337,10 @@
 	do  {
 		uint64_t desc = UNSET_DESC;
 
-		if (!mm->size) {
+		if (mm->size == 0U) {
 			/* Done mapping regions; finish zeroing the table */
 			desc = INVALID_DESC;
-		} else if (mm->base_va + mm->size - 1 < base_va) {
+		} else if ((mm->base_va + mm->size - 1U) < base_va) {
 			/* This area is after the region so get next region */
 			++mm;
 			continue;
@@ -343,7 +349,7 @@
 		debug_print("%s VA:%p size:0x%llx ", get_level_spacer(level),
 			(void *)base_va, (unsigned long long)level_size);
 
-		if (mm->base_va > base_va + level_size - 1) {
+		if (mm->base_va > (base_va + level_size - 1U)) {
 			/* Next region is after this area. Nothing to map yet */
 			desc = INVALID_DESC;
 		/* Make sure that the current level allows block descriptors */
@@ -354,9 +360,10 @@
 			 * it will return the innermost region's attributes.
 			 */
 			unsigned int attr;
-			int r = mmap_region_attr(mm, base_va, level_size, &attr);
+			unsigned int r = mmap_region_attr(mm, base_va,
+							  level_size, &attr);
 
-			if (!r) {
+			if (r == 0U) {
 				desc = mmap_desc(attr,
 					base_va - mm->base_va + mm->base_pa,
 					level);
@@ -365,13 +372,15 @@
 
 		if (desc == UNSET_DESC) {
 			/* Area not covered by a region so need finer table */
-			uint64_t *new_table = xlat_tables[next_xlat++];
+			uint64_t *new_table = xlat_tables[next_xlat];
+
+			next_xlat++;
 			assert(next_xlat <= MAX_XLAT_TABLES);
 			desc = TABLE_DESC | (uintptr_t)new_table;
 
 			/* Recurse to fill in new table */
 			mm = init_xlation_table_inner(mm, base_va,
-						new_table, level+1);
+						new_table, level + 1U);
 		}
 
 		debug_print("\n");
@@ -379,7 +388,7 @@
 		*table++ = desc;
 		base_va += level_size;
 	} while ((base_va & level_index_mask) &&
-		 (base_va - 1 < PLAT_VIRT_ADDR_SPACE_SIZE - 1));
+		 ((base_va - 1U) < (PLAT_VIRT_ADDR_SPACE_SIZE - 1U)));
 
 	return mm;
 }
@@ -388,15 +397,15 @@
 			unsigned int level, uintptr_t *max_va,
 			unsigned long long *max_pa)
 {
-	int el = xlat_arch_current_el();
+	unsigned int el = xlat_arch_current_el();
 
 	execute_never_mask = xlat_arch_get_xn_desc(el);
 
-	if (el == 3) {
+	if (el == 3U) {
 		ap1_mask = LOWER_ATTRS(AP_ONE_VA_RANGE_RES1);
 	} else {
-		assert(el == 1);
-		ap1_mask = 0;
+		assert(el == 1U);
+		ap1_mask = 0ULL;
 	}
 
 	init_xlation_table_inner(mmap, base_va, table, level);
diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h
index 810c48e..f882f7e 100644
--- a/lib/xlat_tables/xlat_tables_private.h
+++ b/lib/xlat_tables/xlat_tables_private.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __XLAT_TABLES_PRIVATE_H__
-#define __XLAT_TABLES_PRIVATE_H__
+#ifndef XLAT_TABLES_PRIVATE_H
+#define XLAT_TABLES_PRIVATE_H
 
 #include <cassert.h>
 #include <platform_def.h>
@@ -44,17 +44,17 @@
 void print_mmap(void);
 
 /* Returns the current Exception Level. The returned EL must be 1 or higher. */
-int xlat_arch_current_el(void);
+unsigned int xlat_arch_current_el(void);
 
 /*
  * Returns the bit mask that has to be ORed to the rest of a translation table
  * descriptor so that execution of code is prohibited at the given Exception
  * Level.
  */
-uint64_t xlat_arch_get_xn_desc(int el);
+uint64_t xlat_arch_get_xn_desc(unsigned int el);
 
 void init_xlation_table(uintptr_t base_va, uint64_t *table,
 			unsigned int level, uintptr_t *max_va,
 			unsigned long long *max_pa);
 
-#endif /* __XLAT_TABLES_PRIVATE_H__ */
+#endif /* XLAT_TABLES_PRIVATE_H */
diff --git a/lib/xlat_tables_v2/aarch32/enable_mmu.S b/lib/xlat_tables_v2/aarch32/enable_mmu.S
index 99cf088..4a4ac30 100644
--- a/lib/xlat_tables_v2/aarch32/enable_mmu.S
+++ b/lib/xlat_tables_v2/aarch32/enable_mmu.S
@@ -8,9 +8,11 @@
 #include <assert_macros.S>
 #include <xlat_tables_v2.h>
 
-	.global	enable_mmu_direct
+	.global	enable_mmu_direct_svc_mon
+	.global	enable_mmu_direct_hyp
 
-func enable_mmu_direct
+	/* void enable_mmu_direct_svc_mon(unsigned int flags) */
+func enable_mmu_direct_svc_mon
 	/* Assert that MMU is turned off */
 #if ENABLE_ASSERTIONS
 	ldcopr  r1, SCTLR
@@ -63,4 +65,56 @@
 	isb
 
 	bx	lr
-endfunc enable_mmu_direct
+endfunc enable_mmu_direct_svc_mon
+
+
+	/* void enable_mmu_direct_hyp(unsigned int flags) */
+func enable_mmu_direct_hyp
+	/* Assert that MMU is turned off */
+#if ENABLE_ASSERTIONS
+	ldcopr  r1, HSCTLR
+	tst	r1, #HSCTLR_M_BIT
+	ASM_ASSERT(eq)
+#endif
+
+	/* Invalidate TLB entries */
+	TLB_INVALIDATE(r0, TLBIALL)
+
+	mov	r3, r0
+	ldr	r0, =mmu_cfg_params
+
+	/* HMAIR0 */
+	ldr	r1, [r0, #(MMU_CFG_MAIR << 3)]
+	stcopr	r1, HMAIR0
+
+	/* HTCR */
+	ldr	r2, [r0, #(MMU_CFG_TCR << 3)]
+	stcopr	r2, HTCR
+
+	/* HTTBR */
+	ldr	r1, [r0, #(MMU_CFG_TTBR0 << 3)]
+	ldr	r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)]
+	stcopr16	r1, r2, HTTBR_64
+
+	/*
+	 * Ensure all translation table writes have drained into memory, the TLB
+	 * invalidation is complete, and translation register writes are
+	 * committed before enabling the MMU
+	 */
+	dsb	ish
+	isb
+
+	/* Enable enable MMU by honoring flags */
+	ldcopr  r1, HSCTLR
+	ldr	r2, =(HSCTLR_WXN_BIT | HSCTLR_C_BIT | HSCTLR_M_BIT)
+	orr	r1, r1, r2
+
+	/* Clear C bit if requested */
+	tst	r3, #DISABLE_DCACHE
+	bicne	r1, r1, #HSCTLR_C_BIT
+
+	stcopr	r1, HSCTLR
+	isb
+
+	bx	lr
+endfunc enable_mmu_direct_hyp
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
index 5e3220c..66938e5 100644
--- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -9,30 +9,30 @@
 #include <assert.h>
 #include <cassert.h>
 #include <platform_def.h>
-#include <utils.h>
+#include <stdbool.h>
 #include <utils_def.h>
 #include <xlat_tables_v2.h>
 #include "../xlat_tables_private.h"
 
-#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)
+#if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)
 #error ARMv7 target does not support LPAE MMU descriptors
 #endif
 
 /*
- * Returns 1 if the provided granule size is supported, 0 otherwise.
+ * Returns true if the provided granule size is supported, false otherwise.
  */
-int xlat_arch_is_granule_size_supported(size_t size)
+bool xlat_arch_is_granule_size_supported(size_t size)
 {
 	/*
 	 * The library uses the long descriptor translation table format, which
 	 * supports 4 KiB pages only.
 	 */
-	return (size == (4U * 1024U));
+	return size == PAGE_SIZE_4KB;
 }
 
 size_t xlat_arch_get_max_supported_granule_size(void)
 {
-	return 4U * 1024U;
+	return PAGE_SIZE_4KB;
 }
 
 #if ENABLE_ASSERTIONS
@@ -43,17 +43,38 @@
 }
 #endif /* ENABLE_ASSERTIONS*/
 
-int is_mmu_enabled_ctx(const xlat_ctx_t *ctx __unused)
+bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx)
 {
-	return (read_sctlr() & SCTLR_M_BIT) != 0;
+	if (ctx->xlat_regime == EL1_EL0_REGIME) {
+		assert(xlat_arch_current_el() == 1U);
+		return (read_sctlr() & SCTLR_M_BIT) != 0U;
+	} else {
+		assert(ctx->xlat_regime == EL2_REGIME);
+		assert(xlat_arch_current_el() == 2U);
+		return (read_hsctlr() & HSCTLR_M_BIT) != 0U;
+	}
 }
 
-uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime __unused)
+bool is_dcache_enabled(void)
 {
-	return UPPER_ATTRS(XN);
+	if (IS_IN_EL2()) {
+		return (read_hsctlr() & HSCTLR_C_BIT) != 0U;
+	} else {
+		return (read_sctlr() & SCTLR_C_BIT) != 0U;
+	}
 }
 
-void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime __unused)
+uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime)
+{
+	if (xlat_regime == EL1_EL0_REGIME) {
+		return UPPER_ATTRS(XN) | UPPER_ATTRS(PXN);
+	} else {
+		assert(xlat_regime == EL2_REGIME);
+		return UPPER_ATTRS(XN);
+	}
+}
+
+void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime)
 {
 	/*
 	 * Ensure the translation table write has drained into memory before
@@ -61,7 +82,12 @@
 	 */
 	dsbishst();
 
-	tlbimvaais(TLBI_ADDR(va));
+	if (xlat_regime == EL1_EL0_REGIME) {
+		tlbimvaais(TLBI_ADDR(va));
+	} else {
+		assert(xlat_regime == EL2_REGIME);
+		tlbimvahis(TLBI_ADDR(va));
+	}
 }
 
 void xlat_arch_tlbi_va_sync(void)
@@ -90,21 +116,27 @@
 	isb();
 }
 
-int xlat_arch_current_el(void)
+unsigned int xlat_arch_current_el(void)
 {
-	/*
-	 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System,
-	 * SVC, Abort, UND, IRQ and FIQ modes) execute at EL3.
-	 *
-	 * The PL1&0 translation regime in AArch32 behaves like the EL1&0 regime
-	 * in AArch64 except for the XN bits, but we set and unset them at the
-	 * same time, so there's no difference in practice.
-	 */
-	return 1;
+	if (IS_IN_HYP()) {
+		return 2U;
+	} else {
+		assert(IS_IN_SVC() || IS_IN_MON());
+		/*
+		 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor,
+		 * System, SVC, Abort, UND, IRQ and FIQ modes) execute at EL3.
+		 *
+		 * The PL1&0 translation regime in AArch32 behaves like the
+		 * EL1&0 regime in AArch64 except for the XN bits, but we set
+		 * and unset them at the same time, so there's no difference in
+		 * practice.
+		 */
+		return 1U;
+	}
 }
 
 /*******************************************************************************
- * Function for enabling the MMU in Secure PL1, assuming that the page tables
+ * Function for enabling the MMU in PL1 or PL2, assuming that the page tables
  * have already been created.
  ******************************************************************************/
 void setup_mmu_cfg(uint64_t *params, unsigned int flags,
@@ -114,8 +146,6 @@
 	uint64_t mair, ttbr0;
 	uint32_t ttbcr;
 
-	assert(IS_IN_SECURE());
-
 	/* Set attributes in the right indices of the MAIR */
 	mair = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
 	mair |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
@@ -124,18 +154,32 @@
 			ATTR_NON_CACHEABLE_INDEX);
 
 	/*
-	 * Configure the control register for stage 1 of the PL1&0 translation
-	 * regime.
+	 * Configure the control register for stage 1 of the PL1&0 or EL2
+	 * translation regimes.
 	 */
 
 	/* Use the Long-descriptor translation table format. */
 	ttbcr = TTBCR_EAE_BIT;
 
-	/*
-	 * Disable translation table walk for addresses that are translated
-	 * using TTBR1. Therefore, only TTBR0 is used.
-	 */
-	ttbcr |= TTBCR_EPD1_BIT;
+	if (xlat_regime == EL1_EL0_REGIME) {
+		assert(IS_IN_SVC() || IS_IN_MON());
+		/*
+		 * Disable translation table walk for addresses that are
+		 * translated using TTBR1. Therefore, only TTBR0 is used.
+		 */
+		ttbcr |= TTBCR_EPD1_BIT;
+	} else {
+		assert(xlat_regime == EL2_REGIME);
+		assert(IS_IN_HYP());
+
+		/*
+		 * Set HTCR bits as well. Set HTTBR table properties
+		 * as Inner & outer WBWA & shareable.
+		 */
+		ttbcr |= HTCR_RES1 |
+			 HTCR_SH0_INNER_SHAREABLE | HTCR_RGN0_OUTER_WBA |
+			 HTCR_RGN0_INNER_WBA;
+	}
 
 	/*
 	 * Limit the input address ranges and memory region sizes translated
@@ -143,20 +187,23 @@
 	 * 32 bits.
 	 */
 	if (max_va != UINT32_MAX) {
-		uintptr_t virtual_addr_space_size = max_va + 1;
+		uintptr_t virtual_addr_space_size = max_va + 1U;
+
 		assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size));
 		/*
 		 * __builtin_ctzll(0) is undefined but here we are guaranteed
 		 * that virtual_addr_space_size is in the range [1, UINT32_MAX].
 		 */
-		ttbcr |= 32 - __builtin_ctzll(virtual_addr_space_size);
+		int t0sz = 32 - __builtin_ctzll(virtual_addr_space_size);
+
+		ttbcr |= (uint32_t) t0sz;
 	}
 
 	/*
 	 * Set the cacheability and shareability attributes for memory
 	 * associated with translation table walks using TTBR0.
 	 */
-	if (flags & XLAT_TABLE_NC) {
+	if ((flags & XLAT_TABLE_NC) != 0U) {
 		/* Inner & outer non-cacheable non-shareable. */
 		ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
 			TTBCR_RGN0_INNER_NC;
diff --git a/lib/xlat_tables_v2/aarch64/enable_mmu.S b/lib/xlat_tables_v2/aarch64/enable_mmu.S
index 5c5a2a9..21717d2 100644
--- a/lib/xlat_tables_v2/aarch64/enable_mmu.S
+++ b/lib/xlat_tables_v2/aarch64/enable_mmu.S
@@ -9,6 +9,7 @@
 #include <xlat_tables_v2.h>
 
 	.global	enable_mmu_direct_el1
+	.global	enable_mmu_direct_el2
 	.global	enable_mmu_direct_el3
 
 	/* Macros to read and write to system register for a given EL. */
@@ -20,6 +21,19 @@
 	mrs	\gp_reg, \reg_name\()_el\()\el
 	.endm
 
+	.macro tlbi_invalidate_all el
+	.if \el == 1
+		TLB_INVALIDATE(vmalle1)
+	.elseif \el == 2
+		TLB_INVALIDATE(alle2)
+	.elseif \el == 3
+		TLB_INVALIDATE(alle3)
+	.else
+		.error "EL must be 1, 2 or 3"
+	.endif
+	.endm
+
+	/* void enable_mmu_direct_el<x>(unsigned int flags) */
 	.macro define_mmu_enable_func el
 	func enable_mmu_direct_\()el\el
 #if ENABLE_ASSERTIONS
@@ -27,17 +41,8 @@
 		tst	x1, #SCTLR_M_BIT
 		ASM_ASSERT(eq)
 #endif
-
-		/* Invalidate TLB entries */
-		.if \el == 1
-		TLB_INVALIDATE(vmalle1)
-		.else
-		.if \el == 3
-		TLB_INVALIDATE(alle3)
-		.else
-		.error "EL must be 1 or 3"
-		.endif
-		.endif
+		/* Invalidate all TLB entries */
+		tlbi_invalidate_all \el
 
 		mov	x7, x0
 		ldr	x0, =mmu_cfg_params
@@ -86,4 +91,5 @@
 	 *  enable_mmu_direct_el3
 	 */
 	define_mmu_enable_func 1
+	define_mmu_enable_func 2
 	define_mmu_enable_func 3
diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
index 0f289e2..d1555bf 100644
--- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
@@ -8,70 +8,71 @@
 #include <arch_helpers.h>
 #include <assert.h>
 #include <cassert.h>
+#include <stdbool.h>
 #include <sys/types.h>
 #include <utils_def.h>
 #include <xlat_tables_v2.h>
 #include "../xlat_tables_private.h"
 
 /*
- * Returns 1 if the provided granule size is supported, 0 otherwise.
+ * Returns true if the provided granule size is supported, false otherwise.
  */
-int xlat_arch_is_granule_size_supported(size_t size)
+bool xlat_arch_is_granule_size_supported(size_t size)
 {
 	u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1();
 
-	if (size == (4U * 1024U)) {
+	if (size == PAGE_SIZE_4KB) {
 		return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) &
 			 ID_AA64MMFR0_EL1_TGRAN4_MASK) ==
 			 ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED;
-	} else if (size == (16U * 1024U)) {
+	} else if (size == PAGE_SIZE_16KB) {
 		return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) &
 			 ID_AA64MMFR0_EL1_TGRAN16_MASK) ==
 			 ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED;
-	} else if (size == (64U * 1024U)) {
+	} else if (size == PAGE_SIZE_64KB) {
 		return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) &
 			 ID_AA64MMFR0_EL1_TGRAN64_MASK) ==
 			 ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED;
+	} else {
+		return 0;
 	}
-
-	return 0;
 }
 
 size_t xlat_arch_get_max_supported_granule_size(void)
 {
-	if (xlat_arch_is_granule_size_supported(64U * 1024U)) {
-		return 64U * 1024U;
-	} else if (xlat_arch_is_granule_size_supported(16U * 1024U)) {
-		return 16U * 1024U;
+	if (xlat_arch_is_granule_size_supported(PAGE_SIZE_64KB)) {
+		return PAGE_SIZE_64KB;
+	} else if (xlat_arch_is_granule_size_supported(PAGE_SIZE_16KB)) {
+		return PAGE_SIZE_16KB;
 	} else {
-		assert(xlat_arch_is_granule_size_supported(4U * 1024U));
-		return 4U * 1024U;
+		assert(xlat_arch_is_granule_size_supported(PAGE_SIZE_4KB));
+		return PAGE_SIZE_4KB;
 	}
 }
 
 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr)
 {
 	/* Physical address can't exceed 48 bits */
-	assert((max_addr & ADDR_MASK_48_TO_63) == 0);
+	assert((max_addr & ADDR_MASK_48_TO_63) == 0U);
 
 	/* 48 bits address */
-	if (max_addr & ADDR_MASK_44_TO_47)
+	if ((max_addr & ADDR_MASK_44_TO_47) != 0U)
 		return TCR_PS_BITS_256TB;
 
 	/* 44 bits address */
-	if (max_addr & ADDR_MASK_42_TO_43)
+	if ((max_addr & ADDR_MASK_42_TO_43) != 0U)
 		return TCR_PS_BITS_16TB;
 
 	/* 42 bits address */
-	if (max_addr & ADDR_MASK_40_TO_41)
+	if ((max_addr & ADDR_MASK_40_TO_41) != 0U)
 		return TCR_PS_BITS_4TB;
 
 	/* 40 bits address */
-	if (max_addr & ADDR_MASK_36_TO_39)
+	if ((max_addr & ADDR_MASK_36_TO_39) != 0U)
 		return TCR_PS_BITS_1TB;
 
 	/* 36 bits address */
-	if (max_addr & ADDR_MASK_32_TO_35)
+	if ((max_addr & ADDR_MASK_32_TO_35) != 0U)
 		return TCR_PS_BITS_64GB;
 
 	return TCR_PS_BITS_4GB;
@@ -99,15 +100,31 @@
 }
 #endif /* ENABLE_ASSERTIONS*/
 
-int is_mmu_enabled_ctx(const xlat_ctx_t *ctx)
+bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx)
 {
 	if (ctx->xlat_regime == EL1_EL0_REGIME) {
-		assert(xlat_arch_current_el() >= 1);
-		return (read_sctlr_el1() & SCTLR_M_BIT) != 0;
+		assert(xlat_arch_current_el() >= 1U);
+		return (read_sctlr_el1() & SCTLR_M_BIT) != 0U;
+	} else if (ctx->xlat_regime == EL2_REGIME) {
+		assert(xlat_arch_current_el() >= 2U);
+		return (read_sctlr_el2() & SCTLR_M_BIT) != 0U;
 	} else {
 		assert(ctx->xlat_regime == EL3_REGIME);
-		assert(xlat_arch_current_el() >= 3);
-		return (read_sctlr_el3() & SCTLR_M_BIT) != 0;
+		assert(xlat_arch_current_el() >= 3U);
+		return (read_sctlr_el3() & SCTLR_M_BIT) != 0U;
+	}
+}
+
+bool is_dcache_enabled(void)
+{
+	unsigned int el = (unsigned int)GET_EL(read_CurrentEl());
+
+	if (el == 1U) {
+		return (read_sctlr_el1() & SCTLR_C_BIT) != 0U;
+	} else if (el == 2U) {
+		return (read_sctlr_el2() & SCTLR_C_BIT) != 0U;
+	} else {
+		return (read_sctlr_el3() & SCTLR_C_BIT) != 0U;
 	}
 }
 
@@ -116,7 +133,8 @@
 	if (xlat_regime == EL1_EL0_REGIME) {
 		return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN);
 	} else {
-		assert(xlat_regime == EL3_REGIME);
+		assert((xlat_regime == EL2_REGIME) ||
+		       (xlat_regime == EL3_REGIME));
 		return UPPER_ATTRS(XN);
 	}
 }
@@ -137,11 +155,14 @@
 	 * exception level (see section D4.9.2 of the ARM ARM rev B.a).
 	 */
 	if (xlat_regime == EL1_EL0_REGIME) {
-		assert(xlat_arch_current_el() >= 1);
+		assert(xlat_arch_current_el() >= 1U);
 		tlbivaae1is(TLBI_ADDR(va));
+	} else if (xlat_regime == EL2_REGIME) {
+		assert(xlat_arch_current_el() >= 2U);
+		tlbivae2is(TLBI_ADDR(va));
 	} else {
 		assert(xlat_regime == EL3_REGIME);
-		assert(xlat_arch_current_el() >= 3);
+		assert(xlat_arch_current_el() >= 3U);
 		tlbivae3is(TLBI_ADDR(va));
 	}
 }
@@ -169,11 +190,11 @@
 	isb();
 }
 
-int xlat_arch_current_el(void)
+unsigned int xlat_arch_current_el(void)
 {
-	int el = GET_EL(read_CurrentEl());
+	unsigned int el = (unsigned int)GET_EL(read_CurrentEl());
 
-	assert(el > 0);
+	assert(el > 0U);
 
 	return el;
 }
@@ -194,22 +215,24 @@
 	 * Limit the input address ranges and memory region sizes translated
 	 * using TTBR0 to the given virtual address space size.
 	 */
-	assert(max_va < ((uint64_t) UINTPTR_MAX));
+	assert(max_va < ((uint64_t)UINTPTR_MAX));
 
-	virtual_addr_space_size = max_va + 1;
+	virtual_addr_space_size = (uintptr_t)max_va + 1U;
 	assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size));
 
 	/*
 	 * __builtin_ctzll(0) is undefined but here we are guaranteed that
 	 * virtual_addr_space_size is in the range [1,UINTPTR_MAX].
 	 */
-	tcr = (uint64_t) 64 - __builtin_ctzll(virtual_addr_space_size);
+	int t0sz = 64 - __builtin_ctzll(virtual_addr_space_size);
+
+	tcr = (uint64_t) t0sz;
 
 	/*
 	 * Set the cacheability and shareability attributes for memory
 	 * associated with translation table walks.
 	 */
-	if ((flags & XLAT_TABLE_NC) != 0) {
+	if ((flags & XLAT_TABLE_NC) != 0U) {
 		/* Inner & outer non-cacheable non-shareable. */
 		tcr |= TCR_SH_NON_SHAREABLE |
 			TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC;
@@ -231,6 +254,8 @@
 		 * that are translated using TTBR1_EL1.
 		 */
 		tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
+	} else if (xlat_regime == EL2_REGIME) {
+		tcr |= TCR_EL2_RES1 | (tcr_ps_bits << TCR_EL2_PS_SHIFT);
 	} else {
 		assert(xlat_regime == EL3_REGIME);
 		tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT);
diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c
index 76c429d..bf0cc9f 100644
--- a/lib/xlat_tables_v2/xlat_tables_context.c
+++ b/lib/xlat_tables_v2/xlat_tables_context.c
@@ -78,18 +78,30 @@
 {
 	assert(tf_xlat_ctx.xlat_regime == EL_REGIME_INVALID);
 
-	int current_el = xlat_arch_current_el();
+	unsigned int current_el = xlat_arch_current_el();
 
-	if (current_el == 1) {
+	if (current_el == 1U) {
 		tf_xlat_ctx.xlat_regime = EL1_EL0_REGIME;
+	} else if (current_el == 2U) {
+		tf_xlat_ctx.xlat_regime = EL2_REGIME;
 	} else {
-		assert(current_el == 3);
+		assert(current_el == 3U);
 		tf_xlat_ctx.xlat_regime = EL3_REGIME;
 	}
 
 	init_xlat_tables_ctx(&tf_xlat_ctx);
 }
 
+int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr)
+{
+	return xlat_get_mem_attributes_ctx(&tf_xlat_ctx, base_va, attr);
+}
+
+int xlat_change_mem_attributes(uintptr_t base_va, size_t size, uint32_t attr)
+{
+	return xlat_change_mem_attributes_ctx(&tf_xlat_ctx, base_va, size, attr);
+}
+
 /*
  * If dynamic allocation of new regions is disabled then by the time we call the
  * function enabling the MMU, we'll have registered all the memory regions to
@@ -109,12 +121,32 @@
 
 #ifdef AARCH32
 
+#if !ERROR_DEPRECATED
 void enable_mmu_secure(unsigned int flags)
 {
+	enable_mmu_svc_mon(flags);
+}
+
+void enable_mmu_direct(unsigned int flags)
+{
+	enable_mmu_direct_svc_mon(flags);
+}
+#endif
+
+void enable_mmu_svc_mon(unsigned int flags)
+{
 	setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
 		      tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
 		      tf_xlat_ctx.va_max_address, EL1_EL0_REGIME);
-	enable_mmu_direct(flags);
+	enable_mmu_direct_svc_mon(flags);
+}
+
+void enable_mmu_hyp(unsigned int flags)
+{
+	setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
+		      tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
+		      tf_xlat_ctx.va_max_address, EL2_REGIME);
+	enable_mmu_direct_hyp(flags);
 }
 
 #else
@@ -127,6 +159,14 @@
 	enable_mmu_direct_el1(flags);
 }
 
+void enable_mmu_el2(unsigned int flags)
+{
+	setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
+		      tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
+		      tf_xlat_ctx.va_max_address, EL2_REGIME);
+	enable_mmu_direct_el2(flags);
+}
+
 void enable_mmu_el3(unsigned int flags)
 {
 	setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c
index e3306e6..0340bf6 100644
--- a/lib/xlat_tables_v2/xlat_tables_core.c
+++ b/lib/xlat_tables_v2/xlat_tables_core.c
@@ -9,6 +9,7 @@
 #include <debug.h>
 #include <errno.h>
 #include <platform_def.h>
+#include <stdbool.h>
 #include <string.h>
 #include <types.h>
 #include <utils_def.h>
@@ -17,6 +18,13 @@
 
 #include "xlat_tables_private.h"
 
+/* Helper function that cleans the data cache only if it is enabled. */
+static inline void xlat_clean_dcache_range(uintptr_t addr, size_t size)
+{
+	if (is_dcache_enabled())
+		clean_dcache_range(addr, size);
+}
+
 #if PLAT_XLAT_TABLES_DYNAMIC
 
 /*
@@ -29,9 +37,9 @@
  * Returns the index of the array corresponding to the specified translation
  * table.
  */
-static int xlat_table_get_index(xlat_ctx_t *ctx, const uint64_t *table)
+static int xlat_table_get_index(const xlat_ctx_t *ctx, const uint64_t *table)
 {
-	for (unsigned int i = 0; i < ctx->tables_num; i++)
+	for (int i = 0; i < ctx->tables_num; i++)
 		if (ctx->tables[i] == table)
 			return i;
 
@@ -39,15 +47,15 @@
 	 * Maybe we were asked to get the index of the base level table, which
 	 * should never happen.
 	 */
-	assert(0);
+	assert(false);
 
 	return -1;
 }
 
 /* Returns a pointer to an empty translation table. */
-static uint64_t *xlat_table_get_empty(xlat_ctx_t *ctx)
+static uint64_t *xlat_table_get_empty(const xlat_ctx_t *ctx)
 {
-	for (unsigned int i = 0; i < ctx->tables_num; i++)
+	for (int i = 0; i < ctx->tables_num; i++)
 		if (ctx->tables_mapped_regions[i] == 0)
 			return ctx->tables[i];
 
@@ -55,21 +63,27 @@
 }
 
 /* Increments region count for a given table. */
-static void xlat_table_inc_regions_count(xlat_ctx_t *ctx, const uint64_t *table)
+static void xlat_table_inc_regions_count(const xlat_ctx_t *ctx,
+					 const uint64_t *table)
 {
-	ctx->tables_mapped_regions[xlat_table_get_index(ctx, table)]++;
+	int idx = xlat_table_get_index(ctx, table);
+
+	ctx->tables_mapped_regions[idx]++;
 }
 
 /* Decrements region count for a given table. */
-static void xlat_table_dec_regions_count(xlat_ctx_t *ctx, const uint64_t *table)
+static void xlat_table_dec_regions_count(const xlat_ctx_t *ctx,
+					 const uint64_t *table)
 {
-	ctx->tables_mapped_regions[xlat_table_get_index(ctx, table)]--;
+	int idx = xlat_table_get_index(ctx, table);
+
+	ctx->tables_mapped_regions[idx]--;
 }
 
 /* Returns 0 if the specified table isn't empty, otherwise 1. */
-static int xlat_table_is_empty(xlat_ctx_t *ctx, const uint64_t *table)
+static bool xlat_table_is_empty(const xlat_ctx_t *ctx, const uint64_t *table)
 {
-	return !ctx->tables_mapped_regions[xlat_table_get_index(ctx, table)];
+	return ctx->tables_mapped_regions[xlat_table_get_index(ctx, table)] == 0;
 }
 
 #else /* PLAT_XLAT_TABLES_DYNAMIC */
@@ -88,13 +102,13 @@
  * Returns a block/page table descriptor for the given level and attributes.
  */
 uint64_t xlat_desc(const xlat_ctx_t *ctx, uint32_t attr,
-		   unsigned long long addr_pa, int level)
+		   unsigned long long addr_pa, unsigned int level)
 {
 	uint64_t desc;
-	int mem_type;
+	uint32_t mem_type;
 
 	/* Make sure that the granularity is fine enough to map this address. */
-	assert((addr_pa & XLAT_BLOCK_MASK(level)) == 0);
+	assert((addr_pa & XLAT_BLOCK_MASK(level)) == 0U);
 
 	desc = addr_pa;
 	/*
@@ -111,8 +125,8 @@
 	 * Deduce other fields of the descriptor based on the MT_NS and MT_RW
 	 * memory region attributes.
 	 */
-	desc |= (attr & MT_NS) ? LOWER_ATTRS(NS) : 0;
-	desc |= (attr & MT_RW) ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO);
+	desc |= ((attr & MT_NS) != 0U) ? LOWER_ATTRS(NS) : 0U;
+	desc |= ((attr & MT_RW) != 0U) ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO);
 
 	/*
 	 * Do not allow unprivileged access when the mapping is for a privileged
@@ -120,7 +134,7 @@
 	 * lower exception levels, set AP[2] to AP_NO_ACCESS_UNPRIVILEGED.
 	 */
 	if (ctx->xlat_regime == EL1_EL0_REGIME) {
-		if (attr & MT_USER) {
+		if ((attr & MT_USER) != 0U) {
 			/* EL0 mapping requested, so we give User access */
 			desc |= LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED);
 		} else {
@@ -128,7 +142,8 @@
 			desc |= LOWER_ATTRS(AP_NO_ACCESS_UNPRIVILEGED);
 		}
 	} else {
-		assert(ctx->xlat_regime == EL3_REGIME);
+		assert((ctx->xlat_regime == EL2_REGIME) ||
+		       (ctx->xlat_regime == EL3_REGIME));
 		desc |= LOWER_ATTRS(AP_ONE_VA_RANGE_RES1);
 	}
 
@@ -172,7 +187,7 @@
 		 * translation regime and the policy applied in
 		 * xlat_arch_regime_get_xn_desc().
 		 */
-		if ((attr & MT_RW) || (attr & MT_EXECUTE_NEVER)) {
+		if (((attr & MT_RW) != 0U) || ((attr & MT_EXECUTE_NEVER) != 0U)) {
 			desc |= xlat_arch_regime_get_xn_desc(ctx->xlat_regime);
 		}
 
@@ -223,10 +238,10 @@
 static void xlat_tables_unmap_region(xlat_ctx_t *ctx, mmap_region_t *mm,
 				     const uintptr_t table_base_va,
 				     uint64_t *const table_base,
-				     const int table_entries,
+				     const unsigned int table_entries,
 				     const unsigned int level)
 {
-	assert(level >= ctx->base_level && level <= XLAT_TABLE_LEVEL_MAX);
+	assert((level >= ctx->base_level) && (level <= XLAT_TABLE_LEVEL_MAX));
 
 	uint64_t *subtable;
 	uint64_t desc;
@@ -234,16 +249,16 @@
 	uintptr_t table_idx_va;
 	uintptr_t table_idx_end_va; /* End VA of this entry */
 
-	uintptr_t region_end_va = mm->base_va + mm->size - 1;
+	uintptr_t region_end_va = mm->base_va + mm->size - 1U;
 
-	int table_idx;
+	unsigned int table_idx;
 
 	if (mm->base_va > table_base_va) {
 		/* Find the first index of the table affected by the region. */
 		table_idx_va = mm->base_va & ~XLAT_BLOCK_MASK(level);
 
-		table_idx = (table_idx_va - table_base_va) >>
-			    XLAT_ADDR_SHIFT(level);
+		table_idx = (unsigned int)((table_idx_va - table_base_va) >>
+			    XLAT_ADDR_SHIFT(level));
 
 		assert(table_idx < table_entries);
 	} else {
@@ -254,19 +269,18 @@
 
 	while (table_idx < table_entries) {
 
-		table_idx_end_va = table_idx_va + XLAT_BLOCK_SIZE(level) - 1;
+		table_idx_end_va = table_idx_va + XLAT_BLOCK_SIZE(level) - 1U;
 
 		desc = table_base[table_idx];
 		uint64_t desc_type = desc & DESC_MASK;
 
-		action_t action = ACTION_NONE;
+		action_t action;
 
 		if ((mm->base_va <= table_idx_va) &&
 		    (region_end_va >= table_idx_end_va)) {
-
 			/* Region covers all block */
 
-			if (level == 3) {
+			if (level == 3U) {
 				/*
 				 * Last level, only page descriptors allowed,
 				 * erase it.
@@ -293,7 +307,6 @@
 
 		} else if ((mm->base_va <= table_idx_end_va) ||
 			   (region_end_va >= table_idx_va)) {
-
 			/*
 			 * Region partially covers block.
 			 *
@@ -302,12 +315,13 @@
 			 * There must be a table descriptor here, if not there
 			 * was a problem when mapping the region.
 			 */
-
-			assert(level < 3);
-
+			assert(level < 3U);
 			assert(desc_type == TABLE_DESC);
 
 			action = ACTION_RECURSE_INTO_TABLE;
+		} else {
+			/* The region doesn't cover the block at all */
+			action = ACTION_NONE;
 		}
 
 		if (action == ACTION_WRITE_BLOCK_ENTRY) {
@@ -322,8 +336,11 @@
 			/* Recurse to write into subtable */
 			xlat_tables_unmap_region(ctx, mm, table_idx_va,
 						 subtable, XLAT_TABLE_ENTRIES,
-						 level + 1);
-
+						 level + 1U);
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+			xlat_clean_dcache_range((uintptr_t)subtable,
+				XLAT_TABLE_ENTRIES * sizeof(uint64_t));
+#endif
 			/*
 			 * If the subtable is now empty, remove its reference.
 			 */
@@ -356,12 +373,12 @@
  * specified region.
  */
 static action_t xlat_tables_map_region_action(const mmap_region_t *mm,
-		const int desc_type, const unsigned long long dest_pa,
-		const uintptr_t table_entry_base_va, const unsigned int level)
+		unsigned int desc_type, unsigned long long dest_pa,
+		uintptr_t table_entry_base_va, unsigned int level)
 {
-	uintptr_t mm_end_va = mm->base_va + mm->size - 1;
+	uintptr_t mm_end_va = mm->base_va + mm->size - 1U;
 	uintptr_t table_entry_end_va =
-			table_entry_base_va + XLAT_BLOCK_SIZE(level) - 1;
+			table_entry_base_va + XLAT_BLOCK_SIZE(level) - 1U;
 
 	/*
 	 * The descriptor types allowed depend on the current table level.
@@ -378,7 +395,7 @@
 		 * translation with this granularity in principle.
 		 */
 
-		if (level == 3) {
+		if (level == 3U) {
 			/*
 			 * Last level, only page descriptors are allowed.
 			 */
@@ -416,8 +433,8 @@
 				 * Also, check if the current level allows block
 				 * descriptors. If not, create a table instead.
 				 */
-				if ((dest_pa & XLAT_BLOCK_MASK(level)) ||
-				    (level < MIN_LVL_BLOCK_DESC) ||
+				if (((dest_pa & XLAT_BLOCK_MASK(level)) != 0U)
+				    || (level < MIN_LVL_BLOCK_DESC) ||
 				    (mm->granularity < XLAT_BLOCK_SIZE(level)))
 					return ACTION_CREATE_NEW_TABLE;
 				else
@@ -449,7 +466,7 @@
 		 * mmap region failed to detect that PA and VA must at least be
 		 * aligned to PAGE_SIZE.
 		 */
-		assert(level < 3);
+		assert(level < 3U);
 
 		if (desc_type == INVALID_DESC) {
 			/*
@@ -472,13 +489,14 @@
 			 */
 			return ACTION_RECURSE_INTO_TABLE;
 		}
-	}
+	} else {
 
-	/*
-	 * This table entry is outside of the region specified in the arguments,
-	 * don't write anything to it.
-	 */
-	return ACTION_NONE;
+		/*
+		 * This table entry is outside of the region specified in the
+		 * arguments, don't write anything to it.
+		 */
+		return ACTION_NONE;
+	}
 }
 
 /*
@@ -488,14 +506,14 @@
  * should have been mapped.
  */
 static uintptr_t xlat_tables_map_region(xlat_ctx_t *ctx, mmap_region_t *mm,
-				   const uintptr_t table_base_va,
+				   uintptr_t table_base_va,
 				   uint64_t *const table_base,
-				   const int table_entries,
-				   const unsigned int level)
+				   unsigned int table_entries,
+				   unsigned int level)
 {
-	assert(level >= ctx->base_level && level <= XLAT_TABLE_LEVEL_MAX);
+	assert((level >= ctx->base_level) && (level <= XLAT_TABLE_LEVEL_MAX));
 
-	uintptr_t mm_end_va = mm->base_va + mm->size - 1;
+	uintptr_t mm_end_va = mm->base_va + mm->size - 1U;
 
 	uintptr_t table_idx_va;
 	unsigned long long table_idx_pa;
@@ -503,20 +521,20 @@
 	uint64_t *subtable;
 	uint64_t desc;
 
-	int table_idx;
+	unsigned int table_idx;
 
 	if (mm->base_va > table_base_va) {
 		/* Find the first index of the table affected by the region. */
 		table_idx_va = mm->base_va & ~XLAT_BLOCK_MASK(level);
 
-		table_idx = (table_idx_va - table_base_va) >>
-			    XLAT_ADDR_SHIFT(level);
+		table_idx = (unsigned int)((table_idx_va - table_base_va) >>
+			    XLAT_ADDR_SHIFT(level));
 
 		assert(table_idx < table_entries);
 	} else {
 		/* Start from the beginning of the table. */
 		table_idx_va = table_base_va;
-		table_idx = 0;
+		table_idx = 0U;
 	}
 
 #if PLAT_XLAT_TABLES_DYNAMIC
@@ -531,7 +549,8 @@
 		table_idx_pa = mm->base_pa + table_idx_va - mm->base_va;
 
 		action_t action = xlat_tables_map_region_action(mm,
-			desc & DESC_MASK, table_idx_pa, table_idx_va, level);
+			(uint32_t)(desc & DESC_MASK), table_idx_pa,
+			table_idx_va, level);
 
 		if (action == ACTION_WRITE_BLOCK_ENTRY) {
 
@@ -540,6 +559,7 @@
 					  level);
 
 		} else if (action == ACTION_CREATE_NEW_TABLE) {
+			uintptr_t end_va;
 
 			subtable = xlat_table_get_empty(ctx);
 			if (subtable == NULL) {
@@ -551,20 +571,31 @@
 			table_base[table_idx] = TABLE_DESC | (unsigned long)subtable;
 
 			/* Recurse to write into subtable */
-			uintptr_t end_va = xlat_tables_map_region(ctx, mm, table_idx_va,
+			end_va = xlat_tables_map_region(ctx, mm, table_idx_va,
 					       subtable, XLAT_TABLE_ENTRIES,
-					       level + 1);
-			if (end_va != table_idx_va + XLAT_BLOCK_SIZE(level) - 1)
+					       level + 1U);
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+			xlat_clean_dcache_range((uintptr_t)subtable,
+				XLAT_TABLE_ENTRIES * sizeof(uint64_t));
+#endif
+			if (end_va !=
+				(table_idx_va + XLAT_BLOCK_SIZE(level) - 1U))
 				return end_va;
 
 		} else if (action == ACTION_RECURSE_INTO_TABLE) {
+			uintptr_t end_va;
 
 			subtable = (uint64_t *)(uintptr_t)(desc & TABLE_ADDR_MASK);
 			/* Recurse to write into subtable */
-			uintptr_t end_va =  xlat_tables_map_region(ctx, mm, table_idx_va,
+			end_va = xlat_tables_map_region(ctx, mm, table_idx_va,
 					       subtable, XLAT_TABLE_ENTRIES,
-					       level + 1);
-			if (end_va != table_idx_va + XLAT_BLOCK_SIZE(level) - 1)
+					       level + 1U);
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+			xlat_clean_dcache_range((uintptr_t)subtable,
+				XLAT_TABLE_ENTRIES * sizeof(uint64_t));
+#endif
+			if (end_va !=
+				(table_idx_va + XLAT_BLOCK_SIZE(level) - 1U))
 				return end_va;
 
 		} else {
@@ -581,7 +612,7 @@
 			break;
 	}
 
-	return table_idx_va - 1;
+	return table_idx_va - 1U;
 }
 
 /*
@@ -593,23 +624,23 @@
  *   ENOMEM: There is not enough memory in the mmap array.
  *    EPERM: Region overlaps another one in an invalid way.
  */
-static int mmap_add_region_check(xlat_ctx_t *ctx, const mmap_region_t *mm)
+static int mmap_add_region_check(const xlat_ctx_t *ctx, const mmap_region_t *mm)
 {
 	unsigned long long base_pa = mm->base_pa;
 	uintptr_t base_va = mm->base_va;
 	size_t size = mm->size;
 	size_t granularity = mm->granularity;
 
-	unsigned long long end_pa = base_pa + size - 1;
-	uintptr_t end_va = base_va + size - 1;
+	unsigned long long end_pa = base_pa + size - 1U;
+	uintptr_t end_va = base_va + size - 1U;
 
 	if (!IS_PAGE_ALIGNED(base_pa) || !IS_PAGE_ALIGNED(base_va) ||
 			!IS_PAGE_ALIGNED(size))
 		return -EINVAL;
 
-	if ((granularity != XLAT_BLOCK_SIZE(1)) &&
-		(granularity != XLAT_BLOCK_SIZE(2)) &&
-		(granularity != XLAT_BLOCK_SIZE(3))) {
+	if ((granularity != XLAT_BLOCK_SIZE(1U)) &&
+		(granularity != XLAT_BLOCK_SIZE(2U)) &&
+		(granularity != XLAT_BLOCK_SIZE(3U))) {
 		return -EINVAL;
 	}
 
@@ -624,24 +655,23 @@
 		return -ERANGE;
 
 	/* Check that there is space in the ctx->mmap array */
-	if (ctx->mmap[ctx->mmap_num - 1].size != 0)
+	if (ctx->mmap[ctx->mmap_num - 1].size != 0U)
 		return -ENOMEM;
 
 	/* Check for PAs and VAs overlaps with all other regions */
-	for (mmap_region_t *mm_cursor = ctx->mmap;
-						mm_cursor->size; ++mm_cursor) {
+	for (const mmap_region_t *mm_cursor = ctx->mmap;
+	     mm_cursor->size != 0U; ++mm_cursor) {
 
 		uintptr_t mm_cursor_end_va = mm_cursor->base_va
-							+ mm_cursor->size - 1;
+							+ mm_cursor->size - 1U;
 
 		/*
 		 * Check if one of the regions is completely inside the other
 		 * one.
 		 */
-		int fully_overlapped_va =
+		bool fully_overlapped_va =
 			((base_va >= mm_cursor->base_va) &&
 					(end_va <= mm_cursor_end_va)) ||
-
 			((mm_cursor->base_va >= base_va) &&
 						(mm_cursor_end_va <= end_va));
 
@@ -654,8 +684,8 @@
 		if (fully_overlapped_va) {
 
 #if PLAT_XLAT_TABLES_DYNAMIC
-			if ((mm->attr & MT_DYNAMIC) ||
-						(mm_cursor->attr & MT_DYNAMIC))
+			if (((mm->attr & MT_DYNAMIC) != 0U) ||
+			    ((mm_cursor->attr & MT_DYNAMIC) != 0U))
 				return -EPERM;
 #endif /* PLAT_XLAT_TABLES_DYNAMIC */
 			if ((mm_cursor->base_va - mm_cursor->base_pa) !=
@@ -674,16 +704,14 @@
 			 */
 
 			unsigned long long mm_cursor_end_pa =
-				     mm_cursor->base_pa + mm_cursor->size - 1;
+				     mm_cursor->base_pa + mm_cursor->size - 1U;
 
-			int separated_pa =
-				(end_pa < mm_cursor->base_pa) ||
+			bool separated_pa = (end_pa < mm_cursor->base_pa) ||
 				(base_pa > mm_cursor_end_pa);
-			int separated_va =
-				(end_va < mm_cursor->base_va) ||
+			bool separated_va = (end_va < mm_cursor->base_va) ||
 				(base_va > mm_cursor_end_va);
 
-			if (!(separated_va && separated_pa))
+			if (!separated_va || !separated_pa)
 				return -EPERM;
 		}
 	}
@@ -695,13 +723,13 @@
 {
 	mmap_region_t *mm_cursor = ctx->mmap, *mm_destination;
 	const mmap_region_t *mm_end = ctx->mmap + ctx->mmap_num;
-	mmap_region_t *mm_last;
-	unsigned long long end_pa = mm->base_pa + mm->size - 1;
-	uintptr_t end_va = mm->base_va + mm->size - 1;
+	const mmap_region_t *mm_last;
+	unsigned long long end_pa = mm->base_pa + mm->size - 1U;
+	uintptr_t end_va = mm->base_va + mm->size - 1U;
 	int ret;
 
 	/* Ignore empty regions */
-	if (!mm->size)
+	if (mm->size == 0U)
 		return;
 
 	/* Static regions must be added before initializing the xlat tables. */
@@ -710,7 +738,7 @@
 	ret = mmap_add_region_check(ctx, mm);
 	if (ret != 0) {
 		ERROR("mmap_add_region_check() failed. error %d\n", ret);
-		assert(0);
+		assert(false);
 		return;
 	}
 
@@ -738,13 +766,15 @@
 	 * Overlapping is only allowed for static regions.
 	 */
 
-	while ((mm_cursor->base_va + mm_cursor->size - 1) < end_va
-	       && mm_cursor->size)
+	while (((mm_cursor->base_va + mm_cursor->size - 1U) < end_va)
+	       && (mm_cursor->size != 0U)) {
 		++mm_cursor;
+	}
 
-	while ((mm_cursor->base_va + mm_cursor->size - 1 == end_va) &&
-	       (mm_cursor->size != 0U) && (mm_cursor->size < mm->size))
+	while (((mm_cursor->base_va + mm_cursor->size - 1U) == end_va) &&
+	       (mm_cursor->size != 0U) && (mm_cursor->size < mm->size)) {
 		++mm_cursor;
+	}
 
 	/*
 	 * Find the last entry marker in the mmap
@@ -763,7 +793,7 @@
 
 	/* Make room for new region by moving other regions up by one place */
 	mm_destination = mm_cursor + 1;
-	memmove(mm_destination, mm_cursor,
+	(void)memmove(mm_destination, mm_cursor,
 		(uintptr_t)mm_last - (uintptr_t)mm_cursor);
 
 	/*
@@ -783,9 +813,11 @@
 
 void mmap_add_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm)
 {
-	while (mm->size) {
-		mmap_add_region_ctx(ctx, mm);
-		mm++;
+	const mmap_region_t *mm_cursor = mm;
+
+	while (mm_cursor->size != 0U) {
+		mmap_add_region_ctx(ctx, mm_cursor);
+		mm_cursor++;
 	}
 }
 
@@ -794,13 +826,13 @@
 int mmap_add_dynamic_region_ctx(xlat_ctx_t *ctx, mmap_region_t *mm)
 {
 	mmap_region_t *mm_cursor = ctx->mmap;
-	mmap_region_t *mm_last = mm_cursor + ctx->mmap_num;
-	unsigned long long end_pa = mm->base_pa + mm->size - 1;
-	uintptr_t end_va = mm->base_va + mm->size - 1;
+	const mmap_region_t *mm_last = mm_cursor + ctx->mmap_num;
+	unsigned long long end_pa = mm->base_pa + mm->size - 1U;
+	uintptr_t end_va = mm->base_va + mm->size - 1U;
 	int ret;
 
 	/* Nothing to do */
-	if (!mm->size)
+	if (mm->size == 0U)
 		return 0;
 
 	/* Now this region is a dynamic one */
@@ -815,16 +847,18 @@
 	 * static regions in mmap_add_region_ctx().
 	 */
 
-	while ((mm_cursor->base_va + mm_cursor->size - 1)
-					< end_va && mm_cursor->size)
+	while (((mm_cursor->base_va + mm_cursor->size - 1U) < end_va)
+	       && (mm_cursor->size != 0U)) {
 		++mm_cursor;
+	}
 
-	while ((mm_cursor->base_va + mm_cursor->size - 1 == end_va)
-				&& (mm_cursor->size < mm->size))
+	while (((mm_cursor->base_va + mm_cursor->size - 1U) == end_va) &&
+	       (mm_cursor->size != 0U) && (mm_cursor->size < mm->size)) {
 		++mm_cursor;
+	}
 
 	/* Make room for new region by moving other regions up by one place */
-	memmove(mm_cursor + 1, mm_cursor,
+	(void)memmove(mm_cursor + 1U, mm_cursor,
 		     (uintptr_t)mm_last - (uintptr_t)mm_cursor);
 
 	/*
@@ -832,7 +866,7 @@
 	 * This shouldn't happen as we have checked in mmap_add_region_check
 	 * that there is free space.
 	 */
-	assert(mm_last->size == 0);
+	assert(mm_last->size == 0U);
 
 	*mm_cursor = *mm;
 
@@ -841,13 +875,16 @@
 	 * not, this region will be mapped when they are initialized.
 	 */
 	if (ctx->initialized) {
-		uintptr_t end_va = xlat_tables_map_region(ctx, mm_cursor,
-				0, ctx->base_table, ctx->base_table_entries,
+		end_va = xlat_tables_map_region(ctx, mm_cursor,
+				0U, ctx->base_table, ctx->base_table_entries,
 				ctx->base_level);
-
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+		xlat_clean_dcache_range((uintptr_t)ctx->base_table,
+				   ctx->base_table_entries * sizeof(uint64_t));
+#endif
 		/* Failed to map, remove mmap entry, unmap and return error. */
-		if (end_va != mm_cursor->base_va + mm_cursor->size - 1) {
-			memmove(mm_cursor, mm_cursor + 1,
+		if (end_va != (mm_cursor->base_va + mm_cursor->size - 1U)) {
+			(void)memmove(mm_cursor, mm_cursor + 1U,
 				(uintptr_t)mm_last - (uintptr_t)mm_cursor);
 
 			/*
@@ -862,14 +899,18 @@
 			 * entries, undo every change done up to this point.
 			 */
 			mmap_region_t unmap_mm = {
-					.base_pa = 0,
+					.base_pa = 0U,
 					.base_va = mm->base_va,
 					.size = end_va - mm->base_va,
-					.attr = 0
+					.attr = 0U
 			};
-			xlat_tables_unmap_region(ctx, &unmap_mm, 0, ctx->base_table,
-							ctx->base_table_entries, ctx->base_level);
-
+			xlat_tables_unmap_region(ctx, &unmap_mm, 0U,
+				ctx->base_table, ctx->base_table_entries,
+				ctx->base_level);
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+			xlat_clean_dcache_range((uintptr_t)ctx->base_table,
+				ctx->base_table_entries * sizeof(uint64_t));
+#endif
 			return -ENOMEM;
 		}
 
@@ -903,61 +944,65 @@
 				   size_t size)
 {
 	mmap_region_t *mm = ctx->mmap;
-	mmap_region_t *mm_last = mm + ctx->mmap_num;
+	const mmap_region_t *mm_last = mm + ctx->mmap_num;
 	int update_max_va_needed = 0;
 	int update_max_pa_needed = 0;
 
 	/* Check sanity of mmap array. */
-	assert(mm[ctx->mmap_num].size == 0);
+	assert(mm[ctx->mmap_num].size == 0U);
 
-	while (mm->size) {
+	while (mm->size != 0U) {
 		if ((mm->base_va == base_va) && (mm->size == size))
 			break;
 		++mm;
 	}
 
 	/* Check that the region was found */
-	if (mm->size == 0)
+	if (mm->size == 0U)
 		return -EINVAL;
 
 	/* If the region is static it can't be removed */
-	if (!(mm->attr & MT_DYNAMIC))
+	if ((mm->attr & MT_DYNAMIC) == 0U)
 		return -EPERM;
 
 	/* Check if this region is using the top VAs or PAs. */
-	if ((mm->base_va + mm->size - 1) == ctx->max_va)
+	if ((mm->base_va + mm->size - 1U) == ctx->max_va)
 		update_max_va_needed = 1;
-	if ((mm->base_pa + mm->size - 1) == ctx->max_pa)
+	if ((mm->base_pa + mm->size - 1U) == ctx->max_pa)
 		update_max_pa_needed = 1;
 
 	/* Update the translation tables if needed */
 	if (ctx->initialized) {
-		xlat_tables_unmap_region(ctx, mm, 0, ctx->base_table,
+		xlat_tables_unmap_region(ctx, mm, 0U, ctx->base_table,
 					 ctx->base_table_entries,
 					 ctx->base_level);
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+		xlat_clean_dcache_range((uintptr_t)ctx->base_table,
+			ctx->base_table_entries * sizeof(uint64_t));
+#endif
 		xlat_arch_tlbi_va_sync();
 	}
 
 	/* Remove this region by moving the rest down by one place. */
-	memmove(mm, mm + 1, (uintptr_t)mm_last - (uintptr_t)mm);
+	(void)memmove(mm, mm + 1U, (uintptr_t)mm_last - (uintptr_t)mm);
 
 	/* Check if we need to update the max VAs and PAs */
-	if (update_max_va_needed) {
-		ctx->max_va = 0;
+	if (update_max_va_needed == 1) {
+		ctx->max_va = 0U;
 		mm = ctx->mmap;
-		while (mm->size) {
-			if ((mm->base_va + mm->size - 1) > ctx->max_va)
-				ctx->max_va = mm->base_va + mm->size - 1;
+		while (mm->size != 0U) {
+			if ((mm->base_va + mm->size - 1U) > ctx->max_va)
+				ctx->max_va = mm->base_va + mm->size - 1U;
 			++mm;
 		}
 	}
 
-	if (update_max_pa_needed) {
-		ctx->max_pa = 0;
+	if (update_max_pa_needed == 1) {
+		ctx->max_pa = 0U;
 		mm = ctx->mmap;
-		while (mm->size) {
-			if ((mm->base_pa + mm->size - 1) > ctx->max_pa)
-				ctx->max_pa = mm->base_pa + mm->size - 1;
+		while (mm->size != 0U) {
+			if ((mm->base_pa + mm->size - 1U) > ctx->max_pa)
+				ctx->max_pa = mm->base_pa + mm->size - 1U;
 			++mm;
 		}
 	}
@@ -971,7 +1016,9 @@
 {
 	assert(ctx != NULL);
 	assert(!ctx->initialized);
-	assert(ctx->xlat_regime == EL3_REGIME || ctx->xlat_regime == EL1_EL0_REGIME);
+	assert((ctx->xlat_regime == EL3_REGIME) ||
+	       (ctx->xlat_regime == EL2_REGIME) ||
+	       (ctx->xlat_regime == EL1_EL0_REGIME));
 	assert(!is_mmu_enabled_ctx(ctx));
 
 	mmap_region_t *mm = ctx->mmap;
@@ -980,25 +1027,29 @@
 
 	/* All tables must be zeroed before mapping any region. */
 
-	for (unsigned int i = 0; i < ctx->base_table_entries; i++)
+	for (unsigned int i = 0U; i < ctx->base_table_entries; i++)
 		ctx->base_table[i] = INVALID_DESC;
 
-	for (unsigned int j = 0; j < ctx->tables_num; j++) {
+	for (int j = 0; j < ctx->tables_num; j++) {
 #if PLAT_XLAT_TABLES_DYNAMIC
 		ctx->tables_mapped_regions[j] = 0;
 #endif
-		for (unsigned int i = 0; i < XLAT_TABLE_ENTRIES; i++)
+		for (unsigned int i = 0U; i < XLAT_TABLE_ENTRIES; i++)
 			ctx->tables[j][i] = INVALID_DESC;
 	}
 
-	while (mm->size) {
-		uintptr_t end_va = xlat_tables_map_region(ctx, mm, 0, ctx->base_table,
-				ctx->base_table_entries, ctx->base_level);
-
-		if (end_va != mm->base_va + mm->size - 1) {
+	while (mm->size != 0U) {
+		uintptr_t end_va = xlat_tables_map_region(ctx, mm, 0U,
+				ctx->base_table, ctx->base_table_entries,
+				ctx->base_level);
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+		xlat_clean_dcache_range((uintptr_t)ctx->base_table,
+				   ctx->base_table_entries * sizeof(uint64_t));
+#endif
+		if (end_va != (mm->base_va + mm->size - 1U)) {
 			ERROR("Not enough memory to map region:\n"
-			      " VA:%p  PA:0x%llx  size:0x%zx  attr:0x%x\n",
-			      (void *)mm->base_va, mm->base_pa, mm->size, mm->attr);
+			      " VA:0x%lx  PA:0x%llx  size:0x%zx  attr:0x%x\n",
+			      mm->base_va, mm->base_pa, mm->size, mm->attr);
 			panic();
 		}
 
@@ -1009,7 +1060,7 @@
 	assert(ctx->max_va <= ctx->va_max_address);
 	assert(ctx->max_pa <= ctx->pa_max_address);
 
-	ctx->initialized = 1;
+	ctx->initialized = true;
 
 	xlat_tables_print(ctx);
 }
diff --git a/lib/xlat_tables_v2/xlat_tables_private.h b/lib/xlat_tables_v2/xlat_tables_private.h
index 93640dd..528996a 100644
--- a/lib/xlat_tables_v2/xlat_tables_private.h
+++ b/lib/xlat_tables_v2/xlat_tables_private.h
@@ -4,10 +4,11 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __XLAT_TABLES_PRIVATE_H__
-#define __XLAT_TABLES_PRIVATE_H__
+#ifndef XLAT_TABLES_PRIVATE_H
+#define XLAT_TABLES_PRIVATE_H
 
 #include <platform_def.h>
+#include <stdbool.h>
 #include <xlat_tables_defs.h>
 
 #if PLAT_XLAT_TABLES_DYNAMIC
@@ -35,6 +36,8 @@
 
 #endif /* PLAT_XLAT_TABLES_DYNAMIC */
 
+extern uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
+
 /*
  * Return the execute-never mask that will prevent instruction fetch at the
  * given translation regime.
@@ -61,7 +64,7 @@
 void xlat_arch_tlbi_va_sync(void);
 
 /* Print VA, PA, size and attributes of all regions in the mmap array. */
-void xlat_mmap_print(mmap_region_t *const mmap);
+void xlat_mmap_print(const mmap_region_t *mmap);
 
 /*
  * Print the current state of the translation tables by reading them from
@@ -73,14 +76,14 @@
  * Returns a block/page table descriptor for the given level and attributes.
  */
 uint64_t xlat_desc(const xlat_ctx_t *ctx, uint32_t attr,
-		   unsigned long long addr_pa, int level);
+		   unsigned long long addr_pa, unsigned int level);
 
 /*
  * Architecture-specific initialization code.
  */
 
 /* Returns the current Exception Level. The returned EL must be 1 or higher. */
-int xlat_arch_current_el(void);
+unsigned int xlat_arch_current_el(void);
 
 /*
  * Return the maximum physical address supported by the hardware.
@@ -89,9 +92,12 @@
 unsigned long long xlat_arch_get_max_supported_pa(void);
 
 /*
- * Return 1 if the MMU of the translation regime managed by the given xlat_ctx_t
- * is enabled, 0 otherwise.
+ * Returns true if the MMU of the translation regime managed by the given
+ * xlat_ctx_t is enabled, false otherwise.
  */
-int is_mmu_enabled_ctx(const xlat_ctx_t *ctx);
+bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx);
 
-#endif /* __XLAT_TABLES_PRIVATE_H__ */
+/* Returns true if the data cache is enabled at the current EL. */
+bool is_dcache_enabled(void);
+
+#endif /* XLAT_TABLES_PRIVATE_H */
diff --git a/lib/xlat_tables_v2/xlat_tables_utils.c b/lib/xlat_tables_v2/xlat_tables_utils.c
index 90a0a86..05533c6 100644
--- a/lib/xlat_tables_v2/xlat_tables_utils.c
+++ b/lib/xlat_tables_v2/xlat_tables_utils.c
@@ -9,6 +9,7 @@
 #include <debug.h>
 #include <errno.h>
 #include <platform_def.h>
+#include <stdbool.h>
 #include <types.h>
 #include <utils_def.h>
 #include <xlat_tables_defs.h>
@@ -18,7 +19,7 @@
 
 #if LOG_LEVEL < LOG_LEVEL_VERBOSE
 
-void xlat_mmap_print(__unused mmap_region_t *const mmap)
+void xlat_mmap_print(__unused const mmap_region_t *mmap)
 {
 	/* Empty */
 }
@@ -30,7 +31,7 @@
 
 #else /* if LOG_LEVEL >= LOG_LEVEL_VERBOSE */
 
-void xlat_mmap_print(mmap_region_t *const mmap)
+void xlat_mmap_print(const mmap_region_t *mmap)
 {
 	tf_printf("mmap:\n");
 	const mmap_region_t *mm = mmap;
@@ -47,7 +48,7 @@
 /* Print the attributes of the specified block descriptor. */
 static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc)
 {
-	int mem_type_index = ATTR_INDEX_GET(desc);
+	uint64_t mem_type_index = ATTR_INDEX_GET(desc);
 	int xlat_regime = ctx->xlat_regime;
 
 	if (mem_type_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
@@ -59,10 +60,10 @@
 		tf_printf("DEV");
 	}
 
-	if (xlat_regime == EL3_REGIME) {
-		/* For EL3 only check the AP[2] and XN bits. */
-		tf_printf((desc & LOWER_ATTRS(AP_RO)) ? "-RO" : "-RW");
-		tf_printf((desc & UPPER_ATTRS(XN)) ? "-XN" : "-EXEC");
+	if ((xlat_regime == EL3_REGIME) || (xlat_regime == EL2_REGIME)) {
+		/* For EL3 and EL2 only check the AP[2] and XN bits. */
+		tf_printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
+		tf_printf(((desc & UPPER_ATTRS(XN)) != 0ULL) ? "-XN" : "-EXEC");
 	} else {
 		assert(xlat_regime == EL1_EL0_REGIME);
 		/*
@@ -80,18 +81,18 @@
 
 		assert((xn_perm == xn_mask) || (xn_perm == 0ULL));
 #endif
-		tf_printf((desc & LOWER_ATTRS(AP_RO)) ? "-RO" : "-RW");
+		tf_printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
 		/* Only check one of PXN and UXN, the other one is the same. */
-		tf_printf((desc & UPPER_ATTRS(PXN)) ? "-XN" : "-EXEC");
+		tf_printf(((desc & UPPER_ATTRS(PXN)) != 0ULL) ? "-XN" : "-EXEC");
 		/*
 		 * Privileged regions can only be accessed from EL1, user
 		 * regions can be accessed from EL1 and EL0.
 		 */
-		tf_printf((desc & LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED))
+		tf_printf(((desc & LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED)) != 0ULL)
 			  ? "-USER" : "-PRIV");
 	}
 
-	tf_printf(LOWER_ATTRS(NS) & desc ? "-NS" : "-S");
+	tf_printf(((LOWER_ATTRS(NS) & desc) != 0ULL) ? "-NS" : "-S");
 }
 
 static const char * const level_spacers[] = {
@@ -108,17 +109,15 @@
  * Recursive function that reads the translation tables passed as an argument
  * and prints their status.
  */
-static void xlat_tables_print_internal(xlat_ctx_t *ctx,
-		const uintptr_t table_base_va,
-		uint64_t *const table_base, const int table_entries,
-		const unsigned int level)
+static void xlat_tables_print_internal(xlat_ctx_t *ctx, uintptr_t table_base_va,
+		const uint64_t *table_base, unsigned int table_entries,
+		unsigned int level)
 {
 	assert(level <= XLAT_TABLE_LEVEL_MAX);
 
 	uint64_t desc;
 	uintptr_t table_idx_va = table_base_va;
-	int table_idx = 0;
-
+	unsigned int table_idx = 0U;
 	size_t level_size = XLAT_BLOCK_SIZE(level);
 
 	/*
@@ -136,9 +135,9 @@
 		if ((desc & DESC_MASK) == INVALID_DESC) {
 
 			if (invalid_row_count == 0) {
-				tf_printf("%sVA:%p size:0x%zx\n",
+				tf_printf("%sVA:0x%lx size:0x%zx\n",
 					  level_spacers[level],
-					  (void *)table_idx_va, level_size);
+					  table_idx_va, level_size);
 			}
 			invalid_row_count++;
 
@@ -164,20 +163,20 @@
 				 * but instead points to the next translation
 				 * table in the translation table walk.
 				 */
-				tf_printf("%sVA:%p size:0x%zx\n",
+				tf_printf("%sVA:0x%lx size:0x%zx\n",
 					  level_spacers[level],
-					  (void *)table_idx_va, level_size);
+					  table_idx_va, level_size);
 
 				uintptr_t addr_inner = desc & TABLE_ADDR_MASK;
 
 				xlat_tables_print_internal(ctx, table_idx_va,
 					(uint64_t *)addr_inner,
-					XLAT_TABLE_ENTRIES, level + 1);
+					XLAT_TABLE_ENTRIES, level + 1U);
 			} else {
-				tf_printf("%sVA:%p PA:0x%llx size:0x%zx ",
+				tf_printf("%sVA:0x%lx PA:0x%llx size:0x%zx ",
 					  level_spacers[level],
-					  (void *)table_idx_va,
-					  (unsigned long long)(desc & TABLE_ADDR_MASK),
+					  table_idx_va,
+					  (uint64_t)(desc & TABLE_ADDR_MASK),
 					  level_size);
 				xlat_desc_print(ctx, desc);
 				tf_printf("\n");
@@ -197,8 +196,12 @@
 void xlat_tables_print(xlat_ctx_t *ctx)
 {
 	const char *xlat_regime_str;
+	int used_page_tables;
+
 	if (ctx->xlat_regime == EL1_EL0_REGIME) {
 		xlat_regime_str = "1&0";
+	} else if (ctx->xlat_regime == EL2_REGIME) {
+		xlat_regime_str = "2";
 	} else {
 		assert(ctx->xlat_regime == EL3_REGIME);
 		xlat_regime_str = "3";
@@ -206,29 +209,28 @@
 	VERBOSE("Translation tables state:\n");
 	VERBOSE("  Xlat regime:     EL%s\n", xlat_regime_str);
 	VERBOSE("  Max allowed PA:  0x%llx\n", ctx->pa_max_address);
-	VERBOSE("  Max allowed VA:  %p\n", (void *) ctx->va_max_address);
+	VERBOSE("  Max allowed VA:  0x%lx\n", ctx->va_max_address);
 	VERBOSE("  Max mapped PA:   0x%llx\n", ctx->max_pa);
-	VERBOSE("  Max mapped VA:   %p\n", (void *) ctx->max_va);
+	VERBOSE("  Max mapped VA:   0x%lx\n", ctx->max_va);
 
-	VERBOSE("  Initial lookup level: %i\n", ctx->base_level);
-	VERBOSE("  Entries @initial lookup level: %i\n",
+	VERBOSE("  Initial lookup level: %u\n", ctx->base_level);
+	VERBOSE("  Entries @initial lookup level: %u\n",
 		ctx->base_table_entries);
 
-	int used_page_tables;
 #if PLAT_XLAT_TABLES_DYNAMIC
 	used_page_tables = 0;
-	for (unsigned int i = 0; i < ctx->tables_num; ++i) {
+	for (int i = 0; i < ctx->tables_num; ++i) {
 		if (ctx->tables_mapped_regions[i] != 0)
 			++used_page_tables;
 	}
 #else
 	used_page_tables = ctx->next_table;
 #endif
-	VERBOSE("  Used %i sub-tables out of %i (spare: %i)\n",
+	VERBOSE("  Used %d sub-tables out of %d (spare: %d)\n",
 		used_page_tables, ctx->tables_num,
 		ctx->tables_num - used_page_tables);
 
-	xlat_tables_print_internal(ctx, 0, ctx->base_table,
+	xlat_tables_print_internal(ctx, 0U, ctx->base_table,
 				   ctx->base_table_entries, ctx->base_level);
 }
 
@@ -251,13 +253,13 @@
  */
 static uint64_t *find_xlat_table_entry(uintptr_t virtual_addr,
 				       void *xlat_table_base,
-				       int xlat_table_base_entries,
+				       unsigned int xlat_table_base_entries,
 				       unsigned long long virt_addr_space_size,
-				       int *out_level)
+				       unsigned int *out_level)
 {
 	unsigned int start_level;
 	uint64_t *table;
-	int entries;
+	unsigned int entries;
 
 	start_level = GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size);
 
@@ -267,9 +269,7 @@
 	for (unsigned int level = start_level;
 	     level <= XLAT_TABLE_LEVEL_MAX;
 	     ++level) {
-		int idx;
-		uint64_t desc;
-		uint64_t desc_type;
+		uint64_t idx, desc, desc_type;
 
 		idx = XLAT_TABLE_IDX(virtual_addr, level);
 		if (idx >= entries) {
@@ -310,19 +310,19 @@
 	 * This shouldn't be reached, the translation table walk should end at
 	 * most at level XLAT_TABLE_LEVEL_MAX and return from inside the loop.
 	 */
-	assert(0);
+	assert(false);
 
 	return NULL;
 }
 
 
-static int get_mem_attributes_internal(const xlat_ctx_t *ctx, uintptr_t base_va,
-		uint32_t *attributes, uint64_t **table_entry,
-		unsigned long long *addr_pa, int *table_level)
+static int xlat_get_mem_attributes_internal(const xlat_ctx_t *ctx,
+		uintptr_t base_va, uint32_t *attributes, uint64_t **table_entry,
+		unsigned long long *addr_pa, unsigned int *table_level)
 {
 	uint64_t *entry;
 	uint64_t desc;
-	int level;
+	unsigned int level;
 	unsigned long long virt_addr_space_size;
 
 	/*
@@ -330,10 +330,12 @@
 	 */
 	assert(ctx != NULL);
 	assert(ctx->initialized);
-	assert(ctx->xlat_regime == EL1_EL0_REGIME || ctx->xlat_regime == EL3_REGIME);
+	assert((ctx->xlat_regime == EL1_EL0_REGIME) ||
+	       (ctx->xlat_regime == EL2_REGIME) ||
+	       (ctx->xlat_regime == EL3_REGIME));
 
-	virt_addr_space_size = (unsigned long long)ctx->va_max_address + 1;
-	assert(virt_addr_space_size > 0);
+	virt_addr_space_size = (unsigned long long)ctx->va_max_address + 1ULL;
+	assert(virt_addr_space_size > 0U);
 
 	entry = find_xlat_table_entry(base_va,
 				ctx->base_table,
@@ -341,7 +343,7 @@
 				virt_addr_space_size,
 				&level);
 	if (entry == NULL) {
-		WARN("Address %p is not mapped.\n", (void *)base_va);
+		WARN("Address 0x%lx is not mapped.\n", base_va);
 		return -EINVAL;
 	}
 
@@ -366,9 +368,9 @@
 #endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
 
 	assert(attributes != NULL);
-	*attributes = 0;
+	*attributes = 0U;
 
-	int attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
+	uint64_t attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
 
 	if (attr_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
 		*attributes |= MT_MEMORY;
@@ -379,20 +381,21 @@
 		*attributes |= MT_DEVICE;
 	}
 
-	int ap2_bit = (desc >> AP2_SHIFT) & 1;
+	uint64_t ap2_bit = (desc >> AP2_SHIFT) & 1U;
 
 	if (ap2_bit == AP2_RW)
 		*attributes |= MT_RW;
 
 	if (ctx->xlat_regime == EL1_EL0_REGIME) {
-		int ap1_bit = (desc >> AP1_SHIFT) & 1;
+		uint64_t ap1_bit = (desc >> AP1_SHIFT) & 1U;
+
 		if (ap1_bit == AP1_ACCESS_UNPRIVILEGED)
 			*attributes |= MT_USER;
 	}
 
-	int ns_bit = (desc >> NS_SHIFT) & 1;
+	uint64_t ns_bit = (desc >> NS_SHIFT) & 1U;
 
-	if (ns_bit == 1)
+	if (ns_bit == 1U)
 		*attributes |= MT_NS;
 
 	uint64_t xn_mask = xlat_arch_regime_get_xn_desc(ctx->xlat_regime);
@@ -400,25 +403,23 @@
 	if ((desc & xn_mask) == xn_mask) {
 		*attributes |= MT_EXECUTE_NEVER;
 	} else {
-		assert((desc & xn_mask) == 0);
+		assert((desc & xn_mask) == 0U);
 	}
 
 	return 0;
 }
 
 
-int get_mem_attributes(const xlat_ctx_t *ctx, uintptr_t base_va,
-		       uint32_t *attributes)
+int xlat_get_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
+				uint32_t *attr)
 {
-	return get_mem_attributes_internal(ctx, base_va, attributes,
-					   NULL, NULL, NULL);
+	return xlat_get_mem_attributes_internal(ctx, base_va, attr,
+				NULL, NULL, NULL);
 }
 
 
-int change_mem_attributes(xlat_ctx_t *ctx,
-			uintptr_t base_va,
-			size_t size,
-			uint32_t attr)
+int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
+				   size_t size, uint32_t attr)
 {
 	/* Note: This implementation isn't optimized. */
 
@@ -426,46 +427,46 @@
 	assert(ctx->initialized);
 
 	unsigned long long virt_addr_space_size =
-		(unsigned long long)ctx->va_max_address + 1;
-	assert(virt_addr_space_size > 0);
+		(unsigned long long)ctx->va_max_address + 1U;
+	assert(virt_addr_space_size > 0U);
 
 	if (!IS_PAGE_ALIGNED(base_va)) {
-		WARN("%s: Address %p is not aligned on a page boundary.\n",
-		     __func__, (void *)base_va);
+		WARN("%s: Address 0x%lx is not aligned on a page boundary.\n",
+		     __func__, base_va);
 		return -EINVAL;
 	}
 
-	if (size == 0) {
+	if (size == 0U) {
 		WARN("%s: Size is 0.\n", __func__);
 		return -EINVAL;
 	}
 
-	if ((size % PAGE_SIZE) != 0) {
+	if ((size % PAGE_SIZE) != 0U) {
 		WARN("%s: Size 0x%zx is not a multiple of a page size.\n",
 		     __func__, size);
 		return -EINVAL;
 	}
 
-	if (((attr & MT_EXECUTE_NEVER) == 0) && ((attr & MT_RW) != 0)) {
+	if (((attr & MT_EXECUTE_NEVER) == 0U) && ((attr & MT_RW) != 0U)) {
 		WARN("%s: Mapping memory as read-write and executable not allowed.\n",
 		     __func__);
 		return -EINVAL;
 	}
 
-	int pages_count = size / PAGE_SIZE;
+	size_t pages_count = size / PAGE_SIZE;
 
-	VERBOSE("Changing memory attributes of %i pages starting from address %p...\n",
-		pages_count, (void *)base_va);
+	VERBOSE("Changing memory attributes of %zu pages starting from address 0x%lx...\n",
+		pages_count, base_va);
 
 	uintptr_t base_va_original = base_va;
 
 	/*
 	 * Sanity checks.
 	 */
-	for (int i = 0; i < pages_count; ++i) {
-		uint64_t *entry;
-		uint64_t desc;
-		int level;
+	for (size_t i = 0U; i < pages_count; ++i) {
+		const uint64_t *entry;
+		uint64_t desc, attr_index;
+		unsigned int level;
 
 		entry = find_xlat_table_entry(base_va,
 					      ctx->base_table,
@@ -473,7 +474,7 @@
 					      virt_addr_space_size,
 					      &level);
 		if (entry == NULL) {
-			WARN("Address %p is not mapped.\n", (void *)base_va);
+			WARN("Address 0x%lx is not mapped.\n", base_va);
 			return -EINVAL;
 		}
 
@@ -485,8 +486,8 @@
 		 */
 		if (((desc & DESC_MASK) != PAGE_DESC) ||
 			(level != XLAT_TABLE_LEVEL_MAX)) {
-			WARN("Address %p is not mapped at the right granularity.\n",
-			     (void *)base_va);
+			WARN("Address 0x%lx is not mapped at the right granularity.\n",
+			     base_va);
 			WARN("Granularity is 0x%llx, should be 0x%x.\n",
 			     (unsigned long long)XLAT_BLOCK_SIZE(level), PAGE_SIZE);
 			return -EINVAL;
@@ -495,11 +496,11 @@
 		/*
 		 * If the region type is device, it shouldn't be executable.
 		 */
-		int attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
+		attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
 		if (attr_index == ATTR_DEVICE_INDEX) {
-			if ((attr & MT_EXECUTE_NEVER) == 0) {
-				WARN("Setting device memory as executable at address %p.",
-				     (void *)base_va);
+			if ((attr & MT_EXECUTE_NEVER) == 0U) {
+				WARN("Setting device memory as executable at address 0x%lx.",
+				     base_va);
 				return -EINVAL;
 			}
 		}
@@ -510,14 +511,14 @@
 	/* Restore original value. */
 	base_va = base_va_original;
 
-	for (int i = 0; i < pages_count; ++i) {
+	for (unsigned int i = 0U; i < pages_count; ++i) {
 
-		uint32_t old_attr, new_attr;
-		uint64_t *entry;
-		int level;
-		unsigned long long addr_pa;
+		uint32_t old_attr = 0U, new_attr;
+		uint64_t *entry = NULL;
+		unsigned int level = 0U;
+		unsigned long long addr_pa = 0ULL;
 
-		get_mem_attributes_internal(ctx, base_va, &old_attr,
+		(void) xlat_get_mem_attributes_internal(ctx, base_va, &old_attr,
 					    &entry, &addr_pa, &level);
 
 		/*
@@ -541,7 +542,9 @@
 		 * before writing the new descriptor.
 		 */
 		*entry = INVALID_DESC;
-
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+		dccvac((uintptr_t)entry);
+#endif
 		/* Invalidate any cached copy of this mapping in the TLBs. */
 		xlat_arch_tlbi_va(base_va, ctx->xlat_regime);
 
@@ -550,7 +553,9 @@
 
 		/* Write new descriptor */
 		*entry = xlat_desc(ctx, new_attr, addr_pa, level);
-
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+		dccvac((uintptr_t)entry);
+#endif
 		base_va += PAGE_SIZE;
 	}
 
diff --git a/maintainers.rst b/maintainers.rst
index 28127f8..1424f85 100644
--- a/maintainers.rst
+++ b/maintainers.rst
@@ -34,13 +34,11 @@
 ----------------
 :M: Haojian Zhuang <haojian.zhuang@linaro.org>
 :G: `hzhuang1`_
-:F: drivers/emmc/
 :F: drivers/partition/
 :F: drivers/synopsys/emmc/
 :F: drivers/synopsys/ufs/
 :F: drivers/ufs/
 :F: include/drivers/dw_ufs.h
-:F: include/drivers/emmc.h
 :F: include/drivers/ufs.h
 :F: include/drivers/synopsys/dw_mmc.h
 
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index 1184b7a..92a0f6e 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -189,6 +189,24 @@
 
 MAKE_DEP = -Wp,-MD,$(DEP) -MT $$@ -MP
 
+
+# MAKE_C_LIB builds a C source file and generates the dependency file
+#   $(1) = output directory
+#   $(2) = source file (%.c)
+#   $(3) = library name
+define MAKE_C_LIB
+$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
+$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | lib$(3)_dirs
+	@echo "  CC      $$<"
+	$$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) $(MAKE_DEP) -c $$< -o $$@
+
+-include $(DEP)
+
+endef
+
+
 # MAKE_C builds a C source file and generates the dependency file
 #   $(1) = output directory
 #   $(2) = source file (%.c)
@@ -243,6 +261,18 @@
 
 endef
 
+# MAKE_LIB_OBJS builds both C source files
+#   $(1) = output directory
+#   $(2) = list of source files
+#   $(3) = name of the library
+define MAKE_LIB_OBJS
+        $(eval C_OBJS := $(filter %.c,$(2)))
+        $(eval REMAIN := $(filter-out %.c,$(2)))
+        $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C_LIB,$(1),$(obj),$(3))))
+
+        $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN)))
+endef
+
 
 # MAKE_OBJS builds both C and assembly source files
 #   $(1) = output directory
@@ -274,6 +304,49 @@
 # This must be set to a C string (including quotes where applicable).
 BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__
 
+.PHONY: libraries
+
+# MAKE_LIB_DIRS macro defines the target for the directory where
+# libraries are created
+define MAKE_LIB_DIRS
+        $(eval LIB_DIR    := ${BUILD_PLAT}/lib)
+        $(eval ROMLIB_DIR    := ${BUILD_PLAT}/romlib)
+        $(eval LIBWRAPPER_DIR := ${BUILD_PLAT}/libwrapper)
+        $(eval $(call MAKE_PREREQ_DIR,${LIB_DIR},${BUILD_PLAT}))
+        $(eval $(call MAKE_PREREQ_DIR,${ROMLIB_DIR},${BUILD_PLAT}))
+        $(eval $(call MAKE_PREREQ_DIR,${LIBWRAPPER_DIR},${BUILD_PLAT}))
+endef
+
+# MAKE_LIB macro defines the targets and options to build each BL image.
+# Arguments:
+#   $(1) = Library name
+define MAKE_LIB
+        $(eval BUILD_DIR  := ${BUILD_PLAT}/lib$(1))
+        $(eval LIB_DIR    := ${BUILD_PLAT}/lib)
+        $(eval ROMLIB_DIR    := ${BUILD_PLAT}/romlib)
+        $(eval SOURCES    := $(LIB$(call uppercase,$(1))_SRCS))
+        $(eval OBJS       := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES))))
+
+$(eval $(call MAKE_PREREQ_DIR,${BUILD_DIR},${BUILD_PLAT}))
+$(eval $(call MAKE_LIB_OBJS,$(BUILD_DIR),$(SOURCES),$(1)))
+
+.PHONY : lib${1}_dirs
+lib${1}_dirs: | ${BUILD_DIR} ${LIB_DIR}  ${ROMLIB_DIR} ${LIBWRAPPER_DIR}
+libraries: ${LIB_DIR}/lib$(1).a
+LDPATHS = -L${LIB_DIR}
+LDLIBS += -l$(1)
+
+ifeq ($(USE_ROMLIB),1)
+LDLIBS := -lwrappers -lc
+endif
+
+all: ${LIB_DIR}/lib$(1).a
+
+${LIB_DIR}/lib$(1).a: $(OBJS)
+	@echo "  AR      $$@"
+	$$(Q)$$(AR) cr $$@ $$?
+endef
+
 # MAKE_BL macro defines the targets and options to build each BL image.
 # Arguments:
 #   $(1) = BL stage (2, 2u, 30, 31, 32, 33)
@@ -313,7 +386,11 @@
 $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES),$(1)))
 $(eval $(call MAKE_LD,$(LINKERFILE),$(BL_LINKERFILE),$(1)))
 
-$(ELF): $(OBJS) $(LINKERFILE) | bl$(1)_dirs $(BL_LIBS)
+ifeq ($(USE_ROMLIB),1)
+$(ELF): romlib.bin
+endif
+
+$(ELF): $(OBJS) $(LINKERFILE) | bl$(1)_dirs libraries $(BL_LIBS)
 	@echo "  LD      $$@"
 ifdef MAKE_BUILD_STRINGS
 	$(call MAKE_BUILD_STRINGS, $(BUILD_DIR)/build_message.o)
@@ -323,7 +400,8 @@
 		$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -xc -c - -o $(BUILD_DIR)/build_message.o
 endif
 	$$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) -Map=$(MAPFILE) \
-		--script $(LINKERFILE) $(BUILD_DIR)/build_message.o $(OBJS) $(LDLIBS) $(BL_LIBS)
+		--script $(LINKERFILE) $(BUILD_DIR)/build_message.o \
+		$(OBJS) $(LDPATHS) $(LDLIBS) $(BL_LIBS)
 
 $(DUMP): $(ELF)
 	@echo "  OD      $$@"
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index cea8533..e4b5bdc 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -166,6 +166,9 @@
 # Build option to choose whether Trusted firmware uses Coherent memory or not.
 USE_COHERENT_MEM		:= 1
 
+# Build option to choose wheter Trusted firmware uses library at ROM
+USE_ROMLIB				:= 0
+
 # Use tbbr_oid.h instead of platform_oid.h
 USE_TBBR_DEFS			= $(ERROR_DEPRECATED)
 
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index a781c4f..3f71d73 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -67,6 +67,8 @@
  * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of
  * flash
  */
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	0
+
 #if TRUSTED_BOARD_BOOT
 #define PLAT_ARM_TRUSTED_ROM_SIZE	0x00020000
 #else
@@ -123,6 +125,15 @@
 #endif
 
 /*
+ * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
+ */
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0x1000
+#else
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0
+#endif
+
+/*
  * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
  * little space for growth.
  */
diff --git a/plat/arm/board/sgm775/fdts/sgm775_tb_fw_config.dts b/plat/arm/board/sgm775/fdts/sgm775_tb_fw_config.dts
new file mode 100644
index 0000000..9502549
--- /dev/null
+++ b/plat/arm/board/sgm775/fdts/sgm775_tb_fw_config.dts
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+	/* Platform Config */
+	plat_arm_bl2 {
+		compatible = "arm,tb_fw";
+		hw_config_addr = <0x0 0x83000000>;
+		hw_config_max_size = <0x01000000>;
+	};
+};
diff --git a/plat/arm/board/sgm775/include/platform_def.h b/plat/arm/board/sgm775/include/platform_def.h
new file mode 100644
index 0000000..babe093
--- /dev/null
+++ b/plat/arm/board/sgm775/include/platform_def.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <sgm_base_platform_def.h>
+
+#define PLAT_MAX_CPUS_PER_CLUSTER	8
+#define PLAT_MAX_PE_PER_CPU		1
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/arm/board/sgm775/platform.mk b/plat/arm/board/sgm775/platform.mk
new file mode 100644
index 0000000..71e71e1
--- /dev/null
+++ b/plat/arm/board/sgm775/platform.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/arm/css/sgm/sgm-common.mk
+
+SGM775_BASE= plat/arm/board/sgm775
+
+FDT_SOURCES += ${SGM775_BASE}/fdts/sgm775_tb_fw_config.dts
+
+PLAT_INCLUDES +=-I${SGM775_BASE}/include/
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index 9483976..d435553 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -28,15 +28,26 @@
 					bl1_tzram_layout.total_base,	\
 					bl1_tzram_layout.total_size,	\
 					MT_MEMORY | MT_RW | MT_SECURE)
-#define MAP_BL1_CODE		MAP_REGION_FLAT(			\
+/*
+ * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
+ * otherwise one region is defined containing both
+ */
+#if SEPARATE_CODE_AND_RODATA
+#define MAP_BL1_RO		MAP_REGION_FLAT(			\
 					BL_CODE_BASE,			\
 					BL1_CODE_END - BL_CODE_BASE,	\
-					MT_CODE | MT_SECURE)
-#define MAP_BL1_RO_DATA		MAP_REGION_FLAT(			\
+					MT_CODE | MT_SECURE),		\
+				MAP_REGION_FLAT(			\
 					BL1_RO_DATA_BASE,		\
 					BL1_RO_DATA_END			\
 						- BL_RO_DATA_BASE,	\
 					MT_RO_DATA | MT_SECURE)
+#else
+#define MAP_BL1_RO		MAP_REGION_FLAT(			\
+					BL_CODE_BASE,			\
+					BL1_CODE_END - BL_CODE_BASE,	\
+					MT_CODE | MT_SECURE)
+#endif
 
 /* Data structure which holds the extents of the trusted SRAM for BL1*/
 static meminfo_t bl1_tzram_layout;
@@ -105,17 +116,22 @@
 
 	const mmap_region_t bl_regions[] = {
 		MAP_BL1_TOTAL,
-		MAP_BL1_CODE,
-		MAP_BL1_RO_DATA,
+		MAP_BL1_RO,
+#if USE_ROMLIB
+		ARM_MAP_ROMLIB_CODE,
+		ARM_MAP_ROMLIB_DATA,
+ #endif
 		{0}
 	};
 
 	arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
 #ifdef AARCH32
-	enable_mmu_secure(0);
+	enable_mmu_svc_mon(0);
 #else
 	enable_mmu_el3(0);
 #endif /* AARCH32 */
+
+	arm_setup_romlib();
 }
 
 void bl1_plat_arch_setup(void)
diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c
index 1d602bb..c67ab49 100644
--- a/plat/arm/common/arm_bl2_el3_setup.c
+++ b/plat/arm/common/arm_bl2_el3_setup.c
@@ -75,15 +75,14 @@
 
 	const mmap_region_t bl_regions[] = {
 		MAP_BL2_EL3_TOTAL,
-		ARM_MAP_BL_CODE,
-		ARM_MAP_BL_RO_DATA,
+		ARM_MAP_BL_RO,
 		{0}
 	};
 
 	arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
 
 #ifdef AARCH32
-	enable_mmu_secure(0);
+	enable_mmu_svc_mon(0);
 #else
 	enable_mmu_el3(0);
 #endif
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 88c0bc9..01ae8f3 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -245,18 +245,23 @@
 
 	const mmap_region_t bl_regions[] = {
 		MAP_BL2_TOTAL,
-		ARM_MAP_BL_CODE,
-		ARM_MAP_BL_RO_DATA,
+		ARM_MAP_BL_RO,
+#if USE_ROMLIB
+		ARM_MAP_ROMLIB_CODE,
+		ARM_MAP_ROMLIB_DATA,
+#endif
 		{0}
 	};
 
 	arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
 
 #ifdef AARCH32
-	enable_mmu_secure(0);
+	enable_mmu_svc_mon(0);
 #else
 	enable_mmu_el1(0);
 #endif
+
+	arm_setup_romlib();
 }
 
 void bl2_plat_arch_setup(void)
diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c
index 2bf8a93..b518f0f 100644
--- a/plat/arm/common/arm_bl2u_setup.c
+++ b/plat/arm/common/arm_bl2u_setup.c
@@ -72,18 +72,22 @@
 
 	const mmap_region_t bl_regions[] = {
 		MAP_BL2U_TOTAL,
-		ARM_MAP_BL_CODE,
-		ARM_MAP_BL_RO_DATA,
+		ARM_MAP_BL_RO,
+#if USE_ROMLIB
+		ARM_MAP_ROMLIB_CODE,
+		ARM_MAP_ROMLIB_DATA,
+#endif
 		{0}
 	};
 
 	arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
 
 #ifdef AARCH32
-	enable_mmu_secure(0);
+	enable_mmu_svc_mon(0);
 #else
 	enable_mmu_el1(0);
 #endif
+	arm_setup_romlib();
 }
 
 void bl2u_plat_arch_setup(void)
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 557854c..c7c45b0 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -285,10 +285,18 @@
 void arm_bl31_plat_arch_setup(void)
 {
 
+#define ARM_MAP_BL_ROMLIB	MAP_REGION_FLAT(			\
+					BL31_BASE,			\
+					BL31_END - BL31_BASE,		\
+					MT_MEMORY | MT_RW | MT_SECURE)
+
 	const mmap_region_t bl_regions[] = {
 		MAP_BL31_TOTAL,
-		ARM_MAP_BL_CODE,
-		ARM_MAP_BL_RO_DATA,
+		ARM_MAP_BL_RO,
+#if USE_ROMLIB
+		ARM_MAP_ROMLIB_CODE,
+		ARM_MAP_ROMLIB_DATA,
+#endif
 #if USE_COHERENT_MEM
 		ARM_MAP_BL_COHERENT_RAM,
 #endif
@@ -298,6 +306,8 @@
 	arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
 
 	enable_mmu_el3(0);
+
+	arm_setup_romlib();
 }
 
 void bl31_plat_arch_setup(void)
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index f83005f..ed43c37 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -10,8 +10,9 @@
 #include <debug.h>
 #include <mmio.h>
 #include <plat_arm.h>
-#include <platform_def.h>
 #include <platform.h>
+#include <platform_def.h>
+#include <romlib.h>
 #include <secure_partition.h>
 
 /* Weak definitions may be overridden in specific ARM standard platform */
@@ -24,6 +25,15 @@
 #pragma weak plat_get_syscnt_freq2
 #endif
 
+
+void arm_setup_romlib(void)
+{
+#if USE_ROMLIB
+	if (!rom_lib_init(ROMLIB_VERSION))
+		panic();
+#endif
+}
+
 /*
  * Set up the page tables for the generic and platform-specific memory regions.
  * The size of the Trusted SRAM seen by the BL image must be specified as well
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 67b574d..d8eda35 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -185,8 +185,7 @@
 
 DYN_CFG_SOURCES		+=	plat/arm/common/arm_dyn_cfg.c		\
 				plat/arm/common/arm_dyn_cfg_helpers.c	\
-				common/fdt_wrappers.c			\
-				${LIBFDT_SRCS}
+				common/fdt_wrappers.c
 
 BL1_SOURCES		+=	${DYN_CFG_SOURCES}
 BL2_SOURCES		+=	${DYN_CFG_SOURCES}
diff --git a/plat/arm/common/arm_tzc_dmc500.c b/plat/arm/common/arm_tzc_dmc500.c
index 89c502c..8cb81e7 100644
--- a/plat/arm/common/arm_tzc_dmc500.c
+++ b/plat/arm/common/arm_tzc_dmc500.c
@@ -7,6 +7,7 @@
 #include <arm_def.h>
 #include <assert.h>
 #include <debug.h>
+#include <plat_arm.h>
 #include <platform_def.h>
 #include <tzc_dmc500.h>
 
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index c7f317c..5191d69 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -203,8 +203,7 @@
 {
 	const mmap_region_t bl_regions[] = {
 		MAP_BL_SP_MIN_TOTAL,
-		ARM_MAP_BL_CODE,
-		ARM_MAP_BL_RO_DATA,
+		ARM_MAP_BL_RO,
 #if USE_COHERENT_MEM
 		ARM_MAP_BL_COHERENT_RAM,
 #endif
@@ -213,5 +212,5 @@
 
 	arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
 
-	enable_mmu_secure(0);
+	enable_mmu_svc_mon(0);
 }
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index 491705d..2d42d8e 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -81,8 +81,7 @@
 
 	const mmap_region_t bl_regions[] = {
 		MAP_BL_TSP_TOTAL,
-		ARM_MAP_BL_CODE,
-		ARM_MAP_BL_RO_DATA,
+		ARM_MAP_BL_RO,
 		{0}
 	};
 
diff --git a/plat/arm/css/common/css_topology.c b/plat/arm/css/common/css_topology.c
index 42f9455..d1f1c98 100644
--- a/plat/arm/css/common/css_topology.c
+++ b/plat/arm/css/common/css_topology.c
@@ -23,6 +23,12 @@
 	if (arm_check_mpidr(mpidr) == 0) {
 #if ARM_PLAT_MT
 		assert((read_mpidr_el1() & MPIDR_MT_MASK) != 0);
+
+		/*
+		 * The DTB files don't provide the MT bit in the mpidr argument
+		 * so set it manually before calculating core position
+		 */
+		mpidr |= MPIDR_MT_MASK;
 #endif
 		return plat_arm_calc_core_pos(mpidr);
 	}
diff --git a/plat/arm/css/drivers/scp/css_pm_scmi.c b/plat/arm/css/drivers/scp/css_pm_scmi.c
index 7032267..cb39da2 100644
--- a/plat/arm/css/drivers/scp/css_pm_scmi.c
+++ b/plat/arm/css/drivers/scp/css_pm_scmi.c
@@ -79,8 +79,7 @@
  */
 void css_scp_suspend(const struct psci_power_state *target_state)
 {
-	int lvl, ret;
-	uint32_t scmi_pwr_state = 0;
+	int ret;
 
 	/* At least power domain level 0 should be specified to be suspended */
 	assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
@@ -99,7 +98,9 @@
 		}
 		return;
 	}
-
+#if !HW_ASSISTED_COHERENCY
+	int lvl;
+	uint32_t scmi_pwr_state = 0;
 	/*
 	 * If we reach here, then assert that power down at system power domain
 	 * level is running.
@@ -136,6 +137,7 @@
 				ret);
 		panic();
 	}
+#endif
 }
 
 /*
diff --git a/plat/arm/css/sgi/aarch64/sgi_helper.S b/plat/arm/css/sgi/aarch64/sgi_helper.S
index aaa5156..dd0fc5b 100644
--- a/plat/arm/css/sgi/aarch64/sgi_helper.S
+++ b/plat/arm/css/sgi/aarch64/sgi_helper.S
@@ -7,28 +7,10 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <platform_def.h>
+#include <cortex_a75.h>
 
-	.globl	plat_is_my_cpu_primary
 	.globl	plat_arm_calc_core_pos
-
-	/* -----------------------------------------------------
-	 * unsigned int plat_is_my_cpu_primary (void);
-	 *
-	 * Find out whether the current cpu is the primary
-	 * cpu (applicable only after a cold boot)
-	 * -----------------------------------------------------
-	 */
-func plat_is_my_cpu_primary
-	mov	x9, x30
-	bl	plat_my_core_pos
-	ldr	x1, =SGI_BOOT_CFG_ADDR
-	ldr	x1, [x1]
-	ubfx	x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
-			#PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
-	cmp	x0, x1
-	cset	w0, eq
-	ret	x9
-endfunc plat_is_my_cpu_primary
+	.globl	plat_reset_handler
 
 	/* -----------------------------------------------------
 	 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
@@ -65,3 +47,41 @@
 	madd    x0, x1, x5, x0
 	ret
 endfunc plat_arm_calc_core_pos
+
+	/* ------------------------------------------------------
+	 * Helper macro that reads the part number of the current
+	 * CPU and jumps to the given label if it matches the CPU
+	 * MIDR provided.
+	 *
+	 * Clobbers x0.
+	 * -----------------------------------------------------
+	 */
+	.macro  jump_if_cpu_midr _cpu_midr, _label
+	mrs	x0, midr_el1
+	ubfx	x0, x0, MIDR_PN_SHIFT, #12
+	cmp	w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+	b.eq	\_label
+	.endm
+
+	/* -----------------------------------------------------
+	 * void plat_reset_handler(void);
+	 *
+	 * Determine the CPU MIDR and disable power down bit for
+	 * that CPU.
+	 * -----------------------------------------------------
+	 */
+func plat_reset_handler
+	jump_if_cpu_midr CORTEX_A75_MIDR, A75
+	ret
+
+	/* -----------------------------------------------------
+	 * Disable CPU power down bit in power control register
+	 * -----------------------------------------------------
+	 */
+A75:
+	mrs	x0, CORTEX_A75_CPUPWRCTLR_EL1
+	bic	x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
+	msr	CORTEX_A75_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc plat_reset_handler
diff --git a/plat/arm/css/sgi/include/platform_def.h b/plat/arm/css/sgi/include/platform_def.h
index 169ae1b..c645d10 100644
--- a/plat/arm/css/sgi/include/platform_def.h
+++ b/plat/arm/css/sgi/include/platform_def.h
@@ -77,11 +77,6 @@
 					CSS_SGI_DEVICE_SIZE,	\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
-#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE	0x45400000
-#define SGI_BOOT_CFG_ADDR			0x45410000
-#define PLAT_CSS_PRIMARY_CPU_SHIFT		8
-#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH		6
-
 /* GIC related constants */
 #define PLAT_ARM_GICD_BASE		0x30000000
 #define PLAT_ARM_GICC_BASE		0x2C000000
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index e0996c7..74d255c 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -4,6 +4,8 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+CSS_USE_SCMI_SDS_DRIVER		:=	1
+
 ENABLE_PLAT_COMPAT		:=	0
 
 CSS_ENT_BASE			:=	plat/arm/css/sgi
diff --git a/plat/arm/css/sgi/sgi_topology.c b/plat/arm/css/sgi/sgi_topology.c
index 1d2e027..3f6357b 100644
--- a/plat/arm/css/sgi/sgi_topology.c
+++ b/plat/arm/css/sgi/sgi_topology.c
@@ -42,3 +42,12 @@
 {
 	return sgi_topology.plat_cluster_core_count;
 }
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[32] = {
+	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,		\
+	16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+};
diff --git a/plat/arm/css/sgm/aarch64/css_sgm_helpers.S b/plat/arm/css/sgm/aarch64/css_sgm_helpers.S
new file mode 100644
index 0000000..d9b3df6
--- /dev/null
+++ b/plat/arm/css/sgm/aarch64/css_sgm_helpers.S
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+#include <cortex_a75.h>
+#include <cortex_a55.h>
+
+	.globl	plat_arm_calc_core_pos
+	.globl	plat_reset_handler
+
+	/* ---------------------------------------------------------------------
+	 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
+	 *
+	 * Function to calculate the core position on FVP.
+	 *
+	 * (ClusterId * MAX_CPUS_PER_CLUSTER * MAX_PE_PER_CPU) +
+	 * (CPUId * MAX_PE_PER_CPU) +
+	 * ThreadId
+	 *
+	 * which can be simplified as:
+	 *
+	 * ((ClusterId * MAX_CPUS_PER_CLUSTER + CPUId) * MAX_PE_PER_CPU)
+	 * + ThreadId
+	 * ---------------------------------------------------------------------
+	 */
+func plat_arm_calc_core_pos
+	/*
+	 * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
+	 * look as if in a multi-threaded implementation.
+	 */
+	tst	x0, #MPIDR_MT_MASK
+	lsr	x3, x0, #MPIDR_AFFINITY_BITS
+	csel	x3, x3, x0, eq
+
+	/* Extract individual affinity fields from MPIDR */
+	ubfx	x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+
+	/* Compute linear position */
+	mov	x4, #PLAT_MAX_CPUS_PER_CLUSTER
+	madd	x1, x2, x4, x1
+	mov	x5, #PLAT_MAX_PE_PER_CPU
+	madd	x0, x1, x5, x0
+	ret
+endfunc plat_arm_calc_core_pos
+
+	/* ------------------------------------------------------
+	 * Helper macro that reads the part number of the current
+	 * CPU and jumps to the given label if it matches the CPU
+	 * MIDR provided.
+	 *
+	 * Clobbers x0.
+	 * -----------------------------------------------------
+	 */
+	.macro  jump_if_cpu_midr _cpu_midr, _label
+	mrs	x0, midr_el1
+	ubfx	x0, x0, MIDR_PN_SHIFT, #12
+	cmp	w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+	b.eq	\_label
+	.endm
+
+	/* -----------------------------------------------------
+	 * void plat_reset_handler(void);
+	 *
+	 * Determine the CPU MIDR and disable power down bit for
+	 * that CPU.
+	 * -----------------------------------------------------
+	 */
+func plat_reset_handler
+	jump_if_cpu_midr CORTEX_A75_MIDR, A75
+	jump_if_cpu_midr CORTEX_A55_MIDR, A55
+	ret
+
+	/* -----------------------------------------------------
+	 * Disable CPU power down bit in power control register
+	 * -----------------------------------------------------
+	 */
+A75:
+	mrs	x0, CORTEX_A75_CPUPWRCTLR_EL1
+	bic	x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
+	msr	CORTEX_A75_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+A55:
+	mrs	x0, CORTEX_A55_CPUPWRCTLR_EL1
+	bic	x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK
+	msr	CORTEX_A55_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc plat_reset_handler
diff --git a/plat/arm/css/sgm/fdts/sgm_tb_fw_config.dts b/plat/arm/css/sgm/fdts/sgm_tb_fw_config.dts
new file mode 100644
index 0000000..9502549
--- /dev/null
+++ b/plat/arm/css/sgm/fdts/sgm_tb_fw_config.dts
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+	/* Platform Config */
+	plat_arm_bl2 {
+		compatible = "arm,tb_fw";
+		hw_config_addr = <0x0 0x83000000>;
+		hw_config_max_size = <0x01000000>;
+	};
+};
diff --git a/plat/arm/css/sgm/include/plat_macros.S b/plat/arm/css/sgm/include/plat_macros.S
new file mode 100644
index 0000000..d877ef8
--- /dev/null
+++ b/plat/arm/css/sgm/include/plat_macros.S
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __PLAT_MACROS_S__
+#define __PLAT_MACROS_S__
+
+#include <cci_macros.S>
+#include <css_macros.S>
+
+/* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant platform registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ * ---------------------------------------------
+ */
+.macro plat_crash_print_regs
+css_print_gic_regs
+print_cci_regs
+.endm
+
+#endif /* __PLAT_MACROS_S__ */
diff --git a/plat/arm/css/sgm/include/platform_oid.h b/plat/arm/css/sgm/include/platform_oid.h
new file mode 100644
index 0000000..18d41e3
--- /dev/null
+++ b/plat/arm/css/sgm/include/platform_oid.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "../../../../../include/plat/arm/board/common/board_arm_oid.h"
+
+/*
+ * Required platform OIDs
+ * (Provided by included header)
+ */
diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h
new file mode 100644
index 0000000..2498430
--- /dev/null
+++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SGM_BASE_PLATFORM_DEF_H__
+#define __SGM_BASE_PLATFORM_DEF_H__
+
+#include <arm_def.h>
+#include <board_arm_def.h>
+#include <board_css_def.h>
+#include <common_def.h>
+#include <css_def.h>
+#include <soc_css_def.h>
+#include <tzc400.h>
+#include <tzc_common.h>
+
+/* CPU topology */
+#define PLAT_ARM_CLUSTER_COUNT		1
+#define PLAT_ARM_CLUSTER_CORE_COUNT	8
+#define PLATFORM_CORE_COUNT		PLAT_ARM_CLUSTER_CORE_COUNT
+
+#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL2
+#define PLAT_NUM_PWR_DOMAINS		(ARM_SYSTEM_COUNT + \
+					PLAT_ARM_CLUSTER_COUNT + \
+					PLATFORM_CORE_COUNT)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
+			CSS_G1S_IRQ_PROPS(grp), \
+			ARM_G1S_IRQ_PROPS(grp)
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE		0x30000000
+#define PLAT_ARM_GICR_BASE		0x300C0000
+#define PLAT_ARM_GICC_BASE		0x2c000000
+
+#define CSS_GIC_SIZE			0x00200000
+
+#define CSS_MAP_GIC_DEVICE		MAP_REGION_FLAT(	\
+					PLAT_ARM_GICD_BASE,	\
+					CSS_GIC_SIZE,		\
+					MT_DEVICE | MT_RW | MT_SECURE)
+
+/* Platform ID address */
+#define SSC_VERSION                     (SSC_REG_BASE + SSC_VERSION_OFFSET)
+#ifndef __ASSEMBLY__
+/* SSC_VERSION related accessors */
+/* Returns the part number of the platform */
+#define GET_PLAT_PART_NUM                                       \
+		GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
+/* Returns the configuration number of the platform */
+#define GET_PLAT_CONFIG_NUM                                     \
+		GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
+#endif /* __ASSEMBLY__ */
+
+
+/*************************************************************************
+ * Definitions common to all SGM CSS based platforms
+ *************************************************************************/
+
+/* TZC-400 related constants */
+#define PLAT_ARM_TZC_BASE		0x2a500000
+#define TZC_NSAID_ALL_AP		0  /* Note: Same as default NSAID!! */
+#define TZC_NSAID_HDLCD0		2
+#define TZC_NSAID_HDLCD1		3
+#define TZC_NSAID_GPU			9
+#define TZC_NSAID_VIDEO			10
+#define TZC_NSAID_DISP0			11
+#define TZC_NSAID_DISP1			12
+
+
+/*************************************************************************
+ * Required platform porting definitions common to all SGM CSS based
+ * platforms
+ *************************************************************************/
+
+/* MHU related constants */
+#define PLAT_CSS_MHU_BASE		0x2b1f0000
+
+#define PLAT_ARM_TRUSTED_ROM_BASE	0x00000000
+#define PLAT_ARM_TRUSTED_ROM_SIZE	0x00080000
+
+#define PLAT_ARM_CCI_BASE		0x2a000000
+
+/* Cluster to CCI slave mapping */
+#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX	6
+#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX	5
+
+/* System timer related constants */
+#define PLAT_ARM_NSTIMER_FRAME_ID	0
+
+/* TZC related constants */
+#define PLAT_ARM_TZC_NS_DEV_ACCESS	(				\
+		TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)	|	\
+		TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)	|	\
+		TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD1)	|	\
+		TZC_REGION_ACCESS_RDWR(TZC_NSAID_GPU)	|	\
+		TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIDEO)	|	\
+		TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP0)	|	\
+		TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP1))
+
+/* Display Processor register definitions to setup the NSAIDs */
+#define MALI_DP_BASE           0x2cc00000
+#define DP_NPROT_NSAID_OFFSET     0x1000c
+#define W_NPROT_NSAID_SHIFT            24
+#define LS_NPORT_NSAID_SHIFT           12
+
+/*
+ * Base address of the first memory region used for communication between AP
+ * and SCP. Used by the BootOverMHU and SCPI protocols.
+ */
+#if !CSS_USE_SCMI_SDS_DRIVER
+/*
+ * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which
+ * means the SCP/AP configuration data gets overwritten when the AP initiates
+ * communication with the SCP. The configuration data is expected to be a
+ * 32-bit word on all CSS platforms. Part of this configuration is
+ * which CPU is the primary, according to the shift and mask definitions below.
+ */
+#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE	(ARM_TRUSTED_SRAM_BASE + 0x80)
+#define PLAT_CSS_PRIMARY_CPU_SHIFT		8
+#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH		4
+#endif
+
+/*
+ * tspd support is conditional so enable this for CSS sgm platforms.
+ */
+#define SPD_tspd
+
+/*
+ * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
+ * SCP_BL2 size plus a little space for growth.
+ */
+#define PLAT_CSS_MAX_SCP_BL2_SIZE	0x15000
+
+/*
+ * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
+ * SCP_BL2U size plus a little space for growth.
+ */
+#define PLAT_CSS_MAX_SCP_BL2U_SIZE	0x15000
+
+/*
+ * Most platform porting definitions provided by included headers
+ */
+
+/*
+ * If ARM_BOARD_OPTIMISE_MEM=0 then use the default, unoptimised values
+ * defined for ARM development platforms.
+ */
+#if ARM_BOARD_OPTIMISE_MEM
+/*
+ * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
+ * plat_arm_mmap array defined for each BL stage.
+ */
+#if IMAGE_BL1
+# if TRUSTED_BOARD_BOOT
+#  define PLAT_ARM_MMAP_ENTRIES		7
+# else
+#  define PLAT_ARM_MMAP_ENTRIES		6
+# endif /* TRUSTED_BOARD_BOOT */
+#elif IMAGE_BL2
+#  define PLAT_ARM_MMAP_ENTRIES		8
+#elif IMAGE_BL2U
+#  define PLAT_ARM_MMAP_ENTRIES		4
+#elif IMAGE_BL31
+#  define PLAT_ARM_MMAP_ENTRIES		6
+#elif IMAGE_BL32
+#  define PLAT_ARM_MMAP_ENTRIES		5
+#endif
+
+/*
+ * Platform specific page table and MMU setup constants
+ */
+#if IMAGE_BL1
+# if TRUSTED_BOARD_BOOT
+#  define MAX_XLAT_TABLES		4
+# else
+#  define MAX_XLAT_TABLES		3
+#endif
+#elif IMAGE_BL2
+#  define MAX_XLAT_TABLES		4
+#elif IMAGE_BL2U
+#  define MAX_XLAT_TABLES		4
+#elif IMAGE_BL31
+#  define MAX_XLAT_TABLES		2
+#elif IMAGE_BL32
+# if ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
+#  define MAX_XLAT_TABLES		3
+# else
+#  define MAX_XLAT_TABLES		2
+# endif
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+ * plus a little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MAX_BL1_RW_SIZE	0xA000
+#else
+# define PLAT_ARM_MAX_BL1_RW_SIZE	0x7000
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MAX_BL2_SIZE		0x1D000
+#else
+# define PLAT_ARM_MAX_BL2_SIZE		0xD000
+#endif
+
+#endif /* ARM_BOARD_OPTIMISE_MEM */
+
+/*******************************************************************************
+ * Memprotect definitions
+ ******************************************************************************/
+/* PSCI memory protect definitions:
+ * This variable is stored in a non-secure flash because some ARM reference
+ * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
+ * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
+ */
+#define PLAT_ARM_MEM_PROT_ADDR		(V2M_FLASH0_BASE + \
+					 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#endif /* __SGM_BASE_PLATFORM_DEF_H__ */
diff --git a/plat/arm/css/sgm/include/sgm_plat_config.h b/plat/arm/css/sgm/include/sgm_plat_config.h
new file mode 100644
index 0000000..b171d9a
--- /dev/null
+++ b/plat/arm/css/sgm/include/sgm_plat_config.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SGM_PLAT_CONFIG_H__
+#define __SGM_PLAT_CONFIG_H__
+
+#include <arm_gic.h>
+#include <ccn.h>
+#include <gicv3.h>
+
+/* The type of interconnect */
+typedef enum {
+	ARM_CCI = 0,
+	ARM_CCN,
+	ARM_CMN
+} css_inteconn_type_t;
+
+typedef ccn_desc_t inteconn_desc_t;
+
+/* Interconnect configurations */
+typedef struct css_inteconn_config {
+	css_inteconn_type_t ip_type;
+	const inteconn_desc_t *plat_inteconn_desc;
+} css_inteconn_config_t;
+
+/* Topology configurations */
+typedef struct css_topology {
+	const unsigned char *power_tree;
+	unsigned int plat_cluster_core_count;
+} css_topology_t;
+
+typedef struct css_plat_config {
+	const gicv3_driver_data_t *gic_data;
+	const css_inteconn_config_t *inteconn;
+	const css_topology_t *topology;
+} css_plat_config_t;
+
+void plat_config_init(void);
+css_plat_config_t *get_plat_config(void);
+#endif /* __SGM_PLAT_CONFIG_H__ */
diff --git a/plat/arm/css/sgm/include/sgm_variant.h b/plat/arm/css/sgm/include/sgm_variant.h
new file mode 100644
index 0000000..a0a91b0
--- /dev/null
+++ b/plat/arm/css/sgm/include/sgm_variant.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SGM_VARIANT_H__
+#define __SGM_VARIANT_H__
+
+/* SSC_VERSION values for sgm */
+#define SGM775_SSC_VER_PART_NUM		0x0790
+
+/* DMC configuration for sgm */
+#define SGM_DMC_SIZE			0x40000
+#define SGM775_DMC_COUNT		4
+
+#endif /* __SGM_VARIANT_H__ */
diff --git a/plat/arm/css/sgm/sgm-common.mk b/plat/arm/css/sgm/sgm-common.mk
new file mode 100644
index 0000000..6a3caba
--- /dev/null
+++ b/plat/arm/css/sgm/sgm-common.mk
@@ -0,0 +1,68 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+CSS_SGM_BASE		:=	plat/arm/css/sgm
+
+PLAT_INCLUDES		:=	-I${CSS_SGM_BASE}/include
+
+PLAT_BL_COMMON_SOURCES	:=	${CSS_SGM_BASE}/sgm_mmap_config.c	\
+				${CSS_SGM_BASE}/aarch64/css_sgm_helpers.S
+
+SECURITY_SOURCES	:=	drivers/arm/tzc/tzc_dmc500.c		\
+				plat/arm/common/arm_tzc_dmc500.c 	\
+				${CSS_SGM_BASE}/sgm_security.c
+
+SGM_CPU_SOURCES		:=	lib/cpus/aarch64/cortex_a55.S		\
+				lib/cpus/aarch64/cortex_a75.S
+
+INTERCONNECT_SOURCES	:=	${CSS_SGM_BASE}/sgm_interconnect.c
+
+SGM_GIC_SOURCES		:=	drivers/arm/gic/common/gic_common.c	\
+				drivers/arm/gic/v3/gicv3_main.c		\
+				drivers/arm/gic/v3/gicv3_helpers.c	\
+				plat/common/plat_gicv3.c		\
+				plat/arm/common/arm_gicv3.c		\
+				drivers/arm/gic/v3/gic600.c		\
+				drivers/arm/gic/v3/arm_gicv3_common.c
+
+BL1_SOURCES		+=	$(SGM_CPU_SOURCES)			\
+				${INTERCONNECT_SOURCES}			\
+				${CSS_SGM_BASE}/sgm_bl1_setup.c	\
+				${CSS_SGM_BASE}/sgm_plat_config.c
+
+BL2_SOURCES		+=	${SECURITY_SOURCES}
+
+BL2U_SOURCES		+=	${SECURITY_SOURCES}
+
+BL31_SOURCES		+=	$(SGM_CPU_SOURCES)			\
+				${INTERCONNECT_SOURCES}			\
+				${SECURITY_SOURCES}			\
+				${SGM_GIC_SOURCES}			\
+				${CSS_SGM_BASE}/sgm_topology.c	\
+				${CSS_SGM_BASE}/sgm_bl31_setup.c	\
+				${CSS_SGM_BASE}/sgm_plat_config.c
+
+# sgm uses CCI-500 as Cache Coherent Interconnect
+ARM_CCI_PRODUCT_ID	:=	500
+
+# Disable the PSCI platform compatibility layer
+ENABLE_PLAT_COMPAT	:=	0
+
+# System coherency is managed in hardware
+HW_ASSISTED_COHERENCY	:=	1
+
+# When building for systems with hardware-assisted coherency, there's no need to
+# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
+USE_COHERENT_MEM	:=	0
+
+override ARM_PLAT_MT	:=	1
+
+$(eval $(call add_define,SGM_PLAT))
+
+include plat/arm/common/arm_common.mk
+include plat/arm/board/common/board_common.mk
+include plat/arm/css/common/css_common.mk
+include plat/arm/soc/common/soc_css.mk
diff --git a/plat/arm/css/sgm/sgm_bl1_setup.c b/plat/arm/css/sgm/sgm_bl1_setup.c
new file mode 100644
index 0000000..51e3e53
--- /dev/null
+++ b/plat/arm/css/sgm/sgm_bl1_setup.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl_common.h>
+#include <debug.h>
+#include <plat_arm.h>
+#include <sgm_plat_config.h>
+#include <soc_css.h>
+
+void bl1_early_platform_setup(void)
+{
+	/* Initialize the platform configuration structure */
+	plat_config_init();
+
+	arm_bl1_early_platform_setup();
+
+#if !HW_ASSISTED_COHERENCY
+	/*
+	 * Initialize Interconnect for this cluster during cold boot.
+	 * No need for locks as no other CPU is active.
+	 */
+	plat_arm_interconnect_init();
+	/*
+	 * Enable Interconnect coherency for the primary CPU's cluster.
+	 */
+	plat_arm_interconnect_enter_coherency();
+#endif
+}
diff --git a/plat/arm/css/sgm/sgm_bl31_setup.c b/plat/arm/css/sgm/sgm_bl31_setup.c
new file mode 100644
index 0000000..a55176a
--- /dev/null
+++ b/plat/arm/css/sgm/sgm_bl31_setup.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl_common.h>
+#include <debug.h>
+#include <plat_arm.h>
+#include <sgm_plat_config.h>
+
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
+{
+	uint32_t plat_version;
+	bl_params_node_t *bl_params;
+
+	bl_params = ((bl_params_t *)arg0)->head;
+
+	/* Initialize the platform configuration structure */
+	plat_config_init();
+
+	while (bl_params) {
+		if (bl_params->image_id == BL33_IMAGE_ID) {
+			plat_version = mmio_read_32(SSC_VERSION);
+			bl_params->ep_info->args.arg2 = plat_version;
+			break;
+		}
+
+		bl_params = bl_params->next_params_info;
+	}
+
+	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+}
diff --git a/plat/arm/css/sgm/sgm_interconnect.c b/plat/arm/css/sgm/sgm_interconnect.c
new file mode 100644
index 0000000..301ea84
--- /dev/null
+++ b/plat/arm/css/sgm/sgm_interconnect.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * As the SGM platform supports FCM (with automatic interconnect
+ * enter/exit), we should not do anything in these interface functions.
+ * They are used to override the weak functions in cci drivers.
+ */
+
+/******************************************************************************
+ * Helper function to initialize ARM interconnect driver.
+ *****************************************************************************/
+void plat_arm_interconnect_init(void)
+{
+}
+
+/******************************************************************************
+ * Helper function to place current master into coherency
+ *****************************************************************************/
+void plat_arm_interconnect_enter_coherency(void)
+{
+}
+
+/******************************************************************************
+ * Helper function to remove current master from coherency
+ *****************************************************************************/
+void plat_arm_interconnect_exit_coherency(void)
+{
+}
diff --git a/plat/arm/css/sgm/sgm_mmap_config.c b/plat/arm/css/sgm/sgm_mmap_config.c
new file mode 100644
index 0000000..009ee64
--- /dev/null
+++ b/plat/arm/css/sgm/sgm_mmap_config.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arm_def.h>
+#include <bl_common.h>
+#include <debug.h>
+#include <plat_arm.h>
+#include <platform_def.h>
+#include <sgm_variant.h>
+
+/*
+ * Table of regions for different BL stages to map using the MMU.
+ * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
+ * arm_configure_mmu_elx() will give the available subset of that.
+ */
+#if IMAGE_BL1
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	V2M_MAP_FLASH0_RO,
+	V2M_MAP_IOFPGA,
+	CSS_MAP_DEVICE,
+	CSS_MAP_GIC_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+#if TRUSTED_BOARD_BOOT
+	ARM_MAP_NS_DRAM1,
+#endif
+	{0}
+};
+#endif
+#if IMAGE_BL2
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	V2M_MAP_FLASH0_RO,
+	V2M_MAP_IOFPGA,
+	CSS_MAP_DEVICE,
+	CSS_MAP_GIC_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+	ARM_MAP_NS_DRAM1,
+	ARM_MAP_TSP_SEC_MEM,
+#ifdef SPD_opteed
+	ARM_OPTEE_PAGEABLE_LOAD_MEM,
+#endif
+	{0}
+};
+#endif
+#if IMAGE_BL2U
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	CSS_MAP_DEVICE,
+	CSS_MAP_GIC_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+	{0}
+};
+#endif
+#if IMAGE_BL31
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	V2M_MAP_IOFPGA,
+	CSS_MAP_DEVICE,
+	CSS_MAP_GIC_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+	{0}
+};
+#endif
+#if IMAGE_BL32
+const mmap_region_t plat_arm_mmap[] = {
+	V2M_MAP_IOFPGA,
+	CSS_MAP_DEVICE,
+	CSS_MAP_GIC_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+	{0}
+};
+#endif
+
+ARM_CASSERT_MMAP
+
+const mmap_region_t *plat_arm_get_mmap(void)
+{
+	return plat_arm_mmap;
+}
diff --git a/plat/arm/css/sgm/sgm_plat_config.c b/plat/arm/css/sgm/sgm_plat_config.c
new file mode 100644
index 0000000..809edf6
--- /dev/null
+++ b/plat/arm/css/sgm/sgm_plat_config.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <debug.h>
+#include <plat_arm.h>
+#include <platform_def.h>
+#include <sgm_plat_config.h>
+#include <sgm_variant.h>
+#include <string.h>
+
+static css_plat_config_t *css_plat_info;
+
+/* Interconnect */
+const css_inteconn_config_t sgm_inteconn = {
+	.ip_type = ARM_CCI,
+	.plat_inteconn_desc = NULL
+};
+
+/* Special definition for SGM775 */
+/* Topology configuration for SGM775 */
+const unsigned char sgm775_power_domain_tree_desc[] = {
+	/* No of root nodes */
+	ARM_SYSTEM_COUNT,
+	/* No of children for the root node */
+	PLAT_ARM_CLUSTER_COUNT,
+	/* No of children for the first cluster node */
+	PLAT_ARM_CLUSTER_CORE_COUNT,
+};
+
+const css_topology_t sgm775_topology = {
+	.power_tree = sgm775_power_domain_tree_desc,
+	.plat_cluster_core_count = PLAT_ARM_CLUSTER_CORE_COUNT
+};
+
+/* Configuration structure for SGM775 */
+css_plat_config_t sgm775_config = {
+	.inteconn = &sgm_inteconn,
+	.topology = &sgm775_topology
+};
+
+/*******************************************************************************
+ * This function initializes the platform structure.
+ ******************************************************************************/
+void plat_config_init(void)
+{
+	/* Get the platform configurations */
+	switch (GET_PLAT_PART_NUM) {
+	case SGM775_SSC_VER_PART_NUM:
+		css_plat_info = &sgm775_config;
+
+		break;
+	default:
+		ERROR("Not a valid sgm variant!\n");
+		panic();
+	}
+}
+
+/*******************************************************************************
+ * This function returns the platform structure pointer.
+ ******************************************************************************/
+css_plat_config_t *get_plat_config(void)
+{
+	assert(css_plat_info != NULL);
+	return css_plat_info;
+}
diff --git a/plat/arm/css/sgm/sgm_security.c b/plat/arm/css/sgm/sgm_security.c
new file mode 100644
index 0000000..7f98060
--- /dev/null
+++ b/plat/arm/css/sgm/sgm_security.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <plat_arm.h>
+#include <sgm_variant.h>
+#include <soc_css.h>
+#include <tzc_dmc500.h>
+
+/* Is populated with the DMC-500 controllers base addresses */
+static tzc_dmc500_driver_data_t plat_driver_data;
+
+void plat_sgm_dp_security_setup(void)
+{
+	unsigned int nprot_nsaid;
+
+	/*
+	 * At reset the Mali display processors start with NSAIDs set to zero
+	 * so the firmware must set them up to the expected values for ARM sgm
+	 * platforms.
+	 */
+
+	nprot_nsaid = mmio_read_32(MALI_DP_BASE + DP_NPROT_NSAID_OFFSET);
+	nprot_nsaid &= ~((0xF << W_NPROT_NSAID_SHIFT) |
+			(0xF << LS_NPORT_NSAID_SHIFT));
+	nprot_nsaid |= ((TZC_NSAID_DISP1 << W_NPROT_NSAID_SHIFT) |
+			(TZC_NSAID_DISP0 << LS_NPORT_NSAID_SHIFT));
+	mmio_write_32(MALI_DP_BASE + DP_NPROT_NSAID_OFFSET, nprot_nsaid);
+}
+
+void plat_arm_security_setup(void)
+{
+	unsigned int i;
+	unsigned int part_num = GET_PLAT_PART_NUM;
+
+	INFO("part_num: 0x%x\n", part_num);
+
+	/*
+	 * Initialise plat_driver_data with platform specific DMC_BASE
+	 * addresses
+	 */
+	switch (part_num) {
+	case SGM775_SSC_VER_PART_NUM:
+		for (i = 0; i < SGM775_DMC_COUNT; i++)
+			plat_driver_data.dmc_base[i] = PLAT_ARM_TZC_BASE
+					+ SGM_DMC_SIZE * i;
+		plat_driver_data.dmc_count = SGM775_DMC_COUNT;
+		break;
+	default:
+		/* Unexpected platform */
+		ERROR("Unexpected platform\n");
+		panic();
+	}
+	/* Initialize the TrustZone Controller in DMC-500 */
+	arm_tzc_dmc500_setup(&plat_driver_data, NULL);
+
+	/* Do DP NSAID setup */
+	plat_sgm_dp_security_setup();
+	/* Do ARM CSS SoC security setup */
+	soc_css_security_setup();
+}
diff --git a/plat/arm/css/sgm/sgm_topology.c b/plat/arm/css/sgm/sgm_topology.c
new file mode 100644
index 0000000..ce72464
--- /dev/null
+++ b/plat/arm/css/sgm/sgm_topology.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat_arm.h>
+#include <sgm_plat_config.h>
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	return get_plat_config()->topology->power_tree;
+}
+
+/*******************************************************************************
+ * This function returns the core count within the cluster corresponding to
+ * `mpidr`.
+ ******************************************************************************/
+unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
+{
+	return get_plat_config()->topology->plat_cluster_core_count;
+}
+
+/*
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ */
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = {
+			0, 1, 2, 3, 4, 5, 6, 7 };
diff --git a/plat/arm/css/sgm/tsp/sgm_tsp_setup.c b/plat/arm/css/sgm/tsp/sgm_tsp_setup.c
new file mode 100644
index 0000000..39bba94
--- /dev/null
+++ b/plat/arm/css/sgm/tsp/sgm_tsp_setup.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat_arm.h>
+#include <sgm_plat_config.h>
+
+void tsp_early_platform_setup(void)
+{
+	/* Initialize the platform configuration structure */
+	plat_config_init();
+
+	arm_tsp_early_platform_setup();
+}
diff --git a/plat/arm/css/sgm/tsp/tsp-sgm.mk b/plat/arm/css/sgm/tsp/tsp-sgm.mk
new file mode 100644
index 0000000..a9e4131
--- /dev/null
+++ b/plat/arm/css/sgm/tsp/tsp-sgm.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL32_SOURCES		+= 	${SGM_GIC_SOURCES}			\
+				${CSS_SGM_BASE}/sgm_plat_config.c	\
+				plat/arm/board/sgm/tsp/sgm_tsp_setup.c
+
+include plat/arm/common/tsp/arm_tsp.mk
diff --git a/plat/common/aarch32/plat_common.c b/plat/common/aarch32/plat_common.c
index 4f27149..16c2b5c 100644
--- a/plat/common/aarch32/plat_common.c
+++ b/plat/common/aarch32/plat_common.c
@@ -17,5 +17,5 @@
 
 void bl32_plat_enable_mmu(uint32_t flags)
 {
-	enable_mmu_secure(flags);
+	enable_mmu_svc_mon(flags);
 }
diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c
index da6f6a5..ec779f4 100644
--- a/plat/hisilicon/hikey/hikey_bl1_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl1_setup.c
@@ -10,11 +10,11 @@
 #include <console.h>
 #include <debug.h>
 #include <dw_mmc.h>
-#include <emmc.h>
 #include <errno.h>
 #include <hi6220.h>
 #include <hikey_def.h>
 #include <hikey_layout.h>
+#include <mmc.h>
 #include <mmio.h>
 #include <platform.h>
 #include <string.h>
@@ -97,6 +97,7 @@
 void bl1_platform_setup(void)
 {
 	dw_mmc_params_t params;
+	struct mmc_device_info info;
 
 	assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) &&
 	       ((SRAM_BASE + SRAM_SIZE) >=
@@ -115,9 +116,10 @@
 	params.desc_base = HIKEY_BL1_MMC_DESC_BASE;
 	params.desc_size = 1 << 20;
 	params.clk_rate = 24 * 1000 * 1000;
-	params.bus_width = EMMC_BUS_WIDTH_8;
-	params.flags = EMMC_FLAG_CMD23;
-	dw_mmc_init(&params);
+	params.bus_width = MMC_BUS_WIDTH_8;
+	params.flags = MMC_FLAG_CMD23;
+	info.mmc_dev_type = MMC_IS_EMMC;
+	dw_mmc_init(&params, &info);
 
 	hikey_io_setup();
 }
diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c
index a3fc607..aad350b 100644
--- a/plat/hisilicon/hikey/hikey_bl2_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl2_setup.c
@@ -11,11 +11,11 @@
 #include <debug.h>
 #include <desc_image_load.h>
 #include <dw_mmc.h>
-#include <emmc.h>
 #include <errno.h>
 #include <hi6220.h>
 #include <hisi_mcu.h>
 #include <hisi_sram_map.h>
+#include <mmc.h>
 #include <mmio.h>
 #ifdef SPD_opteed
 #include <optee_utils.h>
@@ -299,6 +299,7 @@
 void bl2_platform_setup(void)
 {
 	dw_mmc_params_t params;
+	struct mmc_device_info info;
 
 	hikey_sp804_init();
 	hikey_gpio_init();
@@ -328,9 +329,10 @@
 	params.desc_base = HIKEY_MMC_DESC_BASE;
 	params.desc_size = 1 << 20;
 	params.clk_rate = 24 * 1000 * 1000;
-	params.bus_width = EMMC_BUS_WIDTH_8;
-	params.flags = EMMC_FLAG_CMD23;
-	dw_mmc_init(&params);
+	params.bus_width = MMC_BUS_WIDTH_8;
+	params.flags = MMC_FLAG_CMD23;
+	info.mmc_dev_type = MMC_IS_EMMC;
+	dw_mmc_init(&params, &info);
 
 	hikey_io_setup();
 }
diff --git a/plat/hisilicon/hikey/hikey_io_storage.c b/plat/hisilicon/hikey/hikey_io_storage.c
index ef55224..3efbefe 100644
--- a/plat/hisilicon/hikey/hikey_io_storage.c
+++ b/plat/hisilicon/hikey/hikey_io_storage.c
@@ -7,7 +7,6 @@
 #include <arch_helpers.h>
 #include <assert.h>
 #include <debug.h>
-#include <emmc.h>
 #include <errno.h>
 #include <firmware_image_package.h>
 #include <io_block.h>
@@ -15,6 +14,7 @@
 #include <io_fip.h>
 #include <io_memmap.h>
 #include <io_storage.h>
+#include <mmc.h>
 #include <mmio.h>
 #include <platform_def.h>
 #include <semihosting.h>	/* For FOPEN_MODE_... */
@@ -59,10 +59,10 @@
 	},
 #endif
 	.ops		= {
-		.read	= emmc_read_blocks,
-		.write	= emmc_write_blocks,
+		.read	= mmc_read_blocks,
+		.write	= mmc_write_blocks,
 	},
-	.block_size	= EMMC_BLOCK_SIZE,
+	.block_size	= MMC_BLOCK_SIZE,
 };
 
 static const io_uuid_spec_t bl31_uuid_spec = {
diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk
index 6a2474e..ccc7296 100644
--- a/plat/hisilicon/hikey/platform.mk
+++ b/plat/hisilicon/hikey/platform.mk
@@ -65,7 +65,7 @@
 				drivers/io/io_block.c			\
 				drivers/io/io_fip.c			\
 				drivers/io/io_storage.c			\
-				drivers/emmc/emmc.c			\
+				drivers/mmc/mmc.c			\
 				drivers/synopsys/emmc/dw_mmc.c		\
 				lib/cpus/aarch64/cortex_a53.S		\
 				plat/hisilicon/hikey/aarch64/hikey_helpers.S \
@@ -81,7 +81,7 @@
 				drivers/io/io_block.c			\
 				drivers/io/io_fip.c			\
 				drivers/io/io_storage.c			\
-				drivers/emmc/emmc.c			\
+				drivers/mmc/mmc.c			\
 				drivers/synopsys/emmc/dw_mmc.c		\
 				lib/cpus/aarch64/cortex_a53.S		\
 				plat/hisilicon/hikey/aarch64/hikey_helpers.S \
diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c
index 25eed59..6fc4f33 100644
--- a/plat/hisilicon/poplar/bl1_plat_setup.c
+++ b/plat/hisilicon/poplar/bl1_plat_setup.c
@@ -10,9 +10,9 @@
 #include <console.h>
 #include <debug.h>
 #include <dw_mmc.h>
-#include <emmc.h>
 #include <errno.h>
 #include <generic_delay_timer.h>
+#include <mmc.h>
 #include <mmio.h>
 #include <pl061_gpio.h>
 #include <platform.h>
@@ -92,6 +92,7 @@
 void bl1_platform_setup(void)
 {
 	int i;
+	struct mmc_device_info info;
 #if !POPLAR_RECOVERY
 	dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
 #endif
@@ -105,7 +106,8 @@
 #if !POPLAR_RECOVERY
 	/* SoC-specific emmc register are initialized/configured by bootrom */
 	INFO("BL1: initializing emmc\n");
-	dw_mmc_init(&params);
+	info.mmc_dev_type = MMC_IS_EMMC;
+	dw_mmc_init(&params, &info);
 #endif
 
 	plat_io_setup();
diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c
index 2671994..041ed4a 100644
--- a/plat/hisilicon/poplar/bl2_plat_setup.c
+++ b/plat/hisilicon/poplar/bl2_plat_setup.c
@@ -11,9 +11,9 @@
 #include <debug.h>
 #include <desc_image_load.h>
 #include <dw_mmc.h>
-#include <emmc.h>
 #include <errno.h>
 #include <generic_delay_timer.h>
+#include <mmc.h>
 #include <mmio.h>
 #include <optee_utils.h>
 #include <partition/partition.h>
@@ -333,6 +333,8 @@
 
 void bl2_early_platform_setup(meminfo_t *mem_layout)
 {
+	struct mmc_device_info info;
+
 #if !POPLAR_RECOVERY
 	dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
 #endif
@@ -347,7 +349,8 @@
 #if !POPLAR_RECOVERY
 	/* SoC-specific emmc register are initialized/configured by bootrom */
 	INFO("BL2: initializing emmc\n");
-	dw_mmc_init(&params);
+	info.mmc_dev_type = MMC_IS_EMMC;
+	dw_mmc_init(&params, &info);
 #endif
 
 	plat_io_setup();
diff --git a/plat/hisilicon/poplar/include/hi3798cv200.h b/plat/hisilicon/poplar/include/hi3798cv200.h
index 125b048..254b357 100644
--- a/plat/hisilicon/poplar/include/hi3798cv200.h
+++ b/plat/hisilicon/poplar/include/hi3798cv200.h
@@ -67,11 +67,11 @@
 
 #define EMMC_DESC_SIZE			U(0x00100000) /* 1MB */
 #define EMMC_INIT_PARAMS(base)				\
-	{	.bus_width = EMMC_BUS_WIDTH_8,		\
+	{	.bus_width = MMC_BUS_WIDTH_8,		\
 		.clk_rate = 25 * 1000 * 1000,		\
 		.desc_base = (base),	\
 		.desc_size = EMMC_DESC_SIZE,		\
-		.flags =  EMMC_FLAG_CMD23,		\
+		.flags =  MMC_FLAG_CMD23,		\
 		.reg_base = REG_BASE_MCI,		\
 	}
 
diff --git a/plat/hisilicon/poplar/plat_storage.c b/plat/hisilicon/poplar/plat_storage.c
index db52c67..925274c 100644
--- a/plat/hisilicon/poplar/plat_storage.c
+++ b/plat/hisilicon/poplar/plat_storage.c
@@ -7,13 +7,13 @@
 #include <arch_helpers.h>
 #include <assert.h>
 #include <debug.h>
-#include <emmc.h>
 #include <firmware_image_package.h>
 #include <io_block.h>
 #include <io_driver.h>
 #include <io_fip.h>
 #include <io_memmap.h>
 #include <io_storage.h>
+#include <mmc.h>
 #include <mmio.h>
 #include <partition/partition.h>
 #include <semihosting.h>
@@ -38,10 +38,10 @@
 		.length	= POPLAR_EMMC_DATA_SIZE,
 	},
 	.ops		= {
-		.read	= emmc_read_blocks,
-		.write	= emmc_write_blocks,
+		.read	= mmc_read_blocks,
+		.write	= mmc_write_blocks,
 	},
-	.block_size	= EMMC_BLOCK_SIZE,
+	.block_size	= MMC_BLOCK_SIZE,
 };
 #else
 static const io_dev_connector_t *mmap_dev_con;
diff --git a/plat/hisilicon/poplar/platform.mk b/plat/hisilicon/poplar/platform.mk
index 14ffa99..3cdbe59 100644
--- a/plat/hisilicon/poplar/platform.mk
+++ b/plat/hisilicon/poplar/platform.mk
@@ -82,7 +82,7 @@
 BL1_SOURCES	+=							\
 		lib/cpus/aarch64/cortex_a53.S				\
 		drivers/arm/pl061/pl061_gpio.c				\
-		drivers/emmc/emmc.c					\
+		drivers/mmc/mmc.c					\
 		drivers/synopsys/emmc/dw_mmc.c				\
 		drivers/io/io_storage.c					\
 		drivers/io/io_block.c					\
@@ -94,7 +94,7 @@
 
 BL2_SOURCES	+=      						\
 		drivers/arm/pl061/pl061_gpio.c				\
-		drivers/emmc/emmc.c					\
+		drivers/mmc/mmc.c					\
 		drivers/synopsys/emmc/dw_mmc.c				\
 		drivers/io/io_storage.c					\
 		drivers/io/io_block.c					\
diff --git a/plat/layerscape/common/ls_bl1_setup.c b/plat/layerscape/common/ls_bl1_setup.c
index 43f7450..0642b5e 100644
--- a/plat/layerscape/common/ls_bl1_setup.c
+++ b/plat/layerscape/common/ls_bl1_setup.c
@@ -59,7 +59,7 @@
 			     );
 	VERBOSE("After setup the page tables\n");
 #ifdef AARCH32
-	enable_mmu_secure(0);
+	enable_mmu_svc_mon(0);
 #else
 	enable_mmu_el3(0);
 #endif /* AARCH32 */
diff --git a/plat/layerscape/common/ls_bl2_setup.c b/plat/layerscape/common/ls_bl2_setup.c
index 6e6ad6e..4b2dc72 100644
--- a/plat/layerscape/common/ls_bl2_setup.c
+++ b/plat/layerscape/common/ls_bl2_setup.c
@@ -53,7 +53,7 @@
 			      );
 
 #ifdef AARCH32
-	enable_mmu_secure(0);
+	enable_mmu_svc_mon(0);
 #else
 	enable_mmu_el1(0);
 #endif
diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index 379ab3d..1d46eec 100644
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -132,8 +132,7 @@
 				plat/qemu/qemu_io_storage.c		\
 				plat/qemu/${ARCH}/plat_helpers.S	\
 				plat/qemu/qemu_bl2_setup.c		\
-				plat/qemu/dt.c				\
-				$(LIBFDT_SRCS)
+				plat/qemu/dt.c
 ifeq (${LOAD_IMAGE_V2},1)
 BL2_SOURCES		+=	plat/qemu/qemu_bl2_mem_params_desc.c	\
 				plat/qemu/qemu_image_load.c		\
diff --git a/plat/rpi3/include/platform_def.h b/plat/rpi3/include/platform_def.h
index 4674bfb..1950376 100644
--- a/plat/rpi3/include/platform_def.h
+++ b/plat/rpi3/include/platform_def.h
@@ -217,8 +217,8 @@
  */
 #define ADDR_SPACE_SIZE			(ULL(1) << 32)
 
-#define MAX_MMAP_REGIONS		U(8)
-#define MAX_XLAT_TABLES			U(4)
+#define MAX_MMAP_REGIONS		8
+#define MAX_XLAT_TABLES			4
 
 #define MAX_IO_DEVICES			U(3)
 #define MAX_IO_HANDLES			U(4)
diff --git a/plat/st/stm32mp1/stm32mp1_common.c b/plat/st/stm32mp1/stm32mp1_common.c
index 68ca7db..7d84da1 100644
--- a/plat/st/stm32mp1/stm32mp1_common.c
+++ b/plat/st/stm32mp1/stm32mp1_common.c
@@ -74,7 +74,7 @@
 	mmap_add(stm32mp1_mmap);
 	init_xlat_tables();
 
-	enable_mmu_secure(0);
+	enable_mmu_svc_mon(0);
 }
 
 uintptr_t plat_get_ns_image_entrypoint(void)
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index bf2a73f..7cb6eb7 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -12,7 +12,7 @@
 PROGRAMMABLE_RESET_ADDRESS:=	1
 
 # System coherency is managed in hardware
-HW_ASSISTED_COHERENCY	:=	1
+WARMBOOT_ENABLE_DCACHE_EARLY:=	1
 USE_COHERENT_MEM	:=	0
 
 ERROR_DEPRECATED	:=	1
diff --git a/readme.rst b/readme.rst
index 8c78d17..4897f36 100644
--- a/readme.rst
+++ b/readme.rst
@@ -33,16 +33,25 @@
 -  The stdlib source code is derived from FreeBSD code, which uses various
    BSD licenses, including BSD-3-Clause and BSD-2-Clause.
 
--  The libfdt source code is dual licensed. It is used by this project under
-   the terms of the BSD-2-Clause license.
+-  The libfdt source code is disjunctively dual licensed
+   (GPL-2.0+ OR BSD-2-Clause). It is used by this project under the terms of
+   the BSD-2-Clause license. Any contributions to this code must be made under
+   the terms of both licenses.
 
--  The LLVM compiler-rt source code is dual licensed. It is used by this
-   project under the terms of the NCSA license (also known as the University of
-   Illinois/NCSA Open Source License).
+-  The LLVM compiler-rt source code is disjunctively dual licensed
+   (NCSA OR MIT). It is used by this project under the terms of the NCSA
+   license (also known as the University of Illinois/NCSA Open Source License),
+   which is a permissive license compatible with BSD-3-Clause. Any
+   contributions to this code must be made under the terms of both licenses.
 
 -  The zlib source code is licensed under the Zlib license, which is a
    permissive license compatible with BSD-3-Clause.
 
+-  Some STMicroelectronics platform source code is disjunctively dual licensed
+   (GPL-2.0+ OR BSD-3-Clause). It is used by this project under the terms of the
+   BSD-3-Clause license. Any contributions to this code must be made under the
+   terms of both licenses.
+
 This release
 ------------
 
diff --git a/services/spd/trusty/generic-arm64-smcall.c b/services/spd/trusty/generic-arm64-smcall.c
index 38da279..feeecaa 100644
--- a/services/spd/trusty/generic-arm64-smcall.c
+++ b/services/spd/trusty/generic-arm64-smcall.c
@@ -57,14 +57,14 @@
 	}
 }
 
-static uint64_t trusty_generic_platform_smc(uint32_t smc_fid,
-			 uint64_t x1,
-			 uint64_t x2,
-			 uint64_t x3,
-			 uint64_t x4,
+static uintptr_t trusty_generic_platform_smc(uint32_t smc_fid,
+			 u_register_t x1,
+			 u_register_t x2,
+			 u_register_t x3,
+			 u_register_t x4,
 			 void *cookie,
 			 void *handle,
-			 uint64_t flags)
+			 u_register_t flags)
 {
 	switch (smc_fid) {
 	case SMC_FC_DEBUG_PUTC:
diff --git a/services/std_svc/spm/sp_xlat.c b/services/std_svc/spm/sp_xlat.c
index 2aa2fa1..3527138 100644
--- a/services/std_svc/spm/sp_xlat.c
+++ b/services/std_svc/spm/sp_xlat.c
@@ -44,7 +44,7 @@
  * converts an attributes value from the SMC format to the mmap_attr_t format by
  * setting MT_RW/MT_RO, MT_USER/MT_PRIVILEGED and MT_EXECUTE/MT_EXECUTE_NEVER.
  * The other fields are left as 0 because they are ignored by the function
- * change_mem_attributes().
+ * xlat_change_mem_attributes_ctx().
  */
 static unsigned int smc_attr_to_mmap_attr(unsigned int attributes)
 {
@@ -112,12 +112,12 @@
 
 	spin_lock(&mem_attr_smc_lock);
 
-	int rc = get_mem_attributes(sp_ctx->xlat_ctx_handle,
+	int rc = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle,
 				     base_va, &attributes);
 
 	spin_unlock(&mem_attr_smc_lock);
 
-	/* Convert error codes of get_mem_attributes() into SPM ones. */
+	/* Convert error codes of xlat_get_mem_attributes_ctx() into SPM. */
 	assert((rc == 0) || (rc == -EINVAL));
 
 	if (rc == 0) {
@@ -142,13 +142,13 @@
 
 	spin_lock(&mem_attr_smc_lock);
 
-	int ret = change_mem_attributes(sp_ctx->xlat_ctx_handle,
+	int ret = xlat_change_mem_attributes_ctx(sp_ctx->xlat_ctx_handle,
 					base_va, size,
 					smc_attr_to_mmap_attr(attributes));
 
 	spin_unlock(&mem_attr_smc_lock);
 
-	/* Convert error codes of change_mem_attributes() into SPM ones. */
+	/* Convert error codes of xlat_change_mem_attributes_ctx() into SPM. */
 	assert((ret == 0) || (ret == -EINVAL));
 
 	return (ret == 0) ? SPM_SUCCESS : SPM_INVALID_PARAMETER;