| commit | afc2ed63f9c83a3b7408d804cbe22f02d34d075d | [log] [tgz] |
|---|---|---|
| author | Bipin Ravi <bipin.ravi@arm.com> | Wed Mar 31 18:45:55 2021 -0500 |
| committer | Bipin Ravi <bipin.ravi@arm.com> | Fri Sep 03 15:44:56 2021 -0500 |
| tree | daf947db21682ae911e9b73636ec51ae96e92e0a | |
| parent | 213afde907a375f4f28ac1843b633ca83887f174 [diff] |
errata: workaround for Cortex-A710 erratum 2017096 Cortex-A710 erratum 2017096 is a Cat B erratum that applies to revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to set CPUECLTR_EL1[8] to 1 which disables store issue prefetching. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775101/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3