commit | b6d7b3e9d616c255ad9ebaea7e029b383a2c9add | [log] [tgz] |
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author | Tejas Patel <tejas.patel@xilinx.com> | Tue Sep 01 04:43:53 2020 -0700 |
committer | Manish Pandey <manish.pandey2@arm.com> | Mon Dec 07 11:10:13 2020 +0000 |
tree | 92e406d36aaae1084dc19636198d2edcd192c664 | |
parent | 07d8a5f7dc0aed07382cd7d3a276988b2e02b76d [diff] |
plat: xilinx: versal: Add support to get clock rate value Add support to get clock's rate value. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I3ed881053ef323b2ca73e13edd0affda860d381d