| commit | d69bbd0e80d07d4c9008a0666e192491ddf52e43 | [log] [tgz] |
|---|---|---|
| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | Fri May 03 16:35:25 2019 +0530 |
| committer | Jolly Shah <jolly.shah@xilinx.com> | Wed Jan 15 11:04:05 2020 -0800 |
| tree | 3559eee7d3730136e407492faa6c470da86d26c4 | |
| parent | 29af4789759714db41d10e3c80d0b00e14916d54 [diff] |
xilinx: versal: Wire silicon default setup Add new option for serial and default clock setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I0ca7ad51637cdaa6bb891f22c53595d20da7236a