Merge "Tegra: enable SDEI handling" into integration
diff --git a/common/fdt_wrappers.c b/common/fdt_wrappers.c
index 1901a20..5aad14e 100644
--- a/common/fdt_wrappers.c
+++ b/common/fdt_wrappers.c
@@ -341,3 +341,199 @@
return fdt_path_offset(dtb, path);
}
+
+
+/*******************************************************************************
+ * Only devices which are direct children of root node use CPU address domain.
+ * All other devices use addresses that are local to the device node and cannot
+ * directly used by CPU. Device tree provides an address translation mechanism
+ * through "ranges" property which provides mappings from local address space to
+ * parent address space. Since a device could be a child of a child node to the
+ * root node, there can be more than one level of address translation needed to
+ * map the device local address space to CPU address space.
+ * fdtw_translate_address() API performs address translation of a local address
+ * to a global address with help of various helper functions.
+ ******************************************************************************/
+
+static bool fdtw_xlat_hit(const uint32_t *value, int child_addr_size,
+ int parent_addr_size, int range_size, uint64_t base_address,
+ uint64_t *translated_addr)
+{
+ uint64_t local_address, parent_address, addr_range;
+
+ local_address = fdt_read_prop_cells(value, child_addr_size);
+ parent_address = fdt_read_prop_cells(value + child_addr_size,
+ parent_addr_size);
+ addr_range = fdt_read_prop_cells(value + child_addr_size +
+ parent_addr_size,
+ range_size);
+ VERBOSE("DT: Address %llx mapped to %llx with range %llx\n",
+ local_address, parent_address, addr_range);
+
+ /* Perform range check */
+ if ((base_address < local_address) ||
+ (base_address >= local_address + addr_range)) {
+ return false;
+ }
+
+ /* Found hit for the addr range that needs to be translated */
+ *translated_addr = parent_address + (base_address - local_address);
+ VERBOSE("DT: child address %llx mapped to %llx in parent bus\n",
+ local_address, parent_address);
+ return true;
+}
+
+#define ILLEGAL_ADDR ULL(~0)
+
+static uint64_t fdtw_search_all_xlat_entries(const void *dtb,
+ const struct fdt_property *ranges_prop,
+ int local_bus, uint64_t base_address)
+{
+ uint64_t translated_addr;
+ const uint32_t *next_entry;
+ int parent_bus_node, nxlat_entries, length;
+ int self_addr_cells, parent_addr_cells, self_size_cells, ncells_xlat;
+
+ /*
+ * The number of cells in one translation entry in ranges is the sum of
+ * the following values:
+ * self#address-cells + parent#address-cells + self#size-cells
+ * Ex: the iofpga ranges property has one translation entry with 4 cells
+ * They represent iofpga#addr-cells + motherboard#addr-cells + iofpga#size-cells
+ * = 1 + 2 + 1
+ */
+
+ parent_bus_node = fdt_parent_offset(dtb, local_bus);
+ self_addr_cells = fdt_address_cells(dtb, local_bus);
+ self_size_cells = fdt_size_cells(dtb, local_bus);
+ parent_addr_cells = fdt_address_cells(dtb, parent_bus_node);
+
+ /* Number of cells per translation entry i.e., mapping */
+ ncells_xlat = self_addr_cells + parent_addr_cells + self_size_cells;
+
+ assert(ncells_xlat > 0);
+
+ /*
+ * Find the number of translations(mappings) specified in the current
+ * `ranges` property. Note that length represents number of bytes and
+ * is stored in big endian mode.
+ */
+ length = fdt32_to_cpu(ranges_prop->len);
+ nxlat_entries = (length/sizeof(uint32_t))/ncells_xlat;
+
+ assert(nxlat_entries > 0);
+
+ next_entry = (const uint32_t *)ranges_prop->data;
+
+ /* Iterate over the entries in the "ranges" */
+ for (int i = 0; i < nxlat_entries; i++) {
+ if (fdtw_xlat_hit(next_entry, self_addr_cells,
+ parent_addr_cells, self_size_cells, base_address,
+ &translated_addr)){
+ return translated_addr;
+ }
+ next_entry = next_entry + ncells_xlat;
+ }
+
+ INFO("DT: No translation found for address %llx in node %s\n",
+ base_address, fdt_get_name(dtb, local_bus, NULL));
+ return ILLEGAL_ADDR;
+}
+
+
+/*******************************************************************************
+ * address mapping needs to be done recursively starting from current node to
+ * root node through all intermediate parent nodes.
+ * Sample device tree is shown here:
+
+smb@0,0 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x08000000 0x04000000>,
+ <1 0 0 0x14000000 0x04000000>,
+ <2 0 0 0x18000000 0x04000000>,
+ <3 0 0 0x1c000000 0x04000000>,
+ <4 0 0 0x0c000000 0x04000000>,
+ <5 0 0 0x10000000 0x04000000>;
+
+ motherboard {
+ arm,v2m-memory-map = "rs1";
+ compatible = "arm,vexpress,v2m-p1", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ iofpga@3,00000000 {
+ compatible = "arm,amba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 3 0 0x200000>;
+ v2m_serial1: uart@a0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0a0000 0x1000>;
+ interrupts = <0 6 4>;
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+ };
+};
+
+ * As seen above, there are 3 levels of address translations needed. An empty
+ * `ranges` property denotes identity mapping (as seen in `motherboard` node).
+ * Each ranges property can map a set of child addresses to parent bus. Hence
+ * there can be more than 1 (translation) entry in the ranges property as seen
+ * in the `smb` node which has 6 translation entries.
+ ******************************************************************************/
+
+/* Recursive implementation */
+uint64_t fdtw_translate_address(const void *dtb, int node,
+ uint64_t base_address)
+{
+ int length, local_bus_node;
+ const char *node_name;
+ uint64_t global_address;
+
+ local_bus_node = fdt_parent_offset(dtb, node);
+ node_name = fdt_get_name(dtb, local_bus_node, NULL);
+
+ /*
+ * In the example given above, starting from the leaf node:
+ * uart@a000 represents the current node
+ * iofpga@3,00000000 represents the local bus
+ * motherboard represents the parent bus
+ */
+
+ /* Read the ranges property */
+ const struct fdt_property *property = fdt_get_property(dtb,
+ local_bus_node, "ranges", &length);
+
+ if (property == NULL) {
+ if (local_bus_node == 0) {
+ /*
+ * root node doesn't have range property as addresses
+ * are in CPU address space.
+ */
+ return base_address;
+ }
+ INFO("DT: Couldn't find ranges property in node %s\n",
+ node_name);
+ return ILLEGAL_ADDR;
+ } else if (length == 0) {
+ /* empty ranges indicates identity map to parent bus */
+ return fdtw_translate_address(dtb, local_bus_node, base_address);
+ }
+
+ VERBOSE("DT: Translation lookup in node %s at offset %d\n", node_name,
+ local_bus_node);
+ global_address = fdtw_search_all_xlat_entries(dtb, property,
+ local_bus_node, base_address);
+
+ if (global_address == ILLEGAL_ADDR) {
+ return ILLEGAL_ADDR;
+ }
+
+ /* Translate the local device address recursively */
+ return fdtw_translate_address(dtb, local_bus_node, global_address);
+}
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index 2d17f12..2ad7256 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -1890,6 +1890,21 @@
of the system counter, which is retrieved from the first entry in the frequency
modes table.
+Function : plat_arm_set_twedel_scr_el3() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : void
+ Return : uint32_t
+
+This function is used in v8.6+ systems to set the WFE trap delay value in
+SCR_EL3. If this function returns TWED_DISABLED or is left unimplemented, this
+feature is not enabled. The only hook provided is to set the TWED fields in
+SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to adjust
+the WFE trap delays in lower ELs and these fields should be set by the
+appropriate EL2 or EL1 code depending on the platform configuration.
+
#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/fdts/fvp-base-gicv2-psci-aarch32.dts b/fdts/fvp-base-gicv2-psci-aarch32.dts
index fcef927..591ec58 100644
--- a/fdts/fvp-base-gicv2-psci-aarch32.dts
+++ b/fdts/fvp-base-gicv2-psci-aarch32.dts
@@ -4,8 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+/* Configuration: max 4 clusters with up to 4 CPUs */
+
/dts-v1/;
+#define AFF
+#define REG_32
+
+#include "fvp-defs.dtsi"
+
/memreserve/ 0x80000000 0x00010000;
/ {
@@ -42,37 +49,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- core1 {
- cpu = <&CPU1>;
- };
- core2 {
- cpu = <&CPU2>;
- };
- core3 {
- cpu = <&CPU3>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&CPU4>;
- };
- core1 {
- cpu = <&CPU5>;
- };
- core2 {
- cpu = <&CPU6>;
- };
- core3 {
- cpu = <&CPU7>;
- };
- };
- };
+ CPU_MAP
idle-states {
entry-method = "arm,psci";
@@ -96,77 +73,7 @@
};
};
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU1:cpu@1 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU2:cpu@2 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x2>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU3:cpu@3 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x3>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU4:cpu@100 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x100>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU5:cpu@101 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x101>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU6:cpu@102 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x102>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU7:cpu@103 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x103>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
+ CPUS
L2_0: l2-cache0 {
compatible = "cache";
diff --git a/fdts/fvp-base-gicv2-psci.dts b/fdts/fvp-base-gicv2-psci.dts
index 1e0a81c..4b3942e 100644
--- a/fdts/fvp-base-gicv2-psci.dts
+++ b/fdts/fvp-base-gicv2-psci.dts
@@ -4,8 +4,14 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+/* Configuration: max 4 clusters with up to 4 CPUs */
+
/dts-v1/;
+#define AFF
+
+#include "fvp-defs.dtsi"
+
/memreserve/ 0x80000000 0x00010000;
/ {
@@ -42,37 +48,7 @@
#address-cells = <2>;
#size-cells = <0>;
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- core1 {
- cpu = <&CPU1>;
- };
- core2 {
- cpu = <&CPU2>;
- };
- core3 {
- cpu = <&CPU3>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&CPU4>;
- };
- core1 {
- cpu = <&CPU5>;
- };
- core2 {
- cpu = <&CPU6>;
- };
- core3 {
- cpu = <&CPU7>;
- };
- };
- };
+ CPU_MAP
idle-states {
entry-method = "arm,psci";
@@ -96,77 +72,7 @@
};
};
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU1:cpu@1 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU2:cpu@2 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x2>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU3:cpu@3 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x3>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU4:cpu@100 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x100>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU5:cpu@101 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x101>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU6:cpu@102 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x102>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU7:cpu@103 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x103>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
+ CPUS
L2_0: l2-cache0 {
compatible = "cache";
diff --git a/fdts/fvp-base-gicv3-psci-1t.dts b/fdts/fvp-base-gicv3-psci-1t.dts
index 3c82f7b..c5e0424 100644
--- a/fdts/fvp-base-gicv3-psci-1t.dts
+++ b/fdts/fvp-base-gicv3-psci-1t.dts
@@ -4,38 +4,11 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+/* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */
+
/dts-v1/;
+#define AFF 00
+
+#include "fvp-defs.dtsi"
#include "fvp-base-gicv3-psci-common.dtsi"
-
-&CPU0 {
- reg = <0x0 0x0>;
-};
-
-&CPU1 {
- reg = <0x0 0x100>;
-};
-
-&CPU2 {
- reg = <0x0 0x200>;
-};
-
-&CPU3 {
- reg = <0x0 0x300>;
-};
-
-&CPU4 {
- reg = <0x0 0x10000>;
-};
-
-&CPU5 {
- reg = <0x0 0x10100>;
-};
-
-&CPU6 {
- reg = <0x0 0x10200>;
-};
-
-&CPU7 {
- reg = <0x0 0x10300>;
-};
diff --git a/fdts/fvp-base-gicv3-psci-aarch32-1t.dts b/fdts/fvp-base-gicv3-psci-aarch32-1t.dts
index d1d3348..a31c703 100644
--- a/fdts/fvp-base-gicv3-psci-aarch32-1t.dts
+++ b/fdts/fvp-base-gicv3-psci-aarch32-1t.dts
@@ -4,38 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+/* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */
+
/dts-v1/;
+#define AFF 00
+#define REG_32
+
+#include "fvp-defs.dtsi"
#include "fvp-base-gicv3-psci-aarch32-common.dtsi"
-
-&CPU0 {
- reg = <0x0>;
-};
-
-&CPU1 {
- reg = <0x100>;
-};
-
-&CPU2 {
- reg = <0x200>;
-};
-
-&CPU3 {
- reg = <0x300>;
-};
-
-&CPU4 {
- reg = <0x10000>;
-};
-
-&CPU5 {
- reg = <0x10100>;
-};
-
-&CPU6 {
- reg = <0x10200>;
-};
-
-&CPU7 {
- reg = <0x10300>;
-};
diff --git a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
index a28a4a5..1a1bd12 100644
--- a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
+++ b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
@@ -40,37 +40,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- core1 {
- cpu = <&CPU1>;
- };
- core2 {
- cpu = <&CPU2>;
- };
- core3 {
- cpu = <&CPU3>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&CPU4>;
- };
- core1 {
- cpu = <&CPU5>;
- };
- core2 {
- cpu = <&CPU6>;
- };
- core3 {
- cpu = <&CPU7>;
- };
- };
- };
+ CPU_MAP
idle-states {
entry-method = "arm,psci";
@@ -94,77 +64,7 @@
};
};
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU1:cpu@1 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU2:cpu@2 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x2>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU3:cpu@3 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x3>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU4:cpu@100 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x100>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU5:cpu@101 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x101>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU6:cpu@102 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x102>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU7:cpu@103 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x103>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
+ CPUS
L2_0: l2-cache0 {
compatible = "cache";
diff --git a/fdts/fvp-base-gicv3-psci-aarch32.dts b/fdts/fvp-base-gicv3-psci-aarch32.dts
index 513014b..971b2e4 100644
--- a/fdts/fvp-base-gicv3-psci-aarch32.dts
+++ b/fdts/fvp-base-gicv3-psci-aarch32.dts
@@ -4,6 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+/* Configuration: max 4 clusters with up to 4 CPUs */
+
/dts-v1/;
+#define REG_32
+#define AFF
+
+#include "fvp-defs.dtsi"
#include "fvp-base-gicv3-psci-aarch32-common.dtsi"
diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-gicv3-psci-common.dtsi
index 4a7b656..0deb8a2 100644
--- a/fdts/fvp-base-gicv3-psci-common.dtsi
+++ b/fdts/fvp-base-gicv3-psci-common.dtsi
@@ -66,37 +66,7 @@
#address-cells = <2>;
#size-cells = <0>;
- CPU_MAP:cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- core1 {
- cpu = <&CPU1>;
- };
- core2 {
- cpu = <&CPU2>;
- };
- core3 {
- cpu = <&CPU3>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&CPU4>;
- };
- core1 {
- cpu = <&CPU5>;
- };
- core2 {
- cpu = <&CPU6>;
- };
- core3 {
- cpu = <&CPU7>;
- };
- };
- };
+ CPU_MAP
idle-states {
entry-method = "arm,psci";
@@ -120,77 +90,7 @@
};
};
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU1:cpu@1 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU2:cpu@2 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x2>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU3:cpu@3 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x3>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU4:cpu@100 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x100>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU5:cpu@101 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x101>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU6:cpu@102 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x102>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU7:cpu@103 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x103>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
+ CPUS
L2_0: l2-cache0 {
compatible = "cache";
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
index 6e63b43..bda4b8d 100644
--- a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
+++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
@@ -4,185 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+/* DynamIQ configuration: 1 cluster with up to 8 CPUs with 2 threads per each */
+
+/* Set default value if not passed from platform's makefile */
+#ifdef FVP_MAX_PE_PER_CPU
+#define PE_PER_CPU FVP_MAX_PE_PER_CPU
+#else
+#define PE_PER_CPU 2
+#endif
+
/dts-v1/;
#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
-
-&CPU_MAP {
- /delete-node/ cluster0;
-
- cluster0 {
- core0 {
- thread0 {
- cpu = <&CPU0>;
- };
- thread1 {
- cpu = <&CPU1>;
- };
- };
- core1 {
- thread0 {
- cpu = <&CPU2>;
- };
- thread1 {
- cpu = <&CPU3>;
- };
- };
- core2 {
- thread0 {
- cpu = <&CPU4>;
- };
- thread1 {
- cpu = <&CPU5>;
- };
- };
- core3 {
- thread0 {
- cpu = <&CPU6>;
- };
- thread1 {
- cpu = <&CPU7>;
- };
- };
- core4 {
- thread0 {
- cpu = <&CPU8>;
- };
- thread1 {
- cpu = <&CPU9>;
- };
- };
- core5 {
- thread0 {
- cpu = <&CPU10>;
- };
- thread1 {
- cpu = <&CPU11>;
- };
- };
- core6 {
- thread0 {
- cpu = <&CPU12>;
- };
- thread1 {
- cpu = <&CPU13>;
- };
- };
- core7 {
- thread0 {
- cpu = <&CPU14>;
- };
- thread1 {
- cpu = <&CPU15>;
- };
- };
- };
-};
-
-/ {
- cpus {
- CPU0:cpu@0 {
- reg = <0x0 0x0>;
- };
-
- CPU1:cpu@1 {
- reg = <0x0 0x1>;
- };
-
- CPU2:cpu@2 {
- reg = <0x0 0x100>;
- };
-
- CPU3:cpu@3 {
- reg = <0x0 0x101>;
- };
-
- CPU4:cpu@100 {
- reg = <0x0 0x200>;
- };
-
- CPU5:cpu@101 {
- reg = <0x0 0x201>;
- };
-
- CPU6:cpu@102 {
- reg = <0x0 0x300>;
- };
-
- CPU7:cpu@103 {
- reg = <0x0 0x301>;
- };
-
- CPU8:cpu@200 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x400>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU9:cpu@201 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x401>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU10:cpu@202 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x500>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU11:cpu@203 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x501>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU12:cpu@300 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x600>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU13:cpu@301 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x601>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU14:cpu@302 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x700>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU15:cpu@303 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x701>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
- };
-};
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi b/fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi
index 4bed36f..42a439f 100644
--- a/fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi
+++ b/fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi
@@ -6,38 +6,5 @@
/dts-v1/;
+#include "fvp-defs-dynamiq.dtsi"
#include "fvp-base-gicv3-psci-common.dtsi"
-
-/* DynamIQ based designs have upto 8 CPUs in each cluster */
-
-&CPU_MAP {
- /delete-node/ cluster0;
- /delete-node/ cluster1;
-
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- core1 {
- cpu = <&CPU1>;
- };
- core2 {
- cpu = <&CPU2>;
- };
- core3 {
- cpu = <&CPU3>;
- };
- core4 {
- cpu = <&CPU4>;
- };
- core5 {
- cpu = <&CPU5>;
- };
- core6 {
- cpu = <&CPU6>;
- };
- core7 {
- cpu = <&CPU7>;
- };
- };
-};
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq.dts b/fdts/fvp-base-gicv3-psci-dynamiq.dts
index b8b0445..b693f75 100644
--- a/fdts/fvp-base-gicv3-psci-dynamiq.dts
+++ b/fdts/fvp-base-gicv3-psci-dynamiq.dts
@@ -4,38 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+/* DynamIQ configuration: 1 cluster with up to 8 CPUs */
+
+/* Set default value if not passed from platform's makefile */
+#ifdef FVP_MAX_PE_PER_CPU
+#define PE_PER_CPU FVP_MAX_PE_PER_CPU
+#else
+#define PE_PER_CPU 1
+#endif
+
/dts-v1/;
#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
-
-&CPU0 {
- reg = <0x0 0x0>;
-};
-
-&CPU1 {
- reg = <0x0 0x100>;
-};
-
-&CPU2 {
- reg = <0x0 0x200>;
-};
-
-&CPU3 {
- reg = <0x0 0x300>;
-};
-
-&CPU4 {
- reg = <0x0 0x400>;
-};
-
-&CPU5 {
- reg = <0x0 0x500>;
-};
-
-&CPU6 {
- reg = <0x0 0x600>;
-};
-
-&CPU7 {
- reg = <0x0 0x700>;
-};
diff --git a/fdts/fvp-base-gicv3-psci.dts b/fdts/fvp-base-gicv3-psci.dts
index 65fa4b0..eb99472 100644
--- a/fdts/fvp-base-gicv3-psci.dts
+++ b/fdts/fvp-base-gicv3-psci.dts
@@ -4,6 +4,11 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+/* Configuration: max 4 clusters with up to 4 CPUs */
+
/dts-v1/;
+#define AFF
+
+#include "fvp-defs.dtsi"
#include "fvp-base-gicv3-psci-common.dtsi"
diff --git a/fdts/fvp-defs-dynamiq.dtsi b/fdts/fvp-defs-dynamiq.dtsi
new file mode 100644
index 0000000..3659cd3
--- /dev/null
+++ b/fdts/fvp-defs-dynamiq.dtsi
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FVP_DEFS_DYNAMIQ_DTSI
+#define FVP_DEFS_DYNAMIQ_DTSI
+
+/* Set default topology values if not passed from platform's makefile */
+#ifdef FVP_CLUSTER_COUNT
+#define CLUSTER_COUNT FVP_CLUSTER_COUNT
+#else
+#define CLUSTER_COUNT 1
+#endif
+
+#ifdef FVP_MAX_CPUS_PER_CLUSTER
+#define CPUS_PER_CLUSTER FVP_MAX_CPUS_PER_CLUSTER
+#else
+#define CPUS_PER_CLUSTER 8
+#endif
+
+#define CONCAT(x, y) x##y
+#define CONC(x, y) CONCAT(x, y)
+
+/*
+ * n - CPU number
+ * r - MPID
+ */
+#define CPU(n, r) \
+ CPU##n:cpu@r## { \
+ device_type = "cpu"; \
+ compatible = "arm,armv8"; \
+ reg = <0x0 0x##r>; \
+ enable-method = "psci"; \
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; \
+ next-level-cache = <&L2_0>; \
+ };
+
+#if (PE_PER_CPU == 2)
+#define THREAD(n) \
+ thread##n { \
+ cpu = <&CONC(CPU, __COUNTER__)>; \
+ };
+
+#define CORE(n) \
+ core##n { \
+ THREAD(0) \
+ THREAD(1) \
+ };
+
+#else /* PE_PER_CPU == 1 */
+#define CORE(n) \
+ core##n { \
+ cpu = <&CPU##n>;\
+ };
+#endif /* PE_PER_CORE */
+
+#if (CPUS_PER_CLUSTER == 1)
+#if (PE_PER_CPU == 1)
+#define CPUS \
+ CPU(0, 0)
+#else
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 1)
+#endif
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ };
+
+#elif (CPUS_PER_CLUSTER == 2)
+#if (PE_PER_CPU == 1)
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 100)
+#else
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 1) \
+ CPU(2, 100) \
+ CPU(3, 101)
+#endif
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ CORE(1) \
+ };
+
+#elif (CPUS_PER_CLUSTER == 3)
+#if (PE_PER_CPU == 1)
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 100) \
+ CPU(2, 200)
+#else
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 1) \
+ CPU(2, 100) \
+ CPU(3, 101) \
+ CPU(4, 200) \
+ CPU(5, 201)
+#endif
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ CORE(1) \
+ CORE(2) \
+ };
+
+#elif (CPUS_PER_CLUSTER == 4)
+#if (PE_PER_CPU == 1)
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 100) \
+ CPU(2, 200) \
+ CPU(3, 300)
+#else
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 1) \
+ CPU(2, 100) \
+ CPU(3, 101) \
+ CPU(4, 200) \
+ CPU(5, 201) \
+ CPU(6, 300) \
+ CPU(7, 301)
+#endif
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ CORE(1) \
+ CORE(2) \
+ CORE(3) \
+ };
+
+#elif (CPUS_PER_CLUSTER == 5)
+#if (PE_PER_CPU == 1)
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 100) \
+ CPU(2, 200) \
+ CPU(3, 300) \
+ CPU(4, 400)
+#else
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 1) \
+ CPU(2, 100) \
+ CPU(3, 101) \
+ CPU(4, 200) \
+ CPU(5, 201) \
+ CPU(6, 300) \
+ CPU(7, 301) \
+ CPU(8, 400) \
+ CPU(9, 401)
+#endif
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ CORE(1) \
+ CORE(2) \
+ CORE(3) \
+ CORE(4) \
+ };
+
+#elif (CPUS_PER_CLUSTER == 6)
+#if (PE_PER_CPU == 1)
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 100) \
+ CPU(2, 200) \
+ CPU(3, 300) \
+ CPU(4, 400) \
+ CPU(5, 500)
+#else
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 1) \
+ CPU(2, 100) \
+ CPU(3, 101) \
+ CPU(4, 200) \
+ CPU(5, 201) \
+ CPU(6, 300) \
+ CPU(7, 301) \
+ CPU(8, 400) \
+ CPU(9, 401) \
+ CPU(10, 500) \
+ CPU(11, 501)
+#endif
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ CORE(1) \
+ CORE(2) \
+ CORE(3) \
+ CORE(4) \
+ CORE(5) \
+ };
+
+#elif (CPUS_PER_CLUSTER == 7)
+#if (PE_PER_CPU == 1)
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 100) \
+ CPU(2, 200) \
+ CPU(3, 300) \
+ CPU(4, 400) \
+ CPU(5, 500) \
+ CPU(6, 600)
+#else
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 1) \
+ CPU(2, 100) \
+ CPU(3, 101) \
+ CPU(4, 200) \
+ CPU(5, 201) \
+ CPU(6, 300) \
+ CPU(7, 301) \
+ CPU(8, 400) \
+ CPU(9, 401) \
+ CPU(10, 500) \
+ CPU(11, 501) \
+ CPU(12, 600) \
+ CPU(13, 601)
+#endif
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ CORE(1) \
+ CORE(2) \
+ CORE(3) \
+ CORE(4) \
+ CORE(5) \
+ CORE(6) \
+ };
+
+#else
+#if (PE_PER_CPU == 1)
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 100) \
+ CPU(2, 200) \
+ CPU(3, 300) \
+ CPU(4, 400) \
+ CPU(5, 500) \
+ CPU(6, 600) \
+ CPU(7, 700)
+#else
+#define CPUS \
+ CPU(0, 0) \
+ CPU(1, 1) \
+ CPU(2, 100) \
+ CPU(3, 101) \
+ CPU(4, 200) \
+ CPU(5, 201) \
+ CPU(6, 300) \
+ CPU(7, 301) \
+ CPU(8, 400) \
+ CPU(9, 401) \
+ CPU(10, 500) \
+ CPU(11, 501) \
+ CPU(12, 600) \
+ CPU(13, 601) \
+ CPU(14, 700) \
+ CPU(15, 701)
+#endif
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ CORE(1) \
+ CORE(2) \
+ CORE(3) \
+ CORE(4) \
+ CORE(5) \
+ CORE(6) \
+ CORE(7) \
+ };
+#endif /* CPUS_PER_CLUSTER */
+
+#define CPU_MAP \
+ cpu-map { \
+ CLUSTER(0) \
+ };
+
+#endif /* FVP_DEFS_DYNAMIQ_DTSI */
diff --git a/fdts/fvp-defs.dtsi b/fdts/fvp-defs.dtsi
new file mode 100644
index 0000000..1ffe65a
--- /dev/null
+++ b/fdts/fvp-defs.dtsi
@@ -0,0 +1,400 @@
+/*
+ * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FVP_DEFS_DTSI
+#define FVP_DEFS_DTSI
+
+/* Set default topology values if not passed from platform's makefile */
+#ifndef CLUSTER_COUNT
+#ifdef FVP_CLUSTER_COUNT
+#define CLUSTER_COUNT FVP_CLUSTER_COUNT
+#else
+#define CLUSTER_COUNT 2
+#endif
+#endif /* CLUSTER_COUNT */
+
+#ifndef CPUS_PER_CLUSTER
+#ifdef FVP_MAX_CPUS_PER_CLUSTER
+#define CPUS_PER_CLUSTER FVP_MAX_CPUS_PER_CLUSTER
+#else
+#define CPUS_PER_CLUSTER 4
+#endif
+#endif /* CPUS_PER_CLUSTER */
+
+/* Get platform's topology */
+#define CPUS_COUNT (CLUSTER_COUNT * CPUS_PER_CLUSTER)
+
+#define CONCAT(x, y) x##y
+#define CONC(x, y) CONCAT(x, y)
+
+/* CPU's cluster */
+#define CLS(n) (n / CPUS_PER_CLUSTER)
+
+/* CPU's position in cluster */
+#define POS(n) (n % CPUS_PER_CLUSTER)
+
+#define ADR(n, c, p) \
+ CPU##n:cpu@CONC(c, CONC(p, AFF)) {
+
+#define PRE \
+ device_type = "cpu"; \
+ compatible = "arm,armv8";
+
+#ifdef REG_32
+/* 32-bit address */
+#define REG(c, p) \
+ reg = <CONC(0x, CONC(c, CONC(p, AFF)))>;
+#else
+/* 64-bit address */
+#define REG(c, p) \
+ reg = <0x0 CONC(0x, CONC(c, CONC(p, AFF)))>;
+#endif /* REG_32 */
+
+#define POST \
+ enable-method = "psci"; \
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; \
+ next-level-cache = <&L2_0>; \
+ };
+
+#ifdef REG_32
+#define CPU_0 \
+ CPU0:cpu@0 { \
+ PRE \
+ reg = <0x0>; \
+ POST
+#else
+#define CPU_0 \
+ CPU0:cpu@0 { \
+ PRE \
+ reg = <0x0 0x0>;\
+ POST
+#endif /* REG_32 */
+
+/*
+ * n - CPU number
+ */
+#define CPU(n, c, p) \
+ ADR(n, c, p) \
+ PRE \
+ REG(c, p) \
+ POST
+
+/* 2 CPUs */
+#if (CPUS_COUNT > 1)
+#if (CLS(1) == 0)
+#define c1
+#define p1 1
+#else
+#define c1 10
+#define p1 0
+#endif
+
+#define CPU_1 CPU(1, c1, p1) /* CPU1: 0.1; 1.0 */
+
+/* 3 CPUs */
+#if (CPUS_COUNT > 2)
+#if (CLS(2) == 0)
+#define c2
+#define p2 2
+#elif (CLS(2) == 1)
+#define c2 10
+#define p2 0
+#else
+#define c2 20
+#define p2 0
+#endif
+
+#define CPU_2 CPU(2, c2, p2) /* CPU2: 0.2; 1.0; 2.0 */
+
+/* 4 CPUs */
+#if (CPUS_COUNT > 3)
+#if (CLS(3) == 0)
+#define c3
+#elif (CLS(3) == 1)
+#define c3 10
+#else
+#define c3 30
+#endif
+
+#if (POS(3) == 0)
+#define p3 0
+#elif (POS(3) == 1)
+#define p3 1
+#else
+#define p3 3
+#endif
+
+#define CPU_3 CPU(3, c3, p3) /* CPU3: 0.3; 1.0; 1.1; 3.0 */
+
+/* 6 CPUs */
+#if (CPUS_COUNT > 4)
+#if (CLS(4) == 1)
+#define c4 10
+#else
+#define c4 20
+#endif
+
+#if (POS(4) == 0)
+#define p4 0
+#else
+#define p4 1
+#endif
+
+#if (CLS(5) == 1)
+#define c5 10
+#else
+#define c5 20
+#endif
+
+#if (POS(5) == 1)
+#define p5 1
+#else
+#define p5 2
+#endif
+
+#define CPU_4 CPU(4, c4, p4) /* CPU4: 1.0; 1.1; 2.0 */
+#define CPU_5 CPU(5, c5, p5) /* CPU5: 1.1; 1.2; 2.1 */
+
+/* 8 CPUs */
+#if (CPUS_COUNT > 6)
+#if (CLS(6) == 1)
+#define c6 10
+#define p6 2
+#elif (CLS(6) == 2)
+#define c6 20
+#define p6 0
+#else
+#define c6 30
+#define p6 0
+#endif
+
+#if (CLS(7) == 1)
+#define c7 10
+#define p7 3
+#elif (CLS(7) == 2)
+#define c7 20
+#define p7 1
+#else
+#define c7 30
+#define p7 1
+#endif
+
+#define CPU_6 CPU(6, c6, p6) /* CPU6: 1.2; 2.0; 3.0 */
+#define CPU_7 CPU(7, c7, p7) /* CPU7: 1.3; 2.1; 3.1 */
+
+/* 9 CPUs */
+#if (CPUS_COUNT > 8)
+#if (POS(8) == 0)
+#define p8 0
+#else
+#define p8 2
+#endif
+
+#define CPU_8 CPU(8, 20, p8) /* CPU8: 2.0; 2.2 */
+
+/* 12 CPUs */
+#if (CPUS_COUNT > 9)
+#if (CLS(9) == 2)
+#define c9 20
+#define p9 1
+#else
+#define c9 30
+#define p9 0
+#endif
+
+#if (CLS(10) == 2)
+#define c10 20
+#define p10 2
+#else
+#define c10 30
+#define p10 1
+#endif
+
+#if (CLS(11) == 2)
+#define c11 20
+#define p11 3
+#else
+#define c11 30
+#define p11 2
+#endif
+
+#define CPU_9 CPU(9, c9, p9) /* CPU9: 2.1; 3.0 */
+#define CPU_10 CPU(10, c10, p10) /* CPU10: 2.2; 3.1 */
+#define CPU_11 CPU(11, c11, p11) /* CPU11: 2.3; 3.2 */
+
+/* 16 CPUs */
+#if (CPUS_COUNT > 12)
+#define CPU_12 CPU(12, 30, 0) /* CPU12: 3.0 */
+#define CPU_13 CPU(13, 30, 1) /* CPU13: 3.1 */
+#define CPU_14 CPU(14, 30, 2) /* CPU14: 3.2 */
+#define CPU_15 CPU(15, 30, 3) /* CPU15: 3.3 */
+#endif /* > 12 */
+#endif /* > 9 */
+#endif /* > 8 */
+#endif /* > 6 */
+#endif /* > 4 */
+#endif /* > 3 */
+#endif /* > 2 */
+#endif /* > 1 */
+
+#if (CPUS_COUNT == 1)
+#define CPUS \
+ CPU_0
+
+#elif (CPUS_COUNT == 2)
+#define CPUS \
+ CPU_0 \
+ CPU_1
+
+#elif (CPUS_COUNT == 3)
+#define CPUS \
+ CPU_0 \
+ CPU_1 \
+ CPU_2
+
+#elif (CPUS_COUNT == 4)
+#define CPUS \
+ CPU_0 \
+ CPU_1 \
+ CPU_2 \
+ CPU_3
+
+#elif (CPUS_COUNT == 6)
+#define CPUS \
+ CPU_0 \
+ CPU_1 \
+ CPU_2 \
+ CPU_3 \
+ CPU_4 \
+ CPU_5
+
+#elif (CPUS_COUNT == 8)
+#define CPUS \
+ CPU_0 \
+ CPU_1 \
+ CPU_2 \
+ CPU_3 \
+ CPU_4 \
+ CPU_5 \
+ CPU_6 \
+ CPU_7
+
+#elif (CPUS_COUNT == 9)
+#define CPUS \
+ CPU_0 \
+ CPU_1 \
+ CPU_2 \
+ CPU_3 \
+ CPU_4 \
+ CPU_5 \
+ CPU_6 \
+ CPU_7 \
+ CPU_8
+
+#elif (CPUS_COUNT == 12)
+#define CPUS \
+ CPU_0 \
+ CPU_1 \
+ CPU_2 \
+ CPU_3 \
+ CPU_4 \
+ CPU_5 \
+ CPU_6 \
+ CPU_7 \
+ CPU_8 \
+ CPU_9 \
+ CPU_10 \
+ CPU_11
+
+#else
+#define CPUS \
+ CPU_0 \
+ CPU_1 \
+ CPU_2 \
+ CPU_3 \
+ CPU_4 \
+ CPU_5 \
+ CPU_6 \
+ CPU_7 \
+ CPU_8 \
+ CPU_9 \
+ CPU_10 \
+ CPU_11 \
+ CPU_12 \
+ CPU_13 \
+ CPU_14 \
+ CPU_15
+#endif /* CPUS_COUNT */
+
+#define CORE(n) \
+ core##n { \
+ cpu = <&CONC(CPU, __COUNTER__)>; \
+ };
+
+/* Max 4 CPUs per cluster */
+#if (CPUS_PER_CLUSTER == 1)
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ };
+#elif (CPUS_PER_CLUSTER == 2)
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ CORE(1) \
+ };
+
+#elif (CPUS_PER_CLUSTER == 3)
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ CORE(1) \
+ CORE(2) \
+ };
+
+#else
+#define CLUSTER(n) \
+ cluster##n { \
+ CORE(0) \
+ CORE(1) \
+ CORE(2) \
+ CORE(3) \
+ };
+#endif /* CPUS_PER_CLUSTER */
+
+/* Max 4 clusters */
+#if (CLUSTER_COUNT == 1)
+#define CPU_MAP \
+ cpu-map { \
+ CLUSTER(0) \
+ };
+
+#elif (CLUSTER_COUNT == 2)
+#define CPU_MAP \
+ cpu-map { \
+ CLUSTER(0) \
+ CLUSTER(1) \
+ };
+
+#elif (CLUSTER_COUNT == 3)
+#define CPU_MAP \
+ cpu-map { \
+ CLUSTER(0) \
+ CLUSTER(1) \
+ CLUSTER(2) \
+ };
+
+#else
+#define CPU_MAP \
+ cpu-map { \
+ CLUSTER(0) \
+ CLUSTER(1) \
+ CLUSTER(2) \
+ CLUSTER(3) \
+ };
+#endif /* CLUSTER_COUNT */
+
+#endif /* FVP_DEFS_DTSI */
diff --git a/fdts/fvp-foundation-gicv2-psci.dts b/fdts/fvp-foundation-gicv2-psci.dts
index 3a204cb..95a800e 100644
--- a/fdts/fvp-foundation-gicv2-psci.dts
+++ b/fdts/fvp-foundation-gicv2-psci.dts
@@ -4,8 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+/* Configuration: 1 cluster with up to 4 CPUs */
+
/dts-v1/;
+#define AFF
+#define CLUSTER_COUNT 1
+
+#include "fvp-defs.dtsi"
+
/memreserve/ 0x80000000 0x00010000;
/ {
@@ -42,22 +49,7 @@
#address-cells = <2>;
#size-cells = <0>;
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- core1 {
- cpu = <&CPU1>;
- };
- core2 {
- cpu = <&CPU2>;
- };
- core3 {
- cpu = <&CPU3>;
- };
- };
- };
+ CPU_MAP
idle-states {
entry-method = "arm,psci";
@@ -81,41 +73,7 @@
};
};
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU1:cpu@1 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU2:cpu@2 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x2>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU3:cpu@3 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x3>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
+ CPUS
L2_0: l2-cache0 {
compatible = "cache";
diff --git a/fdts/fvp-foundation-gicv3-psci.dts b/fdts/fvp-foundation-gicv3-psci.dts
index d85305a..c295dc1 100644
--- a/fdts/fvp-foundation-gicv3-psci.dts
+++ b/fdts/fvp-foundation-gicv3-psci.dts
@@ -4,8 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+/* Configuration: 1 cluster with up to 4 CPUs */
+
/dts-v1/;
+#define AFF
+#define CLUSTER_COUNT 1
+
+#include "fvp-defs.dtsi"
+
/memreserve/ 0x80000000 0x00010000;
/ {
@@ -42,22 +49,7 @@
#address-cells = <2>;
#size-cells = <0>;
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- core1 {
- cpu = <&CPU1>;
- };
- core2 {
- cpu = <&CPU2>;
- };
- core3 {
- cpu = <&CPU3>;
- };
- };
- };
+ CPU_MAP
idle-states {
entry-method = "arm,psci";
@@ -81,41 +73,7 @@
};
};
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU1:cpu@1 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU2:cpu@2 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x2>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
-
- CPU3:cpu@3 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x3>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- next-level-cache = <&L2_0>;
- };
+ CPUS
L2_0: l2-cache0 {
compatible = "cache";
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 81e0f27..92e6737 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -226,6 +226,12 @@
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
+/* ID_AA64MMFR1_EL1 definitions */
+#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
+#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
+#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
+#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
+
/* ID_AA64MMFR2_EL1 definitions */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
@@ -312,6 +318,9 @@
/* SCR definitions */
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
+#define SCR_TWEDEL_SHIFT U(30)
+#define SCR_TWEDEL_MASK ULL(0xf)
+#define SCR_TWEDEn_BIT (UL(1) << 29)
#define SCR_ATA_BIT (U(1) << 26)
#define SCR_FIEN_BIT (U(1) << 21)
#define SCR_EEL2_BIT (U(1) << 18)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 9513e97..49d827d 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -58,4 +58,10 @@
ID_AA64PFR0_SEL2_MASK) == 1ULL;
}
+static inline bool is_armv8_6_twed_present(void)
+{
+ return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_TWED_SHIFT) &
+ ID_AA64MMFR1_EL1_TWED_MASK) == ID_AA64MMFR1_EL1_TWED_SUPPORTED);
+}
+
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 9cd1ae5..09059ca 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -358,6 +358,7 @@
DEFINE_SYSREG_READ_FUNC(midr_el1)
DEFINE_SYSREG_READ_FUNC(mpidr_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
+DEFINE_SYSREG_READ_FUNC(id_aa64mmfr1_el1)
DEFINE_SYSREG_RW_FUNCS(scr_el3)
DEFINE_SYSREG_RW_FUNCS(hcr_el2)
diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h
index 382651e..1d8da18 100644
--- a/include/common/fdt_wrappers.h
+++ b/include/common/fdt_wrappers.h
@@ -34,4 +34,7 @@
uintptr_t *base, size_t *size);
int fdt_get_stdout_node_offset(const void *dtb);
+uint64_t fdtw_translate_address(const void *dtb, int bus_node,
+ uint64_t base_address);
+
#endif /* FDT_WRAPPERS_H */
diff --git a/include/lib/extensions/twed.h b/include/lib/extensions/twed.h
new file mode 100644
index 0000000..eac4aa3
--- /dev/null
+++ b/include/lib/extensions/twed.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TWED_H
+#define TWED_H
+
+#include <stdint.h>
+
+#define TWED_DISABLED U(0xFFFFFFFF)
+
+uint32_t plat_arm_set_twedel_scr_el3(void);
+
+#endif /* TWEDE_H */
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 0314a85..64a2d7b 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -22,6 +22,7 @@
#include <lib/extensions/mpam.h>
#include <lib/extensions/spe.h>
#include <lib/extensions/sve.h>
+#include <lib/extensions/twed.h>
#include <lib/utils.h>
@@ -229,6 +230,24 @@
sctlr_elx |= SCTLR_IESB_BIT;
#endif
+ /* Enable WFE trap delay in SCR_EL3 if supported and configured */
+ if (is_armv8_6_twed_present()) {
+ uint32_t delay = plat_arm_set_twedel_scr_el3();
+
+ if (delay != TWED_DISABLED) {
+ /* Make sure delay value fits */
+ assert((delay & ~SCR_TWEDEL_MASK) == 0U);
+
+ /* Set delay in SCR_EL3 */
+ scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
+ scr_el3 |= ((delay & SCR_TWEDEL_MASK)
+ << SCR_TWEDEL_SHIFT);
+
+ /* Enable WFE delay */
+ scr_el3 |= SCR_TWEDEn_BIT;
+ }
+ }
+
/*
* Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
* and other EL2 registers are set up by cm_prepare_ns_entry() as they
diff --git a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
index f1d9b93..8172a6e 100644
--- a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
+++ b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
@@ -13,6 +13,9 @@
struct gicv3_config_t gicv3_config;
struct hw_topology_t soc_topology;
+struct uart_serial_config_t uart_serial_config;
+
+#define ILLEGAL_ADDR ULL(~0)
int fconf_populate_gicv3_config(uintptr_t config)
{
@@ -147,7 +150,8 @@
return -1;
}
- INFO("CLUSTER ID: %d cpu-count: %d\n", cluster_count, cpus_per_cluster[cluster_count]);
+ VERBOSE("CLUSTER ID: %d cpu-count: %d\n", cluster_count,
+ cpus_per_cluster[cluster_count]);
/* Find the maximum number of cpus in any cluster */
max_cpu_per_cluster = MAX(max_cpu_per_cluster, cpus_per_cluster[cluster_count]);
@@ -170,5 +174,95 @@
return 0;
}
+int fconf_populate_uart_config(uintptr_t config)
+{
+ int uart_node, node, err;
+ uintptr_t addr;
+ const char *path;
+ uint32_t phandle;
+ uint64_t translated_addr;
+
+ /* Necessary to work with libfdt APIs */
+ const void *hw_config_dtb = (const void *)config;
+
+ /*
+ * uart child node is indirectly referenced through its path which is
+ * specified in the `serial1` property of the "aliases" node.
+ * Note that TF-A boot console is mapped to serial0 while runtime
+ * console is mapped to serial1.
+ */
+
+ path = fdt_get_alias(hw_config_dtb, "serial1");
+ if (path == NULL) {
+ ERROR("FCONF: Could not read serial1 property in aliases node\n");
+ return -1;
+ }
+
+ /* Find the offset of the uart serial node */
+ uart_node = fdt_path_offset(hw_config_dtb, path);
+ if (uart_node < 0) {
+ ERROR("FCONF: Failed to locate uart serial node using its path\n");
+ return -1;
+ }
+
+ /* uart serial node has its offset and size of address in reg property */
+ err = fdt_get_reg_props_by_index(hw_config_dtb, uart_node, 0, &addr,
+ NULL);
+ if (err < 0) {
+ ERROR("FCONF: Failed to read reg property of '%s' node\n",
+ "uart serial");
+ return err;
+ }
+ VERBOSE("FCONF: UART node address: %lx\n", addr);
+
+ /*
+ * Perform address translation of local device address to CPU address
+ * domain.
+ */
+ translated_addr = fdtw_translate_address(hw_config_dtb,
+ uart_node, (uint64_t)addr);
+ if (translated_addr == ILLEGAL_ADDR) {
+ ERROR("FCONF: failed to translate UART node base address");
+ return -1;
+ }
+
+ uart_serial_config.uart_base = translated_addr;
+
+ VERBOSE("FCONF: UART serial device base address: %llx\n",
+ uart_serial_config.uart_base);
+
+ /*
+ * The phandle of the DT node which captures the clock info of uart
+ * serial node is specified in the "clocks" property.
+ */
+ err = fdt_read_uint32(hw_config_dtb, uart_node, "clocks", &phandle);
+ if (err < 0) {
+ ERROR("FCONF: Could not read clocks property in uart serial node\n");
+ return err;
+ }
+
+ node = fdt_node_offset_by_phandle(hw_config_dtb, phandle);
+ if (node < 0) {
+ ERROR("FCONF: Failed to locate clk node using its path\n");
+ return node;
+ }
+
+ /*
+ * Retrieve clock frequency. We assume clock provider generates a fixed
+ * clock.
+ */
+ err = fdt_read_uint32(hw_config_dtb, node, "clock-frequency",
+ &uart_serial_config.uart_clk);
+ if (err < 0) {
+ ERROR("FCONF: Could not read clock-frequency property in clk node\n");
+ return err;
+ }
+
+ VERBOSE("FCONF: UART serial device clk frequency: %x\n",
+ uart_serial_config.uart_clk);
+ return 0;
+}
+
FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
+FCONF_REGISTER_POPULATOR(HW_CONFIG, uart_config, fconf_populate_uart_config);
diff --git a/plat/arm/board/fvp/include/fconf_hw_config_getter.h b/plat/arm/board/fvp/include/fconf_hw_config_getter.h
index dbce0e4..b53e00a 100644
--- a/plat/arm/board/fvp/include/fconf_hw_config_getter.h
+++ b/plat/arm/board/fvp/include/fconf_hw_config_getter.h
@@ -14,6 +14,8 @@
#define hw_config__topology_getter(prop) soc_topology.prop
+#define hw_config__uart_serial_config_getter(prop) uart_serial_config.prop
+
struct gicv3_config_t {
uint64_t gicd_base;
uint64_t gicr_base;
@@ -26,10 +28,17 @@
uint32_t plat_max_pwr_level;
};
+struct uart_serial_config_t {
+ uint64_t uart_base;
+ uint32_t uart_clk;
+};
+
int fconf_populate_gicv3_config(uintptr_t config);
int fconf_populate_topology(uintptr_t config);
+int fconf_populate_uart_config(uintptr_t config);
extern struct gicv3_config_t gicv3_config;
extern struct hw_topology_t soc_topology;
+extern struct uart_serial_config_t uart_serial_config;
#endif /* FCONF_HW_CONFIG_GETTER_H */
diff --git a/plat/arm/board/fvp/jmptbl.i b/plat/arm/board/fvp/jmptbl.i
index 213a974..b72bdab 100644
--- a/plat/arm/board/fvp/jmptbl.i
+++ b/plat/arm/board/fvp/jmptbl.i
@@ -16,6 +16,7 @@
rom rom_lib_init
fdt fdt_getprop
+fdt fdt_get_property
fdt fdt_getprop_namelen
fdt fdt_setprop_inplace
fdt fdt_check_header
@@ -31,6 +32,9 @@
fdt fdt_parent_offset
fdt fdt_stringlist_search
fdt fdt_get_alias_namelen
+fdt fdt_get_name
+fdt fdt_get_alias
+fdt fdt_node_offset_by_phandle
mbedtls mbedtls_asn1_get_alg
mbedtls mbedtls_asn1_get_alg_null
mbedtls mbedtls_asn1_get_bitstring_null
diff --git a/plat/arm/board/juno/jmptbl.i b/plat/arm/board/juno/jmptbl.i
index 09017ac..20ed2c7 100644
--- a/plat/arm/board/juno/jmptbl.i
+++ b/plat/arm/board/juno/jmptbl.i
@@ -16,6 +16,7 @@
rom rom_lib_init
fdt fdt_getprop
+fdt fdt_get_property
fdt fdt_getprop_namelen
fdt fdt_setprop_inplace
fdt fdt_check_header
@@ -28,6 +29,9 @@
fdt fdt_get_alias_namelen
fdt fdt_path_offset
fdt fdt_path_offset_namelen
+fdt fdt_get_name
+fdt fdt_get_alias
+fdt fdt_node_offset_by_phandle
mbedtls mbedtls_asn1_get_alg
mbedtls mbedtls_asn1_get_alg_null
mbedtls mbedtls_asn1_get_bitstring_null
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index 63871d9..b8a4d01 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -11,6 +11,7 @@
#if RAS_EXTENSION
#include <lib/extensions/ras.h>
#endif
+#include <lib/extensions/twed.h>
#include <lib/xlat_tables/xlat_mmu_helpers.h>
#include <plat/common/platform.h>
@@ -20,6 +21,7 @@
* platforms but may also be overridden by a platform if required.
*/
#pragma weak bl31_plat_runtime_setup
+#pragma weak plat_arm_set_twedel_scr_el3
#if SDEI_SUPPORT
#pragma weak plat_sdei_handle_masked_trigger
@@ -100,3 +102,16 @@
#endif
panic();
}
+
+/*******************************************************************************
+ * In v8.6+ platforms with delayed trapping of WFE this hook sets the delay. It
+ * is a weak function definition so can be overridden depending on the
+ * requirements of a platform. The only hook provided is for the TWED fields
+ * in SCR_EL3, the TWED fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 should be
+ * configured as needed in lower exception levels.
+ ******************************************************************************/
+
+uint32_t plat_arm_set_twedel_scr_el3(void)
+{
+ return TWED_DISABLED;
+}
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index ce5815b..e226372 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -73,19 +73,16 @@
switch (state_id) {
case PSTATE_ID_CORE_IDLE:
+ if (psci_get_pstate_type(power_state) != PSTATE_TYPE_STANDBY) {
+ ret = PSCI_E_INVALID_PARAMS;
+ break;
+ }
+
/* Core idle request */
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN;
break;
- case PSTATE_ID_CORE_POWERDN:
-
- /* Core powerdown request */
- req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id;
- req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
-
- break;
-
default:
ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
ret = PSCI_E_INVALID_PARAMS;
@@ -117,7 +114,7 @@
int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
{
const plat_local_state_t *pwr_domain_state;
- uint8_t stateid_afflvl0, stateid_afflvl2;
+ uint8_t stateid_afflvl2;
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t mc_ctx_base;
uint32_t val;
@@ -128,25 +125,14 @@
.system_state_force = 1U,
.update_wake_mask = 1U,
};
- uint32_t cpu = plat_my_core_pos();
int32_t ret = 0;
/* get the state ID */
pwr_domain_state = target_state->pwr_domain_state;
- stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] &
- TEGRA194_STATE_ID_MASK;
stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
TEGRA194_STATE_ID_MASK;
- if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) {
-
- /* Enter CPU powerdown */
- (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
- (uint64_t)TEGRA_NVG_CORE_C7,
- t19x_percpu_data[cpu].wake_time,
- 0U);
-
- } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
+ if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
/* save 'Secure Boot' Processor Feature Config Register */
val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
@@ -187,8 +173,6 @@
/* set system suspend state for house-keeping */
tegra194_set_system_suspend_entry();
- } else {
- ; /* do nothing */
}
return PSCI_E_SUCCESS;
@@ -226,15 +210,6 @@
plat_local_state_t target = states[core_pos];
mce_cstate_info_t cstate_info = { 0 };
- /* CPU suspend */
- if (target == PSTATE_ID_CORE_POWERDN) {
-
- /* Program default wake mask */
- cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK;
- cstate_info.update_wake_mask = 1;
- mce_update_cstate_info(&cstate_info);
- }
-
/* CPU off */
if (target == PLAT_MAX_OFF_STATE) {