tree 66a71202b0a92fae01a1e2b10c69235a5f358a72
parent fa233ac9d435905d2717a9880cfb3a1671e37134
author Antonio Nino Diaz <antonio.ninodiaz@arm.com> 1550508943 +0000
committer Antonio Nino Diaz <antonio.ninodiaz@arm.com> 1550509396 +0000

Disable processor Cycle Counting in Secure state

In a system with ARMv8.5-PMU implemented:

- If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting
  in Secure state in PMCCNTR.

- If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in
  Secure state in PMCCNTR_EL0.

So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64)
or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure
as any EL can change that value.

Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>