Merge "Tegra: introduce support for SMCCC_ARCH_SOC_ID" into integration
diff --git a/Makefile b/Makefile
index 5c4f36c..9972362 100644
--- a/Makefile
+++ b/Makefile
@@ -891,6 +891,7 @@
$(eval $(call assert_boolean,USE_SPINLOCK_CAS))
$(eval $(call assert_boolean,ENCRYPT_BL31))
$(eval $(call assert_boolean,ENCRYPT_BL32))
+$(eval $(call assert_boolean,ERRATA_SPECULATIVE_AT))
$(eval $(call assert_numeric,ARM_ARCH_MAJOR))
$(eval $(call assert_numeric,ARM_ARCH_MINOR))
@@ -967,6 +968,7 @@
$(eval $(call add_define,BL2_IN_XIP_MEM))
$(eval $(call add_define,BL2_INV_DCACHE))
$(eval $(call add_define,USE_SPINLOCK_CAS))
+$(eval $(call add_define,ERRATA_SPECULATIVE_AT))
ifeq (${SANITIZE_UB},trap)
$(eval $(call add_define,MONITOR_TRAPS))
diff --git a/common/desc_image_load.c b/common/desc_image_load.c
index 47c80aa..30b97e0 100644
--- a/common/desc_image_load.c
+++ b/common/desc_image_load.c
@@ -214,9 +214,6 @@
{
bl_params_node_t *params_node;
unsigned int fw_config_id;
-#ifdef SPD_spmd
- uint32_t fw_config_size = 0;
-#endif
uintptr_t fw_config_base;
bl_mem_params_node_t *mem_params;
uintptr_t hw_config_base = 0;
@@ -264,10 +261,6 @@
mem_params = get_bl_mem_params_node(fw_config_id);
if (mem_params != NULL) {
fw_config_base = mem_params->image_info.image_base;
-#ifdef SPD_spmd
- fw_config_size =
- mem_params->image_info.image_size;
-#endif
}
}
@@ -306,11 +299,6 @@
if (params_node->ep_info->args.arg1 == 0U)
params_node->ep_info->args.arg1 =
hw_config_base;
-#ifdef SPD_spmd
- if (params_node->ep_info->args.arg2 == 0U)
- params_node->ep_info->args.arg2 =
- fw_config_size;
-#endif
}
#ifdef SPD_opteed
}
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index e4fb09d..d40134f 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -1,14 +1,20 @@
-Maintainers
-===========
+Project Maintenance
+===================
-Trusted Firmware-A (TF-A) is an Arm maintained project. All contributions are
-ultimately merged by the maintainers listed below. Technical ownership of some
-parts of the codebase is delegated to the sub-maintainers listed below. An
-acknowledgement from these sub-maintainers may be required before the
+Trusted Firmware-A (TF-A) is an open governance community project. All
+contributions are ultimately merged by the maintainers listed below. Technical
+ownership of most parts of the codebase falls on the code owners listed
+below. An acknowledgement from these code owners is required before the
maintainers merge a contribution.
-Main maintainers
-----------------
+More details may be found in the `Project Maintenance Process`_ document.
+
+
+.. _maintainers:
+
+Maintainers
+-----------
+
:M: Dan Handley <dan.handley@arm.com>
:G: `danh-arm`_
:M: Soby Mathew <soby.mathew@arm.com>
@@ -28,63 +34,29 @@
:M: Joanna Farley <joanna.farley@arm.com>
:G: `joannafarley-arm`_
-Allwinner ARMv8 platform port
------------------------------
-:M: Andre Przywara <andre.przywara@arm.com>
-:G: `Andre-ARM`_
-:M: Samuel Holland <samuel@sholland.org>
-:G: `smaeul`_
-:F: docs/plat/allwinner.rst
-:F: plat/allwinner/
-:F: drivers/allwinner/
-Amlogic Meson S905 (GXBB) platform port
----------------------------------------
-:M: Andre Przywara <andre.przywara@arm.com>
-:G: `Andre-ARM`_
-:F: docs/plat/meson-gxbb.rst
-:F: drivers/amlogic/
-:F: plat/amlogic/gxbb/
+.. _code owners:
-Amlogic Meson S905x (GXL) platform port
----------------------------------------
-:M: Remi Pommarel <repk@triplefau.lt>
-:G: `remi-triplefault`_
-:F: docs/plat/meson-gxl.rst
-:F: plat/amlogic/gxl/
+Code owners
+-----------
-Amlogic Meson S905X2 (G12A) platform port
------------------------------------------
-:M: Carlo Caione <ccaione@baylibre.com>
-:G: `carlocaione`_
-:F: docs/plat/meson-g12a.rst
-:F: plat/amlogic/g12a/
+Core Code
+~~~~~~~~~
-Amlogic Meson A113D (AXG) platform port
------------------------------------------
-:M: Carlo Caione <ccaione@baylibre.com>
-:G: `carlocaione`_
-:F: docs/plat/meson-axg.rst
-:F: plat/amlogic/axg/
+.. note::
+ This section is incomplete right now.
Armv7-A architecture port
--------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Etienne Carriere <etienne.carriere@linaro.org>
:G: `etienne-lms`_
-Arm System Guidance for Infrastructure / Mobile FVP platforms
--------------------------------------------------------------
-:M: Nariman Poushin <nariman.poushin@linaro.org>
-:G: `npoushin`_
-:M: Thomas Abraham <thomas.abraham@arm.com>
-:G: `thomas-arm`_
-:F: plat/arm/css/sgi/
-:F: plat/arm/css/sgm/
-:F: plat/arm/board/sgi575/
-:F: plat/arm/board/sgm775/
+
+Drivers, Libraries and Framework Code
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Console API framework
----------------------
+^^^^^^^^^^^^^^^^^^^^^
:M: Julius Werner <jwerner@chromium.org>
:G: `jwerner-chromium`_
:F: drivers/console/
@@ -92,7 +64,7 @@
:F: plat/common/aarch64/crash_console_helpers.S
coreboot support libraries
---------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Julius Werner <jwerner@chromium.org>
:G: `jwerner-chromium`_
:F: drivers/coreboot/
@@ -101,7 +73,7 @@
:F: lib/coreboot/
eMMC/UFS drivers
-----------------
+^^^^^^^^^^^^^^^^
:M: Haojian Zhuang <haojian.zhuang@linaro.org>
:G: `hzhuang1`_
:F: drivers/partition/
@@ -112,8 +84,62 @@
:F: include/drivers/ufs.h
:F: include/drivers/synopsys/dw_mmc.h
+
+Platform Ports
+~~~~~~~~~~~~~~
+
+Allwinner ARMv8 platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:M: Andre Przywara <andre.przywara@arm.com>
+:G: `Andre-ARM`_
+:M: Samuel Holland <samuel@sholland.org>
+:G: `smaeul`_
+:F: docs/plat/allwinner.rst
+:F: plat/allwinner/
+:F: drivers/allwinner/
+
+Amlogic Meson S905 (GXBB) platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:M: Andre Przywara <andre.przywara@arm.com>
+:G: `Andre-ARM`_
+:F: docs/plat/meson-gxbb.rst
+:F: drivers/amlogic/
+:F: plat/amlogic/gxbb/
+
+Amlogic Meson S905x (GXL) platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:M: Remi Pommarel <repk@triplefau.lt>
+:G: `remi-triplefault`_
+:F: docs/plat/meson-gxl.rst
+:F: plat/amlogic/gxl/
+
+Amlogic Meson S905X2 (G12A) platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:M: Carlo Caione <ccaione@baylibre.com>
+:G: `carlocaione`_
+:F: docs/plat/meson-g12a.rst
+:F: plat/amlogic/g12a/
+
+Amlogic Meson A113D (AXG) platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:M: Carlo Caione <ccaione@baylibre.com>
+:G: `carlocaione`_
+:F: docs/plat/meson-axg.rst
+:F: plat/amlogic/axg/
+
+Arm System Guidance for Infrastructure / Mobile FVP platforms
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:M: Nariman Poushin <nariman.poushin@linaro.org>
+:G: `npoushin`_
+:M: Thomas Abraham <thomas.abraham@arm.com>
+:G: `thomas-arm`_
+:F: plat/arm/css/sgi/
+:F: plat/arm/css/sgm/
+:F: plat/arm/board/sgi575/
+:F: plat/arm/board/sgm775/
+
HiSilicon HiKey and HiKey960 platform ports
--------------------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Haojian Zhuang <haojian.zhuang@linaro.org>
:G: `hzhuang1`_
:F: docs/plat/hikey.rst
@@ -122,14 +148,14 @@
:F: plat/hisilicon/hikey960/
HiSilicon Poplar platform port
-------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Shawn Guo <shawn.guo@linaro.org>
:G: `shawnguo2`_
:F: docs/plat/poplar.rst
:F: plat/hisilicon/poplar/
Intel SocFPGA platform ports
-----------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Tien Hock Loh <tien.hock.loh@intel.com>
:G: `thloh85-intel`_
:M: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
@@ -138,13 +164,13 @@
:F: drivers/intel/soc/
MediaTek platform ports
------------------------
+^^^^^^^^^^^^^^^^^^^^^^^
:M: Yidi Lin (林以廸) <yidi.lin@mediatek.com>
:G: `mtk09422`_
:F: plat/mediatek/
Marvell platform ports and SoC drivers
---------------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Konstantin Porotchkin <kostap@marvell.com>
:G: `kostapr`_
:F: docs/plat/marvell/
@@ -153,7 +179,7 @@
:F: tools/marvell/
NVidia platform ports
----------------------
+^^^^^^^^^^^^^^^^^^^^^
:M: Varun Wadekar <vwadekar@nvidia.com>
:G: `vwadekar`_
:F: docs/plat/nvidia-tegra.rst
@@ -162,14 +188,14 @@
:F: plat/nvidia/
NXP QorIQ Layerscape platform ports
------------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Jiafei Pan <jiafei.pan@nxp.com>
:G: `qoriq-open-source`_
:F: docs/plat/ls1043a.rst
:F: plat/layerscape/
NXP i.MX 7 WaRP7 platform port and SoC drivers
-----------------------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
:G: `bryanodonoghue`_
:M: Jun Nie <jun.nie@linaro.org>
@@ -182,35 +208,28 @@
:F: drivers/imx/usdhc/
NXP i.MX 8 platform port
-------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^
:M: Anson Huang <Anson.Huang@nxp.com>
:G: `Anson-Huang`_
:F: docs/plat/imx8.rst
:F: plat/imx/
NXP i.MX8M platform port
-------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^
:M: Jacky Bai <ping.bai@nxp.com>
:G: `JackyBai`_
:F: docs/plat/imx8m.rst
:F: plat/imx/imx8m/
-OP-TEE dispatcher
------------------
-:M: Jens Wiklander <jens.wiklander@linaro.org>
-:G: `jenswi-linaro`_
-:F: docs/components/spd/optee-dispatcher.rst
-:F: services/spd/opteed/
-
QEMU platform port
-------------------
+^^^^^^^^^^^^^^^^^^
:M: Jens Wiklander <jens.wiklander@linaro.org>
:G: `jenswi-linaro`_
:F: docs/plat/qemu.rst
:F: plat/qemu/
Raspberry Pi 3 platform port
-----------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
:G: `grandpaul`_
:F: docs/plat/rpi3.rst
@@ -220,7 +239,7 @@
:F: include/drivers/rpi3/
Raspberry Pi 4 platform port
-----------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Andre Przywara <andre.przywara@arm.com>
:G: `Andre-ARM`_
:F: docs/plat/rpi4.rst
@@ -230,7 +249,7 @@
:F: include/drivers/rpi3/
Renesas rcar-gen3 platform port
--------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
:G: `ldts`_
:M: Marek Vasut <marek.vasut@gmail.com>
@@ -241,7 +260,7 @@
:F: tools/renesas/rcar_layout_create
RockChip platform port
-----------------------
+^^^^^^^^^^^^^^^^^^^^^^
:M: Tony Xie <tony.xie@rock-chips.com>
:G: `TonyXie06`_
:G: `rockchip-linux`_
@@ -250,7 +269,7 @@
:F: plat/rockchip/
STM32MP1 platform port
-----------------------
+^^^^^^^^^^^^^^^^^^^^^^
:M: Yann Gautier <yann.gautier@st.com>
:G: `Yann-lms`_
:F: docs/plat/stm32mp1.rst
@@ -262,21 +281,46 @@
:F: tools/stm32image/
Synquacer platform port
------------------------
+^^^^^^^^^^^^^^^^^^^^^^^
:M: Sumit Garg <sumit.garg@linaro.org>
:G: `b49020`_
:F: docs/plat/synquacer.rst
:F: plat/socionext/synquacer/
Texas Instruments platform port
--------------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Andrew F. Davis <afd@ti.com>
:G: `glneo`_
:F: docs/plat/ti-k3.rst
:F: plat/ti/
+UniPhier platform port
+^^^^^^^^^^^^^^^^^^^^^^
+:M: Masahiro Yamada <yamada.masahiro@socionext.com>
+:G: `masahir0y`_
+:F: docs/plat/socionext-uniphier.rst
+:F: plat/socionext/uniphier/
+
+Xilinx platform port
+^^^^^^^^^^^^^^^^^^^^
+:M: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+:G: `sivadur`_
+:F: docs/plat/xilinx-zynqmp.rst
+:F: plat/xilinx/
+
+
+Secure Payload Dispatchers
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+OP-TEE dispatcher
+^^^^^^^^^^^^^^^^^
+:M: Jens Wiklander <jens.wiklander@linaro.org>
+:G: `jenswi-linaro`_
+:F: docs/components/spd/optee-dispatcher.rst
+:F: services/spd/opteed/
+
TLK/Trusty secure payloads
---------------------------
+^^^^^^^^^^^^^^^^^^^^^^^^^^
:M: Varun Wadekar <vwadekar@nvidia.com>
:G: `vwadekar`_
:F: docs/components/spd/tlk-dispatcher.rst
@@ -285,19 +329,6 @@
:F: services/spd/tlkd/
:F: services/spd/trusty/
-UniPhier platform port
-----------------------
-:M: Masahiro Yamada <yamada.masahiro@socionext.com>
-:G: `masahir0y`_
-:F: docs/plat/socionext-uniphier.rst
-:F: plat/socionext/uniphier/
-
-Xilinx platform port
---------------------
-:M: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
-:G: `sivadur`_
-:F: docs/plat/xilinx-zynqmp.rst
-:F: plat/xilinx/
.. _AlexeiFedorov: https://github.com/AlexeiFedorov
.. _Andre-ARM: https://github.com/Andre-ARM
@@ -339,3 +370,5 @@
.. _odeprez: https://github.com/odeprez
.. _bipinravi-arm: https://github.com/bipinravi-arm
.. _joannafarley-arm: https://github.com/joannafarley-arm
+
+.. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 90fe83f..6f3b605 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -673,6 +673,29 @@
default value of this flag is ``no``. Note this option must be enabled only
for ARM architecture greater than Armv8.5-A.
+- ``ERRATA_SPECULATIVE_AT``: This flag enables/disables page table walk during
+ context restore as speculative AT instructions using an out-of-context
+ translation regime could cause subsequent requests to generate an incorrect
+ translation.
+ System registers are not updated during context save, hence this workaround
+ need not be applied in the context save path.
+
+ This boolean option enables errata for all below CPUs.
+
+ +---------+--------------+
+ | Errata | CPU |
+ +=========+==============+
+ | 1165522 | Cortex-A76 |
+ +---------+--------------+
+ | 1319367 | Cortex-A72 |
+ +---------+--------------+
+ | 1319537 | Cortex-A57 |
+ +---------+--------------+
+ | 1530923 | Cortex-A55 |
+ +---------+--------------+
+ | 1530924 | Cortex-A53 |
+ +---------+--------------+
+
GICv3 driver options
--------------------
diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst
index 68c494b..7886cf4 100644
--- a/docs/process/contributing.rst
+++ b/docs/process/contributing.rst
@@ -4,8 +4,8 @@
Getting Started
---------------
-- Make sure you have a Github account and you are logged on
- `developer.trustedfirmware.org`_.
+- Make sure you have a Github account and you are logged on both
+ `developer.trustedfirmware.org`_ and `review.trustedfirmware.org`_.
- Create an `issue`_ for your work if one does not already exist. This gives
everyone visibility of whether others are working on something similar.
@@ -55,9 +55,9 @@
where XXXX is the year of first contribution (if different to YYYY) and
YYYY is the year of most recent contribution. <OWNER> is your name or
your company name.
- - If you are submitting new files that you intend to be the technical
- sub-maintainer for (for example, a new platform port), then also update
- the :ref:`maintainers` file.
+ - If you are submitting new files that you intend to be the code owner for
+ (for example, a new platform port), then also update the
+ :ref:`code owners` file.
- For topics with multiple commits, you should make all documentation
changes (and nothing else) in the last commit of the series. Otherwise,
include the documentation changes within the single commit.
@@ -91,8 +91,10 @@
targeting the ``integration`` branch.
- The changes will then undergo further review and testing by the
- :ref:`maintainers`. Any review comments will be made directly on your
- patch. This may require you to do some rework.
+ :ref:`code owners` and :ref:`maintainers`. Any review comments will be
+ made directly on your patch. This may require you to do some rework. For
+ controversial changes, the discussion might be moved to the `TF-A mailing
+ list`_ to involve more of the community.
Refer to the `Gerrit Uploading Changes documentation`_ for more details.
@@ -102,12 +104,12 @@
``integration`` branch.
- If the changes are not based on a sufficiently-recent commit, or if they
cannot be automatically rebased, then the :ref:`maintainers` may rebase it
- on the ``master`` branch or ask you to do so.
+ on the ``integration`` branch or ask you to do so.
- After final integration testing, the changes will make their way into the
- ``master`` branch. If a problem is found during integration, the merge
- commit will be removed from the ``integration`` branch and the
- :ref:`maintainers` will ask you to create a new patch set to resolve the
- problem.
+ ``master`` branch. If a problem is found during integration, the
+ :ref:`maintainers` will request your help to solve the issue. They may
+ revert your patches and ask you to resubmit a reworked version of them or
+ they may ask you to provide a fix-up patch.
Binary Components
-----------------
@@ -131,12 +133,14 @@
*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
.. _developer.trustedfirmware.org: https://developer.trustedfirmware.org
+.. _review.trustedfirmware.org: https://review.trustedfirmware.org
.. _issue: https://developer.trustedfirmware.org/project/board/1/
.. _Trusted Firmware-A: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
.. _Git guidelines: http://git-scm.com/book/ch5-2.html
.. _Gerrit Uploading Changes documentation: https://review.trustedfirmware.org/Documentation/user-upload.html
.. _Gerrit Signed-off-by Lines guidelines: https://review.trustedfirmware.org/Documentation/user-signedoffby.html
.. _Gerrit Change-Ids documentation: https://review.trustedfirmware.org/Documentation/user-changeid.html
-.. _TF-A Tests: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/about/
+.. _TF-A Tests: https://trustedfirmware-a-tests.readthedocs.io
.. _Trusted Firmware binary repository: https://review.trustedfirmware.org/admin/repos/tf-binaries
.. _tf-binaries-readme: https://git.trustedfirmware.org/tf-binaries.git/tree/readme.rst
+.. _TF-A mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a
diff --git a/docs/process/faq.rst b/docs/process/faq.rst
index 2c36584..daab198 100644
--- a/docs/process/faq.rst
+++ b/docs/process/faq.rst
@@ -70,12 +70,10 @@
All the comments from ``ci-bot-user`` are associated with Continuous Integration
infrastructure. The links published on the comment are not currently accessible,
but would be after the CI has been transitioned to `trustedfirmware.org`_.
-Please refer to https://github.com/ARM-software/tf-issues/issues/681 for more
-details on the timelines.
--------------
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
.. _Gerrit Upload Patch Set documentation: https://review.trustedfirmware.org/Documentation/intro-user.html#upload-patch-set
.. _Gerrit Replace Changes documentation: https://review.trustedfirmware.org/Documentation/user-upload.html#push_replace
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index e45a594..81e0f27 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -381,6 +381,7 @@
/* HCR definitions */
#define HCR_API_BIT (ULL(1) << 41)
#define HCR_APK_BIT (ULL(1) << 40)
+#define HCR_E2H_BIT (ULL(1) << 34)
#define HCR_TGE_BIT (ULL(1) << 27)
#define HCR_RW_SHIFT U(31)
#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 0491f48..9513e97 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -52,4 +52,10 @@
ID_AA64PFR1_EL1_MTE_MASK);
}
+static inline bool is_armv8_4_sel2_present(void)
+{
+ return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) &
+ ID_AA64PFR0_SEL2_MASK) == 1ULL;
+}
+
#endif /* ARCH_FEATURES_H */
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index e4431d2..b8ba14c 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -289,9 +289,8 @@
int plat_spm_sp_get_next_address(void **sp_base, size_t *sp_size,
void **rd_base, size_t *rd_size);
#if defined(SPD_spmd)
-int plat_spm_core_manifest_load(spmc_manifest_sect_attribute_t *manifest,
- const void *ptr,
- size_t size);
+int plat_spm_core_manifest_load(spmc_manifest_attribute_t *manifest,
+ const void *pm_addr);
#endif
/*******************************************************************************
* Mandatory BL image load functions(may be overridden).
diff --git a/include/services/spm_core_manifest.h b/include/services/spm_core_manifest.h
index 71e6cfb..0c43636 100644
--- a/include/services/spm_core_manifest.h
+++ b/include/services/spm_core_manifest.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef SPMC_MANIFEST_H
-#define SPMC_MANIFEST_H
+#ifndef SPM_CORE_MANIFEST_H
+#define SPM_CORE_MANIFEST_H
#include <stdint.h>
@@ -28,18 +28,18 @@
uint32_t exec_state;
/*
- * Address of binary image containing SPM core in bytes (optional).
+ * Address of binary image containing SPM Core (optional).
*/
uint64_t load_address;
/*
* Offset from the base of the partition's binary image to the entry
- * point of the partition.
+ * point of the partition (optional).
*/
uint64_t entrypoint;
/*
- * Size of binary image containing SPM core in bytes (mandatory).
+ * Size of binary image containing SPM Core in bytes (mandatory).
*/
uint32_t binary_size;
@@ -48,6 +48,6 @@
*/
uint16_t spmc_id;
-} spmc_manifest_sect_attribute_t;
+} spmc_manifest_attribute_t;
-#endif /* SPMC_MANIFEST_H */
+#endif /* SPM_CORE_MANIFEST_H */
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 221f33e..984468a 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -234,6 +234,21 @@
*/
func el2_sysregs_context_restore
+#if ERRATA_SPECULATIVE_AT
+/* Clear EPD0 and EPD1 bit and M bit to disable PTW */
+ mrs x9, hcr_el2
+ tst x9, #HCR_E2H_BIT
+ bne 1f
+ mrs x9, tcr_el2
+ orr x9, x9, #TCR_EPD0_BIT
+ orr x9, x9, #TCR_EPD1_BIT
+ msr tcr_el2, x9
+1: mrs x9, sctlr_el2
+ bic x9, x9, #SCTLR_M_BIT
+ msr sctlr_el2, x9
+ isb
+#endif
+
ldp x9, x10, [x0, #CTX_ACTLR_EL2]
msr actlr_el2, x9
msr afsr0_el2, x10
@@ -282,17 +297,15 @@
msr mair_el2, x15
msr mdcr_el2, x16
- ldp x17, x9, [x0, #CTX_PMSCR_EL2]
+ ldr x17, [x0, #CTX_PMSCR_EL2]
msr PMSCR_EL2, x17
- msr sctlr_el2, x9
ldp x10, x11, [x0, #CTX_SPSR_EL2]
msr spsr_el2, x10
msr sp_el2, x11
- ldp x12, x13, [x0, #CTX_TCR_EL2]
- msr tcr_el2, x12
- msr tpidr_el2, x13
+ ldr x12, [x0, #CTX_TPIDR_EL2]
+ msr tpidr_el2, x12
ldp x14, x15, [x0, #CTX_TTBR0_EL2]
msr ttbr0_el2, x14
@@ -404,6 +417,19 @@
msr scxtnum_el2, x9
#endif
+#if ERRATA_SPECULATIVE_AT
+/*
+ * Make sure all registers are stored successfully except
+ * SCTLR_EL2 and TCR_EL2
+ */
+ isb
+#endif
+
+ ldr x9, [x0, #CTX_SCTLR_EL2]
+ msr sctlr_el2, x9
+ ldr x9, [x0, #CTX_TCR_EL2]
+ msr tcr_el2, x9
+
ret
endfunc el2_sysregs_context_restore
@@ -515,12 +541,22 @@
*/
func el1_sysregs_context_restore
+#if ERRATA_SPECULATIVE_AT
+ mrs x9, tcr_el1
+ orr x9, x9, #TCR_EPD0_BIT
+ orr x9, x9, #TCR_EPD1_BIT
+ msr tcr_el1, x9
+ mrs x9, sctlr_el1
+ bic x9, x9, #SCTLR_M_BIT
+ msr sctlr_el1, x9
+ isb
+#endif
+
ldp x9, x10, [x0, #CTX_SPSR_EL1]
msr spsr_el1, x9
msr elr_el1, x10
- ldp x15, x16, [x0, #CTX_SCTLR_EL1]
- msr sctlr_el1, x15
+ ldr x16, [x0, #CTX_ACTLR_EL1]
msr actlr_el1, x16
ldp x17, x9, [x0, #CTX_CPACR_EL1]
@@ -539,9 +575,8 @@
msr mair_el1, x14
msr amair_el1, x15
- ldp x16, x17, [x0, #CTX_TCR_EL1]
- msr tcr_el1, x16
- msr tpidr_el1, x17
+ ldr x16,[x0, #CTX_TPIDR_EL1]
+ msr tpidr_el1, x16
ldp x9, x10, [x0, #CTX_TPIDR_EL0]
msr tpidr_el0, x9
@@ -597,6 +632,19 @@
msr GCR_EL1, x14
#endif
+#if ERRATA_SPECULATIVE_AT
+/*
+ * Make sure all registers are stored successfully except
+ * SCTLR_EL1 and TCR_EL1
+ */
+ isb
+#endif
+
+ ldr x9, [x0, #CTX_SCTLR_EL1]
+ msr sctlr_el1, x9
+ ldr x9, [x0, #CTX_TCR_EL1]
+ msr tcr_el1, x9
+
/* No explict ISB required here as ERET covers it */
ret
endfunc el1_sysregs_context_restore
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 590a800..608e963 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -293,3 +293,6 @@
# than Armv8.5-A
# By default it is set to "no"
SUPPORT_STACK_MEMTAG := no
+
+# Select workaround for AT speculative behaviour.
+ERRATA_SPECULATIVE_AT := 0
diff --git a/plat/common/plat_spmd_manifest.c b/plat/common/plat_spmd_manifest.c
index 8330356..109b001 100644
--- a/plat/common/plat_spmd_manifest.c
+++ b/plat/common/plat_spmd_manifest.c
@@ -5,65 +5,79 @@
*/
#include <assert.h>
+#include <errno.h>
#include <string.h>
#include <libfdt.h>
#include <common/debug.h>
#include <common/fdt_wrappers.h>
-#include <errno.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <platform_def.h>
#include <services/spm_core_manifest.h>
+#define ATTRIBUTE_ROOT_NODE_STR "attribute"
+
/*******************************************************************************
- * Attribute section handler
+ * SPMC attribute node parser
******************************************************************************/
-static int manifest_parse_attribute(spmc_manifest_sect_attribute_t *attr,
+static int manifest_parse_attribute(spmc_manifest_attribute_t *attr,
const void *fdt,
int node)
{
uint32_t val32;
- int rc = 0;
+ int rc;
- assert(attr && fdt);
+ assert((attr != NULL) && (fdt != NULL));
rc = fdt_read_uint32(fdt, node, "maj_ver", &attr->major_version);
- if (rc) {
- ERROR("Missing SPCI major version in SPM core manifest.\n");
- return -ENOENT;
+ if (rc != 0) {
+ ERROR("Missing SPCI %s version in SPM Core manifest.\n",
+ "major");
+ return rc;
}
rc = fdt_read_uint32(fdt, node, "min_ver", &attr->minor_version);
- if (rc) {
- ERROR("Missing SPCI minor version in SPM core manifest.\n");
- return -ENOENT;
+ if (rc != 0) {
+ ERROR("Missing SPCI %s version in SPM Core manifest.\n",
+ "minor");
+ return rc;
}
rc = fdt_read_uint32(fdt, node, "spmc_id", &val32);
- if (rc) {
+ if (rc != 0) {
ERROR("Missing SPMC ID in manifest.\n");
- return -ENOENT;
+ return rc;
}
- attr->spmc_id = val32;
+
+ attr->spmc_id = val32 & 0xffff;
rc = fdt_read_uint32(fdt, node, "exec_state", &attr->exec_state);
- if (rc)
- NOTICE("Execution state not specified in SPM core manifest.\n");
+ if (rc != 0) {
+ NOTICE("%s not specified in SPM Core manifest.\n",
+ "Execution state");
+ }
rc = fdt_read_uint32(fdt, node, "binary_size", &attr->binary_size);
- if (rc)
- NOTICE("Binary size not specified in SPM core manifest.\n");
+ if (rc != 0) {
+ NOTICE("%s not specified in SPM Core manifest.\n",
+ "Binary size");
+ }
rc = fdt_read_uint64(fdt, node, "load_address", &attr->load_address);
- if (rc)
- NOTICE("Load address not specified in SPM core manifest.\n");
+ if (rc != 0) {
+ NOTICE("%s not specified in SPM Core manifest.\n",
+ "Load address");
+ }
rc = fdt_read_uint64(fdt, node, "entrypoint", &attr->entrypoint);
- if (rc)
- NOTICE("Entrypoint not specified in SPM core manifest.\n");
+ if (rc != 0) {
+ NOTICE("%s not specified in SPM Core manifest.\n",
+ "Entry point");
+ }
- VERBOSE("SPM core manifest attribute section:\n");
- VERBOSE(" version: %x.%x\n", attr->major_version, attr->minor_version);
- VERBOSE(" spmc_id: %x\n", attr->spmc_id);
+ VERBOSE("SPM Core manifest attribute section:\n");
+ VERBOSE(" version: %u.%u\n", attr->major_version, attr->minor_version);
+ VERBOSE(" spmc_id: 0x%x\n", attr->spmc_id);
VERBOSE(" binary_size: 0x%x\n", attr->binary_size);
VERBOSE(" load_address: 0x%llx\n", attr->load_address);
VERBOSE(" entrypoint: 0x%llx\n", attr->entrypoint);
@@ -74,53 +88,98 @@
/*******************************************************************************
* Root node handler
******************************************************************************/
-static int manifest_parse_root(spmc_manifest_sect_attribute_t *manifest,
- const void *fdt,
- int root)
+static int manifest_parse_root(spmc_manifest_attribute_t *manifest,
+ const void *fdt,
+ int root)
{
int node;
- char *str;
- str = "attribute";
- node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str));
+ assert(manifest != NULL);
+
+ node = fdt_subnode_offset_namelen(fdt, root, ATTRIBUTE_ROOT_NODE_STR,
+ sizeof(ATTRIBUTE_ROOT_NODE_STR) - 1);
if (node < 0) {
- ERROR("Root node doesn't contain subnode '%s'\n", str);
- return -ENOENT;
+ ERROR("Root node doesn't contain subnode '%s'\n",
+ ATTRIBUTE_ROOT_NODE_STR);
+ return node;
}
return manifest_parse_attribute(manifest, fdt, node);
}
/*******************************************************************************
- * Platform handler to parse a SPM core manifest.
+ * Platform handler to parse a SPM Core manifest.
******************************************************************************/
-int plat_spm_core_manifest_load(spmc_manifest_sect_attribute_t *manifest,
- const void *ptr,
- size_t size)
+int plat_spm_core_manifest_load(spmc_manifest_attribute_t *manifest,
+ const void *pm_addr)
{
- int rc;
- int root_node;
+ int rc, unmap_ret;
+ uintptr_t pm_base, pm_base_align;
+ size_t mapped_size;
assert(manifest != NULL);
- assert(ptr != NULL);
+ assert(pm_addr != NULL);
- INFO("Reading SPM core manifest at address %p\n", ptr);
+ /*
+ * Assume TOS_FW_CONFIG is not necessarily aligned to a page
+ * boundary, thus calculate the remaining space between SPMC
+ * manifest start address and upper page limit.
+ *
+ */
+ pm_base = (uintptr_t)pm_addr;
+ pm_base_align = page_align(pm_base, UP);
+ mapped_size = pm_base_align - pm_base;
- rc = fdt_check_header(ptr);
- if (rc != 0) {
- ERROR("Wrong format for SPM core manifest (%d).\n", rc);
+ /* Check space within the page at least maps the FDT header */
+ if (mapped_size < sizeof(struct fdt_header)) {
+ ERROR("Error while mapping SPM Core manifest.\n");
return -EINVAL;
}
- INFO("Reading SPM core manifest at address %p\n", ptr);
-
- root_node = fdt_node_offset_by_compatible(ptr, -1,
- "arm,spci-core-manifest-1.0");
- if (root_node < 0) {
- ERROR("Unrecognized SPM core manifest\n");
- return -ENOENT;
+ /* Map first SPMC manifest page in the SPMD translation regime */
+ pm_base_align = page_align(pm_base, DOWN);
+ rc = mmap_add_dynamic_region((unsigned long long)pm_base_align,
+ pm_base_align,
+ PAGE_SIZE,
+ MT_RO_DATA);
+ if (rc != 0) {
+ ERROR("Error while mapping SPM Core manifest (%d).\n", rc);
+ return rc;
}
- INFO("Reading SPM core manifest at address %p\n", ptr);
- return manifest_parse_root(manifest, ptr, root_node);
+ rc = fdt_check_header(pm_addr);
+ if (rc != 0) {
+ ERROR("Wrong format for SPM Core manifest (%d).\n", rc);
+ goto exit_unmap;
+ }
+
+ /* Check SPMC manifest fits within the upper mapped page boundary */
+ if (mapped_size < fdt_totalsize(pm_addr)) {
+ ERROR("SPM Core manifest too large.\n");
+ rc = -EINVAL;
+ goto exit_unmap;
+ }
+
+ VERBOSE("Reading SPM Core manifest at address %p\n", pm_addr);
+
+ rc = fdt_node_offset_by_compatible(pm_addr, -1,
+ "arm,spci-core-manifest-1.0");
+ if (rc < 0) {
+ ERROR("Unrecognized SPM Core manifest\n");
+ goto exit_unmap;
+ }
+
+ rc = manifest_parse_root(manifest, pm_addr, rc);
+
+exit_unmap:
+ unmap_ret = mmap_remove_dynamic_region(pm_base_align, PAGE_SIZE);
+ if (unmap_ret != 0) {
+ ERROR("Error while unmapping SPM Core manifest (%d).\n",
+ unmap_ret);
+ if (rc == 0) {
+ rc = unmap_ret;
+ }
+ }
+
+ return rc;
}
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index a3e1a2d..501782f 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -9,6 +9,7 @@
#include <string.h>
#include <arch_helpers.h>
+#include <arch/aarch64/arch_features.h>
#include <bl31/bl31.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
@@ -16,7 +17,6 @@
#include <lib/smccc.h>
#include <lib/spinlock.h>
#include <lib/utils.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/common_def.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@@ -28,12 +28,12 @@
/*******************************************************************************
* SPM Core context information.
******************************************************************************/
-spmd_spm_core_context_t spm_core_context[PLATFORM_CORE_COUNT];
+static spmd_spm_core_context_t spm_core_context[PLATFORM_CORE_COUNT];
/*******************************************************************************
* SPM Core attribute information read from its manifest.
******************************************************************************/
-static spmc_manifest_sect_attribute_t spmc_attrs;
+static spmc_manifest_attribute_t spmc_attrs;
/*******************************************************************************
* SPM Core entry point information. Discovered on the primary core and reused
@@ -42,18 +42,33 @@
static entry_point_info_t *spmc_ep_info;
/*******************************************************************************
- * Static function declaration.
+ * SPM Core context on current CPU get helper.
******************************************************************************/
-static int32_t spmd_init(void);
-static int spmd_spmc_init(void *rd_base, size_t rd_size);
-static uint64_t spmd_spci_error_return(void *handle, int error_code);
-static uint64_t spmd_smc_forward(uint32_t smc_fid, bool secure_origin,
- uint64_t x1, uint64_t x2, uint64_t x3,
- uint64_t x4, void *handle);
+spmd_spm_core_context_t *spmd_get_context(void)
+{
+ unsigned int linear_id = plat_my_core_pos();
+
+ return &spm_core_context[linear_id];
+}
/*******************************************************************************
- * This function takes an SP context pointer and performs a synchronous entry
- * into it.
+ * Static function declaration.
+ ******************************************************************************/
+static int32_t spmd_init(void);
+static int spmd_spmc_init(void *pm_addr);
+static uint64_t spmd_spci_error_return(void *handle,
+ int error_code);
+static uint64_t spmd_smc_forward(uint32_t smc_fid,
+ bool secure_origin,
+ uint64_t x1,
+ uint64_t x2,
+ uint64_t x3,
+ uint64_t x4,
+ void *handle);
+
+/*******************************************************************************
+ * This function takes an SPMC context pointer and performs a synchronous
+ * SPMC entry.
******************************************************************************/
uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *spmc_ctx)
{
@@ -83,14 +98,14 @@
}
/*******************************************************************************
- * This function returns to the place where spm_sp_synchronous_entry() was
+ * This function returns to the place where spmd_spm_core_sync_entry() was
* called originally.
******************************************************************************/
__dead2 void spmd_spm_core_sync_exit(uint64_t rc)
{
- spmd_spm_core_context_t *ctx = &spm_core_context[plat_my_core_pos()];
+ spmd_spm_core_context_t *ctx = spmd_get_context();
- /* Get context of the SP in use by this CPU. */
+ /* Get current CPU context from SPMC context */
assert(cm_get_context(SECURE) == &(ctx->cpu_ctx));
/*
@@ -104,110 +119,99 @@
}
/*******************************************************************************
- * Jump to the SPM core for the first time.
+ * Jump to the SPM Core for the first time.
******************************************************************************/
static int32_t spmd_init(void)
{
- uint64_t rc = 0;
- spmd_spm_core_context_t *ctx = &spm_core_context[plat_my_core_pos()];
+ spmd_spm_core_context_t *ctx = spmd_get_context();
+ uint64_t rc;
- INFO("SPM Core init start.\n");
+ VERBOSE("SPM Core init start.\n");
ctx->state = SPMC_STATE_RESET;
rc = spmd_spm_core_sync_entry(ctx);
- if (rc) {
+ if (rc != 0ULL) {
ERROR("SPMC initialisation failed 0x%llx\n", rc);
- panic();
+ return 0;
}
ctx->state = SPMC_STATE_IDLE;
- INFO("SPM Core init end.\n");
+ VERBOSE("SPM Core init end.\n");
return 1;
}
/*******************************************************************************
- * Load SPMC manifest, init SPMC.
+ * Loads SPMC manifest and inits SPMC.
******************************************************************************/
-static int spmd_spmc_init(void *rd_base, size_t rd_size)
+static int spmd_spmc_init(void *pm_addr)
{
- int rc;
+ spmd_spm_core_context_t *spm_ctx = spmd_get_context();
uint32_t ep_attr;
- unsigned int linear_id = plat_my_core_pos();
- spmd_spm_core_context_t *spm_ctx = &spm_core_context[linear_id];
+ int rc;
- /* Load the SPM core manifest */
- rc = plat_spm_core_manifest_load(&spmc_attrs, rd_base, rd_size);
+ /* Load the SPM Core manifest */
+ rc = plat_spm_core_manifest_load(&spmc_attrs, pm_addr);
if (rc != 0) {
- WARN("No or invalid SPM core manifest image provided by BL2 "
- "boot loader. ");
- return 1;
+ WARN("No or invalid SPM Core manifest image provided by BL2\n");
+ return rc;
}
/*
- * Ensure that the SPM core version is compatible with the SPM
- * dispatcher version
+ * Ensure that the SPM Core version is compatible with the SPM
+ * Dispatcher version.
*/
if ((spmc_attrs.major_version != SPCI_VERSION_MAJOR) ||
(spmc_attrs.minor_version > SPCI_VERSION_MINOR)) {
- WARN("Unsupported SPCI version (%x.%x) specified in SPM core "
- "manifest image provided by BL2 boot loader.\n",
+ WARN("Unsupported SPCI version (%u.%u)\n",
spmc_attrs.major_version, spmc_attrs.minor_version);
- return 1;
+ return -EINVAL;
}
- INFO("SPCI version (%x.%x).\n", spmc_attrs.major_version,
+ VERBOSE("SPCI version (%u.%u)\n", spmc_attrs.major_version,
spmc_attrs.minor_version);
- INFO("SPM core run time EL%x.\n",
+ VERBOSE("SPM Core run time EL%x.\n",
SPMD_SPM_AT_SEL2 ? MODE_EL2 : MODE_EL1);
/* Validate the SPMC ID, Ensure high bit is set */
- if (!(spmc_attrs.spmc_id >> SPMC_SECURE_ID_SHIFT) &
- SPMC_SECURE_ID_MASK) {
- WARN("Invalid ID (0x%x) for SPMC.\n",
- spmc_attrs.spmc_id);
- return 1;
+ if (((spmc_attrs.spmc_id >> SPMC_SECURE_ID_SHIFT) &
+ SPMC_SECURE_ID_MASK) == 0U) {
+ WARN("Invalid ID (0x%x) for SPMC.\n", spmc_attrs.spmc_id);
+ return -EINVAL;
}
- INFO("SPMC ID %x.\n", spmc_attrs.spmc_id);
-
- /* Validate the SPM core execution state */
+ /* Validate the SPM Core execution state */
if ((spmc_attrs.exec_state != MODE_RW_64) &&
(spmc_attrs.exec_state != MODE_RW_32)) {
- WARN("Unsupported SPM core execution state %x specified in "
- "manifest image provided by BL2 boot loader.\n",
+ WARN("Unsupported %s%x.\n", "SPM Core execution state 0x",
spmc_attrs.exec_state);
- return 1;
+ return -EINVAL;
}
- INFO("SPM core execution state %x.\n", spmc_attrs.exec_state);
+ VERBOSE("%s%x.\n", "SPM Core execution state 0x",
+ spmc_attrs.exec_state);
#if SPMD_SPM_AT_SEL2
/* Ensure manifest has not requested AArch32 state in S-EL2 */
if (spmc_attrs.exec_state == MODE_RW_32) {
WARN("AArch32 state at S-EL2 is not supported.\n");
- return 1;
+ return -EINVAL;
}
/*
* Check if S-EL2 is supported on this system if S-EL2
* is required for SPM
*/
- uint64_t sel2 = read_id_aa64pfr0_el1();
-
- sel2 >>= ID_AA64PFR0_SEL2_SHIFT;
- sel2 &= ID_AA64PFR0_SEL2_MASK;
-
- if (!sel2) {
- WARN("SPM core run time S-EL2 is not supported.");
- return 1;
+ if (!is_armv8_4_sel2_present()) {
+ WARN("SPM Core run time S-EL2 is not supported.\n");
+ return -EINVAL;
}
#endif /* SPMD_SPM_AT_SEL2 */
/* Initialise an entrypoint to set up the CPU context */
ep_attr = SECURE | EP_ST_ENABLE;
- if (read_sctlr_el3() & SCTLR_EE_BIT) {
+ if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0ULL) {
ep_attr |= EP_EE_BIG;
}
@@ -215,8 +219,8 @@
assert(spmc_ep_info->pc == BL32_BASE);
/*
- * Populate SPSR for SPM core based upon validated parameters from the
- * manifest
+ * Populate SPSR for SPM Core based upon validated parameters from the
+ * manifest.
*/
if (spmc_attrs.exec_state == MODE_RW_32) {
spmc_ep_info->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
@@ -236,99 +240,66 @@
DISABLE_ALL_EXCEPTIONS);
}
- /* Initialise SPM core context with this entry point information */
+ /* Initialise SPM Core context with this entry point information */
cm_setup_context(&spm_ctx->cpu_ctx, spmc_ep_info);
/* Reuse PSCI affinity states to mark this SPMC context as off */
spm_ctx->state = AFF_STATE_OFF;
- INFO("SPM core setup done.\n");
+ INFO("SPM Core setup done.\n");
- /* Register init function for deferred init. */
+ /* Register init function for deferred init. */
bl31_register_bl32_init(&spmd_init);
return 0;
}
/*******************************************************************************
- * Initialize context of SPM core.
+ * Initialize context of SPM Core.
******************************************************************************/
int spmd_setup(void)
{
+ void *spmc_manifest;
int rc;
- void *rd_base;
- size_t rd_size;
- uintptr_t rd_base_align;
- uintptr_t rd_size_align;
spmc_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
- if (!spmc_ep_info) {
- WARN("No SPM core image provided by BL2 boot loader, Booting "
- "device without SP initialization. SMC`s destined for SPM "
- "core will return SMC_UNK\n");
- return 1;
+ if (spmc_ep_info == NULL) {
+ WARN("No SPM Core image provided by BL2 boot loader.\n");
+ return -EINVAL;
}
/* Under no circumstances will this parameter be 0 */
- assert(spmc_ep_info->pc != 0U);
+ assert(spmc_ep_info->pc != 0ULL);
/*
* Check if BL32 ep_info has a reference to 'tos_fw_config'. This will
- * be used as a manifest for the SPM core at the next lower EL/mode.
+ * be used as a manifest for the SPM Core at the next lower EL/mode.
*/
- if (spmc_ep_info->args.arg0 == 0U || spmc_ep_info->args.arg2 == 0U) {
- ERROR("Invalid or absent SPM core manifest\n");
- panic();
- }
-
- /* Obtain whereabouts of SPM core manifest */
- rd_base = (void *) spmc_ep_info->args.arg0;
- rd_size = spmc_ep_info->args.arg2;
-
- rd_base_align = page_align((uintptr_t) rd_base, DOWN);
- rd_size_align = page_align((uintptr_t) rd_size, UP);
-
- /* Map the manifest in the SPMD translation regime first */
- VERBOSE("SPM core manifest base : 0x%lx\n", rd_base_align);
- VERBOSE("SPM core manifest size : 0x%lx\n", rd_size_align);
- rc = mmap_add_dynamic_region((unsigned long long) rd_base_align,
- (uintptr_t) rd_base_align,
- rd_size_align,
- MT_RO_DATA);
- if (rc != 0) {
- ERROR("Error while mapping SPM core manifest (%d).\n", rc);
- panic();
+ spmc_manifest = (void *)spmc_ep_info->args.arg0;
+ if (spmc_manifest == NULL) {
+ ERROR("Invalid or absent SPM Core manifest.\n");
+ return -EINVAL;
}
/* Load manifest, init SPMC */
- rc = spmd_spmc_init(rd_base, rd_size);
+ rc = spmd_spmc_init(spmc_manifest);
if (rc != 0) {
- int mmap_rc;
-
- WARN("Booting device without SPM initialization. "
- "SPCI SMCs destined for SPM core will return "
- "ENOTSUPPORTED\n");
-
- mmap_rc = mmap_remove_dynamic_region(rd_base_align,
- rd_size_align);
- if (mmap_rc != 0) {
- ERROR("Error while unmapping SPM core manifest (%d).\n",
- mmap_rc);
- panic();
- }
-
- return rc;
+ WARN("Booting device without SPM initialization.\n");
}
- return 0;
+ return rc;
}
/*******************************************************************************
* Forward SMC to the other security state
******************************************************************************/
-static uint64_t spmd_smc_forward(uint32_t smc_fid, bool secure_origin,
- uint64_t x1, uint64_t x2, uint64_t x3,
- uint64_t x4, void *handle)
+static uint64_t spmd_smc_forward(uint32_t smc_fid,
+ bool secure_origin,
+ uint64_t x1,
+ uint64_t x2,
+ uint64_t x3,
+ uint64_t x4,
+ void *handle)
{
uint32_t secure_state_in = (secure_origin) ? SECURE : NON_SECURE;
uint32_t secure_state_out = (!secure_origin) ? SECURE : NON_SECURE;
@@ -367,19 +338,23 @@
* This function handles all SMCs in the range reserved for SPCI. Each call is
* either forwarded to the other security state or handled by the SPM dispatcher
******************************************************************************/
-uint64_t spmd_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
- uint64_t x3, uint64_t x4, void *cookie, void *handle,
+uint64_t spmd_smc_handler(uint32_t smc_fid,
+ uint64_t x1,
+ uint64_t x2,
+ uint64_t x3,
+ uint64_t x4,
+ void *cookie,
+ void *handle,
uint64_t flags)
{
- spmd_spm_core_context_t *ctx = &spm_core_context[plat_my_core_pos()];
+ spmd_spm_core_context_t *ctx = spmd_get_context();
bool secure_origin;
int32_t ret;
/* Determine which security state this SMC originated from */
secure_origin = is_caller_secure(flags);
- INFO("SPM: 0x%x, 0x%llx, 0x%llx, 0x%llx, 0x%llx, "
- "0x%llx, 0x%llx, 0x%llx\n",
+ INFO("SPM: 0x%x 0x%llx 0x%llx 0x%llx 0x%llx 0x%llx 0x%llx 0x%llx\n",
smc_fid, x1, x2, x3, x4, SMC_GET_GP(handle, CTX_GPREG_X5),
SMC_GET_GP(handle, CTX_GPREG_X6),
SMC_GET_GP(handle, CTX_GPREG_X7));
@@ -388,7 +363,7 @@
case SPCI_ERROR:
/*
* Check if this is the first invocation of this interface on
- * this CPU. If so, then indicate that the SPM core initialised
+ * this CPU. If so, then indicate that the SPM Core initialised
* unsuccessfully.
*/
if (secure_origin && (ctx->state == SPMC_STATE_RESET)) {
@@ -402,9 +377,9 @@
case SPCI_VERSION:
/*
* TODO: This is an optimization that the version information
- * provided by the SPM core manifest is returned by the SPM
+ * provided by the SPM Core manifest is returned by the SPM
* dispatcher. It might be a better idea to simply forward this
- * call to the SPM core and wash our hands completely.
+ * call to the SPM Core and wash our hands completely.
*/
ret = MAKE_SPCI_VERSION(spmc_attrs.major_version,
spmc_attrs.minor_version);
@@ -416,7 +391,7 @@
case SPCI_FEATURES:
/*
* This is an optional interface. Do the minimal checks and
- * forward to SPM core which will handle it if implemented.
+ * forward to SPM Core which will handle it if implemented.
*/
/*
@@ -428,42 +403,42 @@
SPCI_ERROR_NOT_SUPPORTED);
}
- /* Forward SMC from Normal world to the SPM core */
+ /* Forward SMC from Normal world to the SPM Core */
if (!secure_origin) {
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, handle);
- } else {
- /*
- * Return success if call was from secure world i.e. all
- * SPCI functions are supported. This is essentially a
- * nop.
- */
- SMC_RET8(handle, SPCI_SUCCESS_SMC32, x1, x2, x3, x4,
- SMC_GET_GP(handle, CTX_GPREG_X5),
- SMC_GET_GP(handle, CTX_GPREG_X6),
- SMC_GET_GP(handle, CTX_GPREG_X7));
}
+ /*
+ * Return success if call was from secure world i.e. all
+ * SPCI functions are supported. This is essentially a
+ * nop.
+ */
+ SMC_RET8(handle, SPCI_SUCCESS_SMC32, x1, x2, x3, x4,
+ SMC_GET_GP(handle, CTX_GPREG_X5),
+ SMC_GET_GP(handle, CTX_GPREG_X6),
+ SMC_GET_GP(handle, CTX_GPREG_X7));
+
break; /* not reached */
case SPCI_ID_GET:
/*
* Returns the ID of the calling SPCI component.
- */
+ */
if (!secure_origin) {
SMC_RET8(handle, SPCI_SUCCESS_SMC32,
SPCI_TARGET_INFO_MBZ, SPCI_NS_ENDPOINT_ID,
SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
SPCI_PARAM_MBZ);
- } else {
- SMC_RET8(handle, SPCI_SUCCESS_SMC32,
- SPCI_TARGET_INFO_MBZ, spmc_attrs.spmc_id,
- SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
- SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
- SPCI_PARAM_MBZ);
}
+ SMC_RET8(handle, SPCI_SUCCESS_SMC32,
+ SPCI_TARGET_INFO_MBZ, spmc_attrs.spmc_id,
+ SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
+ SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
+ SPCI_PARAM_MBZ);
+
break; /* not reached */
case SPCI_RX_RELEASE:
@@ -513,7 +488,7 @@
/*
* Check if this is the first invocation of this interface on
* this CPU from the Secure world. If so, then indicate that the
- * SPM core initialised successfully.
+ * SPM Core initialised successfully.
*/
if (secure_origin && (ctx->state == SPMC_STATE_RESET)) {
spmd_spm_core_sync_exit(0);
diff --git a/services/std_svc/spmd/spmd_private.h b/services/std_svc/spmd/spmd_private.h
index 0ad35c7..232031b 100644
--- a/services/std_svc/spmd/spmd_private.h
+++ b/services/std_svc/spmd/spmd_private.h
@@ -33,12 +33,6 @@
#include <services/spci_svc.h>
#include <stdint.h>
-/*
- * Convert a function no. in a FID to a bit position. All function nos. are
- * between 0 and 0x1f
- */
-#define SPCI_FNO_TO_BIT_POS(_fid) (1 << ((_fid) & U(0x1f)))
-
typedef enum spmc_state {
SPMC_STATE_RESET = 0,
SPMC_STATE_IDLE
@@ -60,21 +54,10 @@
#define SPCI_NS_ENDPOINT_ID U(0)
/* Mask and shift to check valid secure SPCI Endpoint ID. */
-#define SPMC_SECURE_ID_MASK 0x1
-#define SPMC_SECURE_ID_SHIFT 15
+#define SPMC_SECURE_ID_MASK U(1)
+#define SPMC_SECURE_ID_SHIFT U(15)
-/*
- * Data structure used by the SPM dispatcher (SPMD) in EL3 to track sequence of
- * SPCI calls from lower ELs.
- *
- * next_smc_bit_map: Per-cpu bit map of SMCs from each world that are expected
- * next.
- */
-typedef struct spmd_spci_context {
- uint32_t next_smc_bit_map[2];
-} spmd_spci_context_t;
-
-/* Functions used to enter/exit a Secure Partition synchronously */
+/* Functions used to enter/exit SPMC synchronously */
uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *ctx);
__dead2 void spmd_spm_core_sync_exit(uint64_t rc);
@@ -82,6 +65,9 @@
uint64_t spmd_spm_core_enter(uint64_t *c_rt_ctx);
void __dead2 spmd_spm_core_exit(uint64_t c_rt_ctx, uint64_t ret);
+/* SPMC context on current CPU get helper */
+spmd_spm_core_context_t *spmd_get_context(void);
+
#endif /* __ASSEMBLER__ */
#endif /* SPMD_PRIVATE_H */