Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 1 | # |
Antonio Nino Diaz | 8855e52 | 2019-01-21 11:53:29 +0000 | [diff] [blame] | 2 | # Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 3 | # |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | # SPDX-License-Identifier: BSD-3-Clause |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 5 | # |
| 6 | |
| 7 | # Default, static values for build variables, listed in alphabetic order. |
| 8 | # Dependencies between build options, if any, are handled in the top-level |
| 9 | # Makefile, after this file is included. This ensures that the former is better |
| 10 | # poised to handle dependencies, as all build variables would have a default |
| 11 | # value by then. |
| 12 | |
Antonio Nino Diaz | 8fd9d4d | 2018-08-08 16:28:43 +0100 | [diff] [blame] | 13 | # Use T32 by default |
| 14 | AARCH32_INSTRUCTION_SET := T32 |
| 15 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 16 | # The AArch32 Secure Payload to be built as BL32 image |
| 17 | AARCH32_SP := none |
| 18 | |
| 19 | # The Target build architecture. Supported values are: aarch64, aarch32. |
| 20 | ARCH := aarch64 |
| 21 | |
Jeenu Viswambharan | c877b41 | 2017-01-16 16:52:35 +0000 | [diff] [blame] | 22 | # ARM Architecture major and minor versions: 8.0 by default. |
| 23 | ARM_ARCH_MAJOR := 8 |
| 24 | ARM_ARCH_MINOR := 0 |
| 25 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 26 | # Base commit to perform code check on |
| 27 | BASE_COMMIT := origin/master |
| 28 | |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 29 | # Execute BL2 at EL3 |
| 30 | BL2_AT_EL3 := 0 |
| 31 | |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 32 | # BL2 image is stored in XIP memory, for now, this option is only supported |
| 33 | # when BL2_AT_EL3 is 1. |
| 34 | BL2_IN_XIP_MEM := 0 |
| 35 | |
Hadi Asyrafi | b90f207 | 2019-08-20 15:33:27 +0800 | [diff] [blame] | 36 | # Do dcache invalidate upon BL2 entry at EL3 |
| 37 | BL2_INV_DCACHE := 1 |
| 38 | |
Alexei Fedorov | 9fc5963 | 2019-05-24 12:17:09 +0100 | [diff] [blame] | 39 | # Select the branch protection features to use. |
| 40 | BRANCH_PROTECTION := 0 |
| 41 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 42 | # By default, consider that the platform may release several CPUs out of reset. |
| 43 | # The platform Makefile is free to override this value. |
| 44 | COLD_BOOT_SINGLE_CPU := 0 |
| 45 | |
Julius Werner | 3429c77 | 2017-06-09 15:17:15 -0700 | [diff] [blame] | 46 | # Flag to compile in coreboot support code. Exclude by default. The coreboot |
| 47 | # Makefile system will set this when compiling TF as part of a coreboot image. |
| 48 | COREBOOT := 0 |
| 49 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 50 | # For Chain of Trust |
| 51 | CREATE_KEYS := 1 |
| 52 | |
| 53 | # Build flag to include AArch32 registers in cpu context save and restore during |
| 54 | # world switch. This flag must be set to 0 for AArch64-only platforms. |
| 55 | CTX_INCLUDE_AARCH32_REGS := 1 |
| 56 | |
| 57 | # Include FP registers in cpu context |
| 58 | CTX_INCLUDE_FPREGS := 0 |
| 59 | |
Antonio Nino Diaz | 5283962 | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 60 | # Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This |
| 61 | # must be set to 1 if the platform wants to use this feature in the Secure |
| 62 | # world. It is not needed to use it in the Non-secure world. |
| 63 | CTX_INCLUDE_PAUTH_REGS := 0 |
| 64 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 65 | # Debug build |
| 66 | DEBUG := 0 |
| 67 | |
| 68 | # Build platform |
| 69 | DEFAULT_PLAT := fvp |
| 70 | |
Christoph Müllner | 9e4609f | 2019-04-24 09:45:30 +0200 | [diff] [blame] | 71 | # Disable the generation of the binary image (ELF only). |
| 72 | DISABLE_BIN_GENERATION := 0 |
| 73 | |
Soby Mathew | 209a60c | 2018-03-26 12:43:37 +0100 | [diff] [blame] | 74 | # Enable capability to disable authentication dynamically. Only meant for |
| 75 | # development platforms. |
| 76 | DYN_DISABLE_AUTH := 0 |
| 77 | |
Jeenu Viswambharan | 5f83591 | 2018-07-31 16:13:33 +0100 | [diff] [blame] | 78 | # Build option to enable MPAM for lower ELs |
| 79 | ENABLE_MPAM_FOR_LOWER_ELS := 0 |
| 80 | |
Soby Mathew | 3bd17c0 | 2018-08-28 11:13:55 +0100 | [diff] [blame] | 81 | # Flag to Enable Position Independant support (PIE) |
| 82 | ENABLE_PIE := 0 |
| 83 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 84 | # Flag to enable Performance Measurement Framework |
| 85 | ENABLE_PMF := 0 |
| 86 | |
| 87 | # Flag to enable PSCI STATs functionality |
| 88 | ENABLE_PSCI_STAT := 0 |
| 89 | |
| 90 | # Flag to enable runtime instrumentation using PMF |
| 91 | ENABLE_RUNTIME_INSTRUMENTATION := 0 |
| 92 | |
Douglas Raillard | 51faada | 2017-02-24 18:14:15 +0000 | [diff] [blame] | 93 | # Flag to enable stack corruption protection |
| 94 | ENABLE_STACK_PROTECTOR := 0 |
| 95 | |
Jeenu Viswambharan | 21b818c | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 96 | # Flag to enable exception handling in EL3 |
| 97 | EL3_EXCEPTION_HANDLING := 0 |
| 98 | |
Alexei Fedorov | 9fc5963 | 2019-05-24 12:17:09 +0100 | [diff] [blame] | 99 | # Flag to enable Branch Target Identification. |
| 100 | # Internal flag not meant for direct setting. |
| 101 | # Use BRANCH_PROTECTION to enable BTI. |
| 102 | ENABLE_BTI := 0 |
| 103 | |
| 104 | # Flag to enable Pointer Authentication. |
| 105 | # Internal flag not meant for direct setting. |
| 106 | # Use BRANCH_PROTECTION to enable PAUTH. |
Antonio Nino Diaz | b86048c | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 107 | ENABLE_PAUTH := 0 |
| 108 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 109 | # Build flag to treat usage of deprecated platform and framework APIs as error. |
| 110 | ERROR_DEPRECATED := 0 |
| 111 | |
Jeenu Viswambharan | 1a7c1cf | 2017-12-08 12:13:51 +0000 | [diff] [blame] | 112 | # Fault injection support |
| 113 | FAULT_INJECTION_SUPPORT := 0 |
| 114 | |
Masahiro Yamada | 1c75d5d | 2016-12-25 13:52:22 +0900 | [diff] [blame] | 115 | # Byte alignment that each component in FIP is aligned to |
| 116 | FIP_ALIGN := 0 |
| 117 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 118 | # Default FIP file name |
| 119 | FIP_NAME := fip.bin |
| 120 | |
| 121 | # Default FWU_FIP file name |
| 122 | FWU_FIP_NAME := fwu_fip.bin |
| 123 | |
| 124 | # For Chain of Trust |
| 125 | GENERATE_COT := 0 |
| 126 | |
Jeenu Viswambharan | 74dce7f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 127 | # Hint platform interrupt control layer that Group 0 interrupts are for EL3. By |
| 128 | # default, they are for Secure EL1. |
| 129 | GICV2_G0_FOR_EL3 := 0 |
| 130 | |
Jeenu Viswambharan | 76454ab | 2017-11-30 12:54:15 +0000 | [diff] [blame] | 131 | # Route External Aborts to EL3. Disabled by default; External Aborts are handled |
| 132 | # by lower ELs. |
| 133 | HANDLE_EA_EL3_FIRST := 0 |
| 134 | |
Jeenu Viswambharan | 3c251af | 2017-01-04 13:51:42 +0000 | [diff] [blame] | 135 | # Whether system coherency is managed in hardware, without explicit software |
| 136 | # operations. |
| 137 | HW_ASSISTED_COHERENCY := 0 |
| 138 | |
Soby Mathew | 2091755 | 2017-08-31 11:49:32 +0100 | [diff] [blame] | 139 | # Set the default algorithm for the generation of Trusted Board Boot keys |
| 140 | KEY_ALG := rsa |
| 141 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 142 | # NS timer register save and restore |
| 143 | NS_TIMER_SWITCH := 0 |
| 144 | |
Varun Wadekar | 77f1f7a | 2019-01-31 09:22:30 -0800 | [diff] [blame] | 145 | # Include lib/libc in the final image |
| 146 | OVERRIDE_LIBC := 0 |
| 147 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 148 | # Build PL011 UART driver in minimal generic UART mode |
| 149 | PL011_GENERIC_UART := 0 |
| 150 | |
| 151 | # By default, consider that the platform's reset address is not programmable. |
| 152 | # The platform Makefile is free to override this value. |
| 153 | PROGRAMMABLE_RESET_ADDRESS := 0 |
| 154 | |
Antonio Nino Diaz | 7330861 | 2019-02-28 13:35:21 +0000 | [diff] [blame] | 155 | # Flag used to choose the power state format: Extended State-ID or Original |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 156 | PSCI_EXTENDED_STATE_ID := 0 |
| 157 | |
Jeenu Viswambharan | 14c6016 | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 158 | # Enable RAS support |
| 159 | RAS_EXTENSION := 0 |
| 160 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 161 | # By default, BL1 acts as the reset handler, not BL31 |
| 162 | RESET_TO_BL31 := 0 |
| 163 | |
| 164 | # For Chain of Trust |
| 165 | SAVE_KEYS := 0 |
| 166 | |
Jeenu Viswambharan | b7cb133 | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 167 | # Software Delegated Exception support |
| 168 | SDEI_SUPPORT := 0 |
| 169 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 170 | # Whether code and read-only data should be put on separate memory pages. The |
| 171 | # platform Makefile is free to override this value. |
| 172 | SEPARATE_CODE_AND_RODATA := 0 |
| 173 | |
Daniel Boulby | 1dcc28c | 2018-09-18 11:45:51 +0100 | [diff] [blame] | 174 | # If the BL31 image initialisation code is recalimed after use for the secondary |
| 175 | # cores stack |
| 176 | RECLAIM_INIT_CODE := 0 |
| 177 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 178 | # SPD choice |
| 179 | SPD := none |
| 180 | |
Antonio Nino Diaz | 2fccb22 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 181 | # For including the Secure Partition Manager |
| 182 | ENABLE_SPM := 0 |
| 183 | |
Antonio Nino Diaz | 8855e52 | 2019-01-21 11:53:29 +0000 | [diff] [blame] | 184 | # Use the SPM based on MM |
| 185 | SPM_MM := 1 |
Antonio Nino Diaz | 2d7b9e5 | 2018-10-30 11:08:08 +0000 | [diff] [blame] | 186 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 187 | # Flag to introduce an infinite loop in BL1 just before it exits into the next |
| 188 | # image. This is meant to help debugging the post-BL2 phase. |
| 189 | SPIN_ON_BL1_EXIT := 0 |
| 190 | |
| 191 | # Flags to build TF with Trusted Boot support |
| 192 | TRUSTED_BOARD_BOOT := 0 |
| 193 | |
Antonio Nino Diaz | e23e057 | 2018-09-25 09:41:08 +0100 | [diff] [blame] | 194 | # Build option to choose whether Trusted Firmware uses Coherent memory or not. |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 195 | USE_COHERENT_MEM := 1 |
| 196 | |
Antonio Nino Diaz | e23e057 | 2018-09-25 09:41:08 +0100 | [diff] [blame] | 197 | # Build option to choose whether Trusted Firmware uses library at ROM |
| 198 | USE_ROMLIB := 0 |
Roberto Vargas | 5accce5 | 2018-05-22 16:05:42 +0100 | [diff] [blame] | 199 | |
Masahiro Yamada | bb41eb7 | 2017-05-22 12:11:24 +0900 | [diff] [blame] | 200 | # Use tbbr_oid.h instead of platform_oid.h |
Antonio Nino Diaz | e23e057 | 2018-09-25 09:41:08 +0100 | [diff] [blame] | 201 | USE_TBBR_DEFS := 1 |
Masahiro Yamada | bb41eb7 | 2017-05-22 12:11:24 +0900 | [diff] [blame] | 202 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 203 | # Build verbosity |
| 204 | V := 0 |
Soby Mathew | bcc3c49 | 2017-04-10 22:35:42 +0100 | [diff] [blame] | 205 | |
| 206 | # Whether to enable D-Cache early during warm boot. This is usually |
| 207 | # applicable for platforms wherein interconnect programming is not |
| 208 | # required to enable cache coherency after warm reset (eg: single cluster |
| 209 | # platforms). |
| 210 | WARMBOOT_ENABLE_DCACHE_EARLY := 0 |
dp-arm | d832aee | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 211 | |
Dimitris Papastamos | c776dee | 2017-10-13 15:07:45 +0100 | [diff] [blame] | 212 | # Build option to enable/disable the Statistical Profiling Extensions |
dp-arm | d832aee | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 213 | ENABLE_SPE_FOR_LOWER_ELS := 1 |
| 214 | |
Dimitris Papastamos | c776dee | 2017-10-13 15:07:45 +0100 | [diff] [blame] | 215 | # SPE is only supported on AArch64 so disable it on AArch32. |
dp-arm | d832aee | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 216 | ifeq (${ARCH},aarch32) |
| 217 | override ENABLE_SPE_FOR_LOWER_ELS := 0 |
dp-arm | d832aee | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 218 | endif |
Dimitris Papastamos | 0319a97 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 219 | |
Justin Chadwell | 9dd9438 | 2019-07-18 14:25:33 +0100 | [diff] [blame] | 220 | # Include Memory Tagging Extension registers in cpu context. This must be set |
| 221 | # to 1 if the platform wants to use this feature in the Secure world and MTE is |
| 222 | # enabled at ELX. |
| 223 | CTX_INCLUDE_MTE_REGS := 0 |
| 224 | |
Dimitris Papastamos | 0319a97 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 225 | ENABLE_AMU := 0 |
David Cunado | 1a85337 | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 226 | |
| 227 | # By default, enable Scalable Vector Extension if implemented for Non-secure |
| 228 | # lower ELs |
| 229 | # Note SVE is only supported on AArch64 - therefore do not enable in AArch32 |
| 230 | ifneq (${ARCH},aarch32) |
| 231 | ENABLE_SVE_FOR_NS := 1 |
| 232 | else |
| 233 | override ENABLE_SVE_FOR_NS := 0 |
| 234 | endif |
Justin Chadwell | 1f46197 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 235 | |
| 236 | SANITIZE_UB := off |
Soby Mathew | c97cba4 | 2019-09-25 14:03:41 +0100 | [diff] [blame] | 237 | |
| 238 | # For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock |
| 239 | # implementation variant using the ARMv8.1-LSE compare-and-swap instruction. |
| 240 | # Default: disabled |
| 241 | USE_SPINLOCK_CAS := 0 |