Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 1 | # |
Dan Handley | bc1a03c | 2018-02-27 16:03:58 +0000 | [diff] [blame] | 2 | # Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 3 | # |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | # SPDX-License-Identifier: BSD-3-Clause |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 5 | # |
| 6 | |
| 7 | # Default, static values for build variables, listed in alphabetic order. |
| 8 | # Dependencies between build options, if any, are handled in the top-level |
| 9 | # Makefile, after this file is included. This ensures that the former is better |
| 10 | # poised to handle dependencies, as all build variables would have a default |
| 11 | # value by then. |
| 12 | |
| 13 | # The AArch32 Secure Payload to be built as BL32 image |
| 14 | AARCH32_SP := none |
| 15 | |
| 16 | # The Target build architecture. Supported values are: aarch64, aarch32. |
| 17 | ARCH := aarch64 |
| 18 | |
Jeenu Viswambharan | c877b41 | 2017-01-16 16:52:35 +0000 | [diff] [blame] | 19 | # ARM Architecture major and minor versions: 8.0 by default. |
| 20 | ARM_ARCH_MAJOR := 8 |
| 21 | ARM_ARCH_MINOR := 0 |
| 22 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 23 | # Determine the version of ARM GIC architecture to use for interrupt management |
| 24 | # in EL3. The platform port can change this value if needed. |
| 25 | ARM_GIC_ARCH := 2 |
| 26 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 27 | # Base commit to perform code check on |
| 28 | BASE_COMMIT := origin/master |
| 29 | |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 30 | # Execute BL2 at EL3 |
| 31 | BL2_AT_EL3 := 0 |
| 32 | |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 33 | # BL2 image is stored in XIP memory, for now, this option is only supported |
| 34 | # when BL2_AT_EL3 is 1. |
| 35 | BL2_IN_XIP_MEM := 0 |
| 36 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 37 | # By default, consider that the platform may release several CPUs out of reset. |
| 38 | # The platform Makefile is free to override this value. |
| 39 | COLD_BOOT_SINGLE_CPU := 0 |
| 40 | |
Julius Werner | 3429c77 | 2017-06-09 15:17:15 -0700 | [diff] [blame] | 41 | # Flag to compile in coreboot support code. Exclude by default. The coreboot |
| 42 | # Makefile system will set this when compiling TF as part of a coreboot image. |
| 43 | COREBOOT := 0 |
| 44 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 45 | # For Chain of Trust |
| 46 | CREATE_KEYS := 1 |
| 47 | |
| 48 | # Build flag to include AArch32 registers in cpu context save and restore during |
| 49 | # world switch. This flag must be set to 0 for AArch64-only platforms. |
| 50 | CTX_INCLUDE_AARCH32_REGS := 1 |
| 51 | |
| 52 | # Include FP registers in cpu context |
| 53 | CTX_INCLUDE_FPREGS := 0 |
| 54 | |
| 55 | # Debug build |
| 56 | DEBUG := 0 |
| 57 | |
| 58 | # Build platform |
| 59 | DEFAULT_PLAT := fvp |
| 60 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 61 | # Flag to enable Performance Measurement Framework |
| 62 | ENABLE_PMF := 0 |
| 63 | |
| 64 | # Flag to enable PSCI STATs functionality |
| 65 | ENABLE_PSCI_STAT := 0 |
| 66 | |
| 67 | # Flag to enable runtime instrumentation using PMF |
| 68 | ENABLE_RUNTIME_INSTRUMENTATION := 0 |
| 69 | |
Douglas Raillard | 51faada | 2017-02-24 18:14:15 +0000 | [diff] [blame] | 70 | # Flag to enable stack corruption protection |
| 71 | ENABLE_STACK_PROTECTOR := 0 |
| 72 | |
Jeenu Viswambharan | 21b818c | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 73 | # Flag to enable exception handling in EL3 |
| 74 | EL3_EXCEPTION_HANDLING := 0 |
| 75 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 76 | # Build flag to treat usage of deprecated platform and framework APIs as error. |
| 77 | ERROR_DEPRECATED := 0 |
| 78 | |
Masahiro Yamada | 1c75d5d | 2016-12-25 13:52:22 +0900 | [diff] [blame] | 79 | # Byte alignment that each component in FIP is aligned to |
| 80 | FIP_ALIGN := 0 |
| 81 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 82 | # Default FIP file name |
| 83 | FIP_NAME := fip.bin |
| 84 | |
| 85 | # Default FWU_FIP file name |
| 86 | FWU_FIP_NAME := fwu_fip.bin |
| 87 | |
| 88 | # For Chain of Trust |
| 89 | GENERATE_COT := 0 |
| 90 | |
Jeenu Viswambharan | 74dce7f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 91 | # Hint platform interrupt control layer that Group 0 interrupts are for EL3. By |
| 92 | # default, they are for Secure EL1. |
| 93 | GICV2_G0_FOR_EL3 := 0 |
| 94 | |
Jeenu Viswambharan | 3c251af | 2017-01-04 13:51:42 +0000 | [diff] [blame] | 95 | # Whether system coherency is managed in hardware, without explicit software |
| 96 | # operations. |
| 97 | HW_ASSISTED_COHERENCY := 0 |
| 98 | |
Soby Mathew | 2091755 | 2017-08-31 11:49:32 +0100 | [diff] [blame] | 99 | # Set the default algorithm for the generation of Trusted Board Boot keys |
| 100 | KEY_ALG := rsa |
| 101 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 102 | # Flag to enable new version of image loading |
| 103 | LOAD_IMAGE_V2 := 0 |
| 104 | |
Dan Handley | bc1a03c | 2018-02-27 16:03:58 +0000 | [diff] [blame] | 105 | # Enable use of the console API allowing multiple consoles to be registered |
| 106 | # at the same time. |
| 107 | MULTI_CONSOLE_API := 0 |
Julius Werner | 9536bae | 2017-07-31 18:15:11 -0700 | [diff] [blame] | 108 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 109 | # NS timer register save and restore |
| 110 | NS_TIMER_SWITCH := 0 |
| 111 | |
| 112 | # Build PL011 UART driver in minimal generic UART mode |
| 113 | PL011_GENERIC_UART := 0 |
| 114 | |
| 115 | # By default, consider that the platform's reset address is not programmable. |
| 116 | # The platform Makefile is free to override this value. |
| 117 | PROGRAMMABLE_RESET_ADDRESS := 0 |
| 118 | |
| 119 | # Flag used to choose the power state format viz Extended State-ID or the |
| 120 | # Original format. |
| 121 | PSCI_EXTENDED_STATE_ID := 0 |
| 122 | |
| 123 | # By default, BL1 acts as the reset handler, not BL31 |
| 124 | RESET_TO_BL31 := 0 |
| 125 | |
| 126 | # For Chain of Trust |
| 127 | SAVE_KEYS := 0 |
| 128 | |
Jeenu Viswambharan | b7cb133 | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 129 | # Software Delegated Exception support |
| 130 | SDEI_SUPPORT := 0 |
| 131 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 132 | # Whether code and read-only data should be put on separate memory pages. The |
| 133 | # platform Makefile is free to override this value. |
| 134 | SEPARATE_CODE_AND_RODATA := 0 |
| 135 | |
Antonio Nino Diaz | 2f37046 | 2018-04-23 15:43:29 +0100 | [diff] [blame] | 136 | # Default to SMCCC Version 1.X |
| 137 | SMCCC_MAJOR_VERSION := 1 |
| 138 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 139 | # SPD choice |
| 140 | SPD := none |
| 141 | |
Antonio Nino Diaz | 2fccb22 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 142 | # For including the Secure Partition Manager |
| 143 | ENABLE_SPM := 0 |
| 144 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 145 | # Flag to introduce an infinite loop in BL1 just before it exits into the next |
| 146 | # image. This is meant to help debugging the post-BL2 phase. |
| 147 | SPIN_ON_BL1_EXIT := 0 |
| 148 | |
| 149 | # Flags to build TF with Trusted Boot support |
| 150 | TRUSTED_BOARD_BOOT := 0 |
| 151 | |
| 152 | # Build option to choose whether Trusted firmware uses Coherent memory or not. |
| 153 | USE_COHERENT_MEM := 1 |
| 154 | |
Masahiro Yamada | bb41eb7 | 2017-05-22 12:11:24 +0900 | [diff] [blame] | 155 | # Use tbbr_oid.h instead of platform_oid.h |
| 156 | USE_TBBR_DEFS = $(ERROR_DEPRECATED) |
| 157 | |
Jeenu Viswambharan | 2fae4b1 | 2016-10-24 14:31:51 +0100 | [diff] [blame] | 158 | # Build verbosity |
| 159 | V := 0 |
Soby Mathew | bcc3c49 | 2017-04-10 22:35:42 +0100 | [diff] [blame] | 160 | |
| 161 | # Whether to enable D-Cache early during warm boot. This is usually |
| 162 | # applicable for platforms wherein interconnect programming is not |
| 163 | # required to enable cache coherency after warm reset (eg: single cluster |
| 164 | # platforms). |
| 165 | WARMBOOT_ENABLE_DCACHE_EARLY := 0 |
dp-arm | d832aee | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 166 | |
Dimitris Papastamos | c776dee | 2017-10-13 15:07:45 +0100 | [diff] [blame] | 167 | # Build option to enable/disable the Statistical Profiling Extensions |
dp-arm | d832aee | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 168 | ENABLE_SPE_FOR_LOWER_ELS := 1 |
| 169 | |
Dimitris Papastamos | c776dee | 2017-10-13 15:07:45 +0100 | [diff] [blame] | 170 | # SPE is only supported on AArch64 so disable it on AArch32. |
dp-arm | d832aee | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 171 | ifeq (${ARCH},aarch32) |
| 172 | override ENABLE_SPE_FOR_LOWER_ELS := 0 |
dp-arm | d832aee | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 173 | endif |
Dimitris Papastamos | 0319a97 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 174 | |
| 175 | ENABLE_AMU := 0 |
David Cunado | 1a85337 | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 176 | |
| 177 | # By default, enable Scalable Vector Extension if implemented for Non-secure |
| 178 | # lower ELs |
| 179 | # Note SVE is only supported on AArch64 - therefore do not enable in AArch32 |
| 180 | ifneq (${ARCH},aarch32) |
| 181 | ENABLE_SVE_FOR_NS := 1 |
| 182 | else |
| 183 | override ENABLE_SVE_FOR_NS := 0 |
| 184 | endif |