Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | 17e84ee | 2018-03-22 08:57:52 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <assert.h> |
| 10 | #include <debug.h> |
| 11 | #include <gic_common.h> |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 12 | #include <interrupt_props.h> |
Soby Mathew | e9ec3ce | 2016-02-01 17:59:22 +0000 | [diff] [blame] | 13 | #include "../common/gic_common_private.h" |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 14 | #include "gicv3_private.h" |
| 15 | |
| 16 | /* |
| 17 | * Accessor to read the GIC Distributor IGRPMODR corresponding to the |
| 18 | * interrupt `id`, 32 interrupt IDs at a time. |
| 19 | */ |
| 20 | unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id) |
| 21 | { |
| 22 | unsigned n = id >> IGRPMODR_SHIFT; |
| 23 | return mmio_read_32(base + GICD_IGRPMODR + (n << 2)); |
| 24 | } |
| 25 | |
| 26 | /* |
| 27 | * Accessor to write the GIC Distributor IGRPMODR corresponding to the |
| 28 | * interrupt `id`, 32 interrupt IDs at a time. |
| 29 | */ |
| 30 | void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val) |
| 31 | { |
| 32 | unsigned n = id >> IGRPMODR_SHIFT; |
| 33 | mmio_write_32(base + GICD_IGRPMODR + (n << 2), val); |
| 34 | } |
| 35 | |
| 36 | /* |
| 37 | * Accessor to get the bit corresponding to interrupt ID |
| 38 | * in GIC Distributor IGRPMODR. |
| 39 | */ |
| 40 | unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id) |
| 41 | { |
| 42 | unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); |
| 43 | unsigned int reg_val = gicd_read_igrpmodr(base, id); |
| 44 | |
| 45 | return (reg_val >> bit_num) & 0x1; |
| 46 | } |
| 47 | |
| 48 | /* |
| 49 | * Accessor to set the bit corresponding to interrupt ID |
| 50 | * in GIC Distributor IGRPMODR. |
| 51 | */ |
| 52 | void gicd_set_igrpmodr(uintptr_t base, unsigned int id) |
| 53 | { |
| 54 | unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); |
| 55 | unsigned int reg_val = gicd_read_igrpmodr(base, id); |
| 56 | |
| 57 | gicd_write_igrpmodr(base, id, reg_val | (1 << bit_num)); |
| 58 | } |
| 59 | |
| 60 | /* |
| 61 | * Accessor to clear the bit corresponding to interrupt ID |
| 62 | * in GIC Distributor IGRPMODR. |
| 63 | */ |
| 64 | void gicd_clr_igrpmodr(uintptr_t base, unsigned int id) |
| 65 | { |
| 66 | unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); |
| 67 | unsigned int reg_val = gicd_read_igrpmodr(base, id); |
| 68 | |
| 69 | gicd_write_igrpmodr(base, id, reg_val & ~(1 << bit_num)); |
| 70 | } |
| 71 | |
| 72 | /* |
| 73 | * Accessor to read the GIC Re-distributor IPRIORITYR corresponding to the |
| 74 | * interrupt `id`, 4 interrupts IDs at a time. |
| 75 | */ |
| 76 | unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id) |
| 77 | { |
| 78 | unsigned n = id >> IPRIORITYR_SHIFT; |
| 79 | return mmio_read_32(base + GICR_IPRIORITYR + (n << 2)); |
| 80 | } |
| 81 | |
| 82 | /* |
| 83 | * Accessor to write the GIC Re-distributor IPRIORITYR corresponding to the |
| 84 | * interrupt `id`, 4 interrupts IDs at a time. |
| 85 | */ |
| 86 | void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) |
| 87 | { |
| 88 | unsigned n = id >> IPRIORITYR_SHIFT; |
| 89 | mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val); |
| 90 | } |
| 91 | |
| 92 | /* |
| 93 | * Accessor to get the bit corresponding to interrupt ID |
| 94 | * from GIC Re-distributor IGROUPR0. |
| 95 | */ |
| 96 | unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id) |
| 97 | { |
| 98 | unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); |
| 99 | unsigned int reg_val = gicr_read_igroupr0(base); |
| 100 | |
| 101 | return (reg_val >> bit_num) & 0x1; |
| 102 | } |
| 103 | |
| 104 | /* |
| 105 | * Accessor to set the bit corresponding to interrupt ID |
| 106 | * in GIC Re-distributor IGROUPR0. |
| 107 | */ |
| 108 | void gicr_set_igroupr0(uintptr_t base, unsigned int id) |
| 109 | { |
| 110 | unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); |
| 111 | unsigned int reg_val = gicr_read_igroupr0(base); |
| 112 | |
| 113 | gicr_write_igroupr0(base, reg_val | (1 << bit_num)); |
| 114 | } |
| 115 | |
| 116 | /* |
| 117 | * Accessor to clear the bit corresponding to interrupt ID |
| 118 | * in GIC Re-distributor IGROUPR0. |
| 119 | */ |
| 120 | void gicr_clr_igroupr0(uintptr_t base, unsigned int id) |
| 121 | { |
| 122 | unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); |
| 123 | unsigned int reg_val = gicr_read_igroupr0(base); |
| 124 | |
| 125 | gicr_write_igroupr0(base, reg_val & ~(1 << bit_num)); |
| 126 | } |
| 127 | |
| 128 | /* |
| 129 | * Accessor to get the bit corresponding to interrupt ID |
| 130 | * from GIC Re-distributor IGRPMODR0. |
| 131 | */ |
| 132 | unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id) |
| 133 | { |
| 134 | unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); |
| 135 | unsigned int reg_val = gicr_read_igrpmodr0(base); |
| 136 | |
| 137 | return (reg_val >> bit_num) & 0x1; |
| 138 | } |
| 139 | |
| 140 | /* |
| 141 | * Accessor to set the bit corresponding to interrupt ID |
| 142 | * in GIC Re-distributor IGRPMODR0. |
| 143 | */ |
| 144 | void gicr_set_igrpmodr0(uintptr_t base, unsigned int id) |
| 145 | { |
| 146 | unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); |
| 147 | unsigned int reg_val = gicr_read_igrpmodr0(base); |
| 148 | |
| 149 | gicr_write_igrpmodr0(base, reg_val | (1 << bit_num)); |
| 150 | } |
| 151 | |
| 152 | /* |
| 153 | * Accessor to clear the bit corresponding to interrupt ID |
| 154 | * in GIC Re-distributor IGRPMODR0. |
| 155 | */ |
| 156 | void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id) |
| 157 | { |
| 158 | unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); |
| 159 | unsigned int reg_val = gicr_read_igrpmodr0(base); |
| 160 | |
| 161 | gicr_write_igrpmodr0(base, reg_val & ~(1 << bit_num)); |
| 162 | } |
| 163 | |
| 164 | /* |
| 165 | * Accessor to set the bit corresponding to interrupt ID |
| 166 | * in GIC Re-distributor ISENABLER0. |
| 167 | */ |
| 168 | void gicr_set_isenabler0(uintptr_t base, unsigned int id) |
| 169 | { |
| 170 | unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); |
| 171 | |
| 172 | gicr_write_isenabler0(base, (1 << bit_num)); |
| 173 | } |
| 174 | |
Soby Mathew | 38a7861 | 2016-01-15 14:20:57 +0000 | [diff] [blame] | 175 | /* |
Jeenu Viswambharan | cbd3f37 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 176 | * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor |
Jeenu Viswambharan | 979225f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 177 | * ICENABLER0. |
| 178 | */ |
| 179 | void gicr_set_icenabler0(uintptr_t base, unsigned int id) |
| 180 | { |
| 181 | unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); |
| 182 | |
| 183 | gicr_write_icenabler0(base, (1 << bit_num)); |
| 184 | } |
| 185 | |
| 186 | /* |
| 187 | * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor |
Jeenu Viswambharan | cbd3f37 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 188 | * ISACTIVER0. |
| 189 | */ |
| 190 | unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id) |
| 191 | { |
| 192 | unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); |
| 193 | unsigned int reg_val = gicr_read_isactiver0(base); |
| 194 | |
| 195 | return (reg_val >> bit_num) & 0x1; |
| 196 | } |
| 197 | |
| 198 | /* |
Jeenu Viswambharan | a2816a1 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 199 | * Accessor to clear the bit corresponding to interrupt ID in GIC Re-distributor |
| 200 | * ICPENDRR0. |
| 201 | */ |
| 202 | void gicr_set_icpendr0(uintptr_t base, unsigned int id) |
| 203 | { |
| 204 | unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); |
| 205 | |
| 206 | gicr_write_icpendr0(base, (1 << bit_num)); |
| 207 | } |
| 208 | |
| 209 | /* |
| 210 | * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor |
| 211 | * ISPENDR0. |
| 212 | */ |
| 213 | void gicr_set_ispendr0(uintptr_t base, unsigned int id) |
| 214 | { |
| 215 | unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); |
| 216 | |
| 217 | gicr_write_ispendr0(base, (1 << bit_num)); |
| 218 | } |
| 219 | |
| 220 | /* |
Soby Mathew | 38a7861 | 2016-01-15 14:20:57 +0000 | [diff] [blame] | 221 | * Accessor to set the byte corresponding to interrupt ID |
| 222 | * in GIC Re-distributor IPRIORITYR. |
| 223 | */ |
| 224 | void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) |
| 225 | { |
| 226 | mmio_write_8(base + GICR_IPRIORITYR + id, pri & GIC_PRI_MASK); |
| 227 | } |
| 228 | |
Jeenu Viswambharan | 2296610 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 229 | /* |
| 230 | * Accessor to set the bit fields corresponding to interrupt ID |
| 231 | * in GIC Re-distributor ICFGR0. |
| 232 | */ |
| 233 | void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg) |
| 234 | { |
Jeenu Viswambharan | 17e84ee | 2018-03-22 08:57:52 +0000 | [diff] [blame^] | 235 | /* Interrupt configuration is a 2-bit field */ |
| 236 | unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1); |
| 237 | unsigned int bit_shift = bit_num << 1; |
| 238 | |
Jeenu Viswambharan | 2296610 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 239 | uint32_t reg_val = gicr_read_icfgr0(base); |
| 240 | |
| 241 | /* Clear the field, and insert required configuration */ |
Jeenu Viswambharan | 17e84ee | 2018-03-22 08:57:52 +0000 | [diff] [blame^] | 242 | reg_val &= ~(GIC_CFG_MASK << bit_shift); |
| 243 | reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift); |
Jeenu Viswambharan | 2296610 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 244 | |
| 245 | gicr_write_icfgr0(base, reg_val); |
| 246 | } |
| 247 | |
| 248 | /* |
| 249 | * Accessor to set the bit fields corresponding to interrupt ID |
| 250 | * in GIC Re-distributor ICFGR1. |
| 251 | */ |
| 252 | void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg) |
| 253 | { |
Jeenu Viswambharan | 17e84ee | 2018-03-22 08:57:52 +0000 | [diff] [blame^] | 254 | /* Interrupt configuration is a 2-bit field */ |
| 255 | unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1); |
| 256 | unsigned int bit_shift = bit_num << 1; |
| 257 | |
Jeenu Viswambharan | 2296610 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 258 | uint32_t reg_val = gicr_read_icfgr1(base); |
| 259 | |
| 260 | /* Clear the field, and insert required configuration */ |
Jeenu Viswambharan | 17e84ee | 2018-03-22 08:57:52 +0000 | [diff] [blame^] | 261 | reg_val &= ~(GIC_CFG_MASK << bit_shift); |
| 262 | reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift); |
Jeenu Viswambharan | 2296610 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 263 | |
| 264 | gicr_write_icfgr1(base, reg_val); |
| 265 | } |
| 266 | |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 267 | /****************************************************************************** |
| 268 | * This function marks the core as awake in the re-distributor and |
| 269 | * ensures that the interface is active. |
| 270 | *****************************************************************************/ |
| 271 | void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) |
| 272 | { |
| 273 | /* |
| 274 | * The WAKER_PS_BIT should be changed to 0 |
| 275 | * only when WAKER_CA_BIT is 1. |
| 276 | */ |
| 277 | assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT); |
| 278 | |
| 279 | /* Mark the connected core as awake */ |
| 280 | gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); |
| 281 | |
| 282 | /* Wait till the WAKER_CA_BIT changes to 0 */ |
| 283 | while (gicr_read_waker(gicr_base) & WAKER_CA_BIT) |
| 284 | ; |
| 285 | } |
| 286 | |
| 287 | |
| 288 | /****************************************************************************** |
| 289 | * This function marks the core as asleep in the re-distributor and ensures |
| 290 | * that the interface is quiescent. |
| 291 | *****************************************************************************/ |
| 292 | void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) |
| 293 | { |
| 294 | /* Mark the connected core as asleep */ |
| 295 | gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); |
| 296 | |
| 297 | /* Wait till the WAKER_CA_BIT changes to 1 */ |
| 298 | while (!(gicr_read_waker(gicr_base) & WAKER_CA_BIT)) |
| 299 | ; |
| 300 | } |
| 301 | |
| 302 | |
| 303 | /******************************************************************************* |
| 304 | * This function probes the Redistributor frames when the driver is initialised |
| 305 | * and saves their base addresses. These base addresses are used later to |
| 306 | * initialise each Redistributor interface. |
| 307 | ******************************************************************************/ |
| 308 | void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, |
| 309 | unsigned int rdistif_num, |
| 310 | uintptr_t gicr_base, |
| 311 | mpidr_hash_fn mpidr_to_core_pos) |
| 312 | { |
Soby Mathew | 4c0d039 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 313 | u_register_t mpidr; |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 314 | unsigned int proc_num; |
| 315 | unsigned long long typer_val; |
| 316 | uintptr_t rdistif_base = gicr_base; |
| 317 | |
| 318 | assert(rdistif_base_addrs); |
| 319 | |
| 320 | /* |
| 321 | * Iterate over the Redistributor frames. Store the base address of each |
| 322 | * frame in the platform provided array. Use the "Processor Number" |
| 323 | * field to index into the array if the platform has not provided a hash |
| 324 | * function to convert an MPIDR (obtained from the "Affinity Value" |
| 325 | * field into a linear index. |
| 326 | */ |
| 327 | do { |
| 328 | typer_val = gicr_read_typer(rdistif_base); |
| 329 | if (mpidr_to_core_pos) { |
| 330 | mpidr = mpidr_from_gicr_typer(typer_val); |
| 331 | proc_num = mpidr_to_core_pos(mpidr); |
| 332 | } else { |
| 333 | proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & |
| 334 | TYPER_PROC_NUM_MASK; |
| 335 | } |
| 336 | assert(proc_num < rdistif_num); |
| 337 | rdistif_base_addrs[proc_num] = rdistif_base; |
| 338 | rdistif_base += (1 << GICR_PCPUBASE_SHIFT); |
| 339 | } while (!(typer_val & TYPER_LAST_BIT)); |
| 340 | } |
| 341 | |
| 342 | /******************************************************************************* |
| 343 | * Helper function to configure the default attributes of SPIs. |
| 344 | ******************************************************************************/ |
| 345 | void gicv3_spis_configure_defaults(uintptr_t gicd_base) |
| 346 | { |
| 347 | unsigned int index, num_ints; |
| 348 | |
| 349 | num_ints = gicd_read_typer(gicd_base); |
| 350 | num_ints &= TYPER_IT_LINES_NO_MASK; |
| 351 | num_ints = (num_ints + 1) << 5; |
| 352 | |
| 353 | /* |
| 354 | * Treat all SPIs as G1NS by default. The number of interrupts is |
| 355 | * calculated as 32 * (IT_LINES + 1). We do 32 at a time. |
| 356 | */ |
| 357 | for (index = MIN_SPI_ID; index < num_ints; index += 32) |
| 358 | gicd_write_igroupr(gicd_base, index, ~0U); |
| 359 | |
| 360 | /* Setup the default SPI priorities doing four at a time */ |
| 361 | for (index = MIN_SPI_ID; index < num_ints; index += 4) |
| 362 | gicd_write_ipriorityr(gicd_base, |
| 363 | index, |
| 364 | GICD_IPRIORITYR_DEF_VAL); |
| 365 | |
| 366 | /* |
| 367 | * Treat all SPIs as level triggered by default, write 16 at |
| 368 | * a time |
| 369 | */ |
| 370 | for (index = MIN_SPI_ID; index < num_ints; index += 16) |
| 371 | gicd_write_icfgr(gicd_base, index, 0); |
| 372 | } |
| 373 | |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 374 | #if !ERROR_DEPRECATED |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 375 | /******************************************************************************* |
| 376 | * Helper function to configure secure G0 and G1S SPIs. |
| 377 | ******************************************************************************/ |
| 378 | void gicv3_secure_spis_configure(uintptr_t gicd_base, |
| 379 | unsigned int num_ints, |
| 380 | const unsigned int *sec_intr_list, |
| 381 | unsigned int int_grp) |
| 382 | { |
| 383 | unsigned int index, irq_num; |
Soby Mathew | 4c0d039 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 384 | unsigned long long gic_affinity_val; |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 385 | |
Soby Mathew | 03ffb6b | 2015-12-03 14:12:54 +0000 | [diff] [blame] | 386 | assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 387 | /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ |
| 388 | assert(num_ints ? (uintptr_t)sec_intr_list : 1); |
| 389 | |
| 390 | for (index = 0; index < num_ints; index++) { |
| 391 | irq_num = sec_intr_list[index]; |
| 392 | if (irq_num >= MIN_SPI_ID) { |
| 393 | |
| 394 | /* Configure this interrupt as a secure interrupt */ |
| 395 | gicd_clr_igroupr(gicd_base, irq_num); |
| 396 | |
| 397 | /* Configure this interrupt as G0 or a G1S interrupt */ |
Soby Mathew | 03ffb6b | 2015-12-03 14:12:54 +0000 | [diff] [blame] | 398 | if (int_grp == INTR_GROUP1S) |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 399 | gicd_set_igrpmodr(gicd_base, irq_num); |
| 400 | else |
| 401 | gicd_clr_igrpmodr(gicd_base, irq_num); |
| 402 | |
| 403 | /* Set the priority of this interrupt */ |
Soby Mathew | 38a7861 | 2016-01-15 14:20:57 +0000 | [diff] [blame] | 404 | gicd_set_ipriorityr(gicd_base, |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 405 | irq_num, |
| 406 | GIC_HIGHEST_SEC_PRIORITY); |
| 407 | |
| 408 | /* Target SPIs to the primary CPU */ |
| 409 | gic_affinity_val = |
| 410 | gicd_irouter_val_from_mpidr(read_mpidr(), 0); |
| 411 | gicd_write_irouter(gicd_base, |
| 412 | irq_num, |
| 413 | gic_affinity_val); |
| 414 | |
| 415 | /* Enable this interrupt */ |
| 416 | gicd_set_isenabler(gicd_base, irq_num); |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | } |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 421 | #endif |
| 422 | |
| 423 | /******************************************************************************* |
| 424 | * Helper function to configure properties of secure SPIs |
| 425 | ******************************************************************************/ |
| 426 | unsigned int gicv3_secure_spis_configure_props(uintptr_t gicd_base, |
| 427 | const interrupt_prop_t *interrupt_props, |
| 428 | unsigned int interrupt_props_num) |
| 429 | { |
| 430 | unsigned int i; |
| 431 | const interrupt_prop_t *current_prop; |
| 432 | unsigned long long gic_affinity_val; |
| 433 | unsigned int ctlr_enable = 0; |
| 434 | |
| 435 | /* Make sure there's a valid property array */ |
| 436 | assert(interrupt_props != NULL); |
| 437 | assert(interrupt_props_num > 0); |
| 438 | |
| 439 | for (i = 0; i < interrupt_props_num; i++) { |
| 440 | current_prop = &interrupt_props[i]; |
| 441 | |
| 442 | if (current_prop->intr_num < MIN_SPI_ID) |
| 443 | continue; |
| 444 | |
| 445 | /* Configure this interrupt as a secure interrupt */ |
| 446 | gicd_clr_igroupr(gicd_base, current_prop->intr_num); |
| 447 | |
| 448 | /* Configure this interrupt as G0 or a G1S interrupt */ |
| 449 | assert((current_prop->intr_grp == INTR_GROUP0) || |
| 450 | (current_prop->intr_grp == INTR_GROUP1S)); |
| 451 | if (current_prop->intr_grp == INTR_GROUP1S) { |
| 452 | gicd_set_igrpmodr(gicd_base, current_prop->intr_num); |
| 453 | ctlr_enable |= CTLR_ENABLE_G1S_BIT; |
| 454 | } else { |
| 455 | gicd_clr_igrpmodr(gicd_base, current_prop->intr_num); |
| 456 | ctlr_enable |= CTLR_ENABLE_G0_BIT; |
| 457 | } |
| 458 | |
| 459 | /* Set interrupt configuration */ |
| 460 | gicd_set_icfgr(gicd_base, current_prop->intr_num, |
| 461 | current_prop->intr_cfg); |
| 462 | |
| 463 | /* Set the priority of this interrupt */ |
| 464 | gicd_set_ipriorityr(gicd_base, current_prop->intr_num, |
| 465 | current_prop->intr_pri); |
| 466 | |
| 467 | /* Target SPIs to the primary CPU */ |
| 468 | gic_affinity_val = gicd_irouter_val_from_mpidr(read_mpidr(), 0); |
| 469 | gicd_write_irouter(gicd_base, current_prop->intr_num, |
| 470 | gic_affinity_val); |
| 471 | |
| 472 | /* Enable this interrupt */ |
| 473 | gicd_set_isenabler(gicd_base, current_prop->intr_num); |
| 474 | } |
| 475 | |
| 476 | return ctlr_enable; |
| 477 | } |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 478 | |
| 479 | /******************************************************************************* |
| 480 | * Helper function to configure the default attributes of SPIs. |
| 481 | ******************************************************************************/ |
| 482 | void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base) |
| 483 | { |
| 484 | unsigned int index; |
| 485 | |
| 486 | /* |
| 487 | * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a |
| 488 | * more scalable approach as it avoids clearing the enable bits in the |
| 489 | * GICD_CTLR |
| 490 | */ |
| 491 | gicr_write_icenabler0(gicr_base, ~0); |
| 492 | gicr_wait_for_pending_write(gicr_base); |
| 493 | |
| 494 | /* Treat all SGIs/PPIs as G1NS by default. */ |
| 495 | gicr_write_igroupr0(gicr_base, ~0U); |
| 496 | |
| 497 | /* Setup the default PPI/SGI priorities doing four at a time */ |
| 498 | for (index = 0; index < MIN_SPI_ID; index += 4) |
| 499 | gicr_write_ipriorityr(gicr_base, |
| 500 | index, |
| 501 | GICD_IPRIORITYR_DEF_VAL); |
| 502 | |
| 503 | /* Configure all PPIs as level triggered by default */ |
| 504 | gicr_write_icfgr1(gicr_base, 0); |
| 505 | } |
| 506 | |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 507 | #if !ERROR_DEPRECATED |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 508 | /******************************************************************************* |
| 509 | * Helper function to configure secure G0 and G1S SPIs. |
| 510 | ******************************************************************************/ |
| 511 | void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, |
| 512 | unsigned int num_ints, |
| 513 | const unsigned int *sec_intr_list, |
| 514 | unsigned int int_grp) |
| 515 | { |
| 516 | unsigned int index, irq_num; |
| 517 | |
Soby Mathew | 03ffb6b | 2015-12-03 14:12:54 +0000 | [diff] [blame] | 518 | assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 519 | /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ |
| 520 | assert(num_ints ? (uintptr_t)sec_intr_list : 1); |
| 521 | |
| 522 | for (index = 0; index < num_ints; index++) { |
| 523 | irq_num = sec_intr_list[index]; |
| 524 | if (irq_num < MIN_SPI_ID) { |
| 525 | |
| 526 | /* Configure this interrupt as a secure interrupt */ |
| 527 | gicr_clr_igroupr0(gicr_base, irq_num); |
| 528 | |
| 529 | /* Configure this interrupt as G0 or a G1S interrupt */ |
Soby Mathew | 03ffb6b | 2015-12-03 14:12:54 +0000 | [diff] [blame] | 530 | if (int_grp == INTR_GROUP1S) |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 531 | gicr_set_igrpmodr0(gicr_base, irq_num); |
| 532 | else |
| 533 | gicr_clr_igrpmodr0(gicr_base, irq_num); |
| 534 | |
| 535 | /* Set the priority of this interrupt */ |
Soby Mathew | 38a7861 | 2016-01-15 14:20:57 +0000 | [diff] [blame] | 536 | gicr_set_ipriorityr(gicr_base, |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 537 | irq_num, |
| 538 | GIC_HIGHEST_SEC_PRIORITY); |
| 539 | |
| 540 | /* Enable this interrupt */ |
| 541 | gicr_set_isenabler0(gicr_base, irq_num); |
| 542 | } |
| 543 | } |
| 544 | } |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 545 | #endif |
| 546 | |
| 547 | /******************************************************************************* |
| 548 | * Helper function to configure properties of secure G0 and G1S PPIs and SGIs. |
| 549 | ******************************************************************************/ |
Jeenu Viswambharan | 385f1db | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 550 | unsigned int gicv3_secure_ppi_sgi_configure_props(uintptr_t gicr_base, |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 551 | const interrupt_prop_t *interrupt_props, |
| 552 | unsigned int interrupt_props_num) |
| 553 | { |
| 554 | unsigned int i; |
| 555 | const interrupt_prop_t *current_prop; |
Jeenu Viswambharan | 385f1db | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 556 | unsigned int ctlr_enable = 0; |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 557 | |
| 558 | /* Make sure there's a valid property array */ |
| 559 | assert(interrupt_props != NULL); |
| 560 | assert(interrupt_props_num > 0); |
| 561 | |
| 562 | for (i = 0; i < interrupt_props_num; i++) { |
| 563 | current_prop = &interrupt_props[i]; |
| 564 | |
| 565 | if (current_prop->intr_num >= MIN_SPI_ID) |
| 566 | continue; |
| 567 | |
| 568 | /* Configure this interrupt as a secure interrupt */ |
| 569 | gicr_clr_igroupr0(gicr_base, current_prop->intr_num); |
| 570 | |
| 571 | /* Configure this interrupt as G0 or a G1S interrupt */ |
| 572 | assert((current_prop->intr_grp == INTR_GROUP0) || |
| 573 | (current_prop->intr_grp == INTR_GROUP1S)); |
Jeenu Viswambharan | 385f1db | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 574 | if (current_prop->intr_grp == INTR_GROUP1S) { |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 575 | gicr_set_igrpmodr0(gicr_base, current_prop->intr_num); |
Jeenu Viswambharan | 385f1db | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 576 | ctlr_enable |= CTLR_ENABLE_G1S_BIT; |
| 577 | } else { |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 578 | gicr_clr_igrpmodr0(gicr_base, current_prop->intr_num); |
Jeenu Viswambharan | 385f1db | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 579 | ctlr_enable |= CTLR_ENABLE_G0_BIT; |
| 580 | } |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 581 | |
| 582 | /* Set the priority of this interrupt */ |
| 583 | gicr_set_ipriorityr(gicr_base, current_prop->intr_num, |
| 584 | current_prop->intr_pri); |
| 585 | |
| 586 | /* |
| 587 | * Set interrupt configuration for PPIs. Configuration for SGIs |
| 588 | * are ignored. |
| 589 | */ |
| 590 | if ((current_prop->intr_num >= MIN_PPI_ID) && |
| 591 | (current_prop->intr_num < MIN_SPI_ID)) { |
| 592 | gicr_set_icfgr1(gicr_base, current_prop->intr_num, |
| 593 | current_prop->intr_cfg); |
| 594 | } |
| 595 | |
| 596 | /* Enable this interrupt */ |
| 597 | gicr_set_isenabler0(gicr_base, current_prop->intr_num); |
| 598 | } |
Jeenu Viswambharan | 385f1db | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 599 | |
| 600 | return ctlr_enable; |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 601 | } |