Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Soby Mathew | 0c306cc | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | #ifndef __PLAT_ARM_H__ |
| 7 | #define __PLAT_ARM_H__ |
| 8 | |
Antonio Nino Diaz | 3b211ff | 2017-04-11 14:04:56 +0100 | [diff] [blame] | 9 | #include <arm_xlat_tables.h> |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 10 | #include <bakery_lock.h> |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 11 | #include <cassert.h> |
| 12 | #include <cpu_data.h> |
| 13 | #include <stdint.h> |
Summer Qin | 23411d2 | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 14 | #include <tzc_common.h> |
Scott Branden | 53d9c9c | 2017-04-10 11:45:52 -0700 | [diff] [blame] | 15 | #include <utils_def.h> |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 16 | |
Sandrine Bailleux | afc931f | 2016-09-15 10:09:53 +0100 | [diff] [blame] | 17 | /******************************************************************************* |
| 18 | * Forward declarations |
| 19 | ******************************************************************************/ |
| 20 | struct bl31_params; |
| 21 | struct meminfo; |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 22 | struct image_info; |
Soby Mathew | cab0b5b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 23 | struct bl_params; |
Sandrine Bailleux | afc931f | 2016-09-15 10:09:53 +0100 | [diff] [blame] | 24 | |
Summer Qin | 23411d2 | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 25 | typedef struct arm_tzc_regions_info { |
| 26 | unsigned long long base; |
| 27 | unsigned long long end; |
| 28 | tzc_region_attributes_t sec_attr; |
| 29 | unsigned int nsaid_permissions; |
| 30 | } arm_tzc_regions_info_t; |
| 31 | |
| 32 | /******************************************************************************* |
| 33 | * Default mapping definition of the TrustZone Controller for ARM standard |
| 34 | * platforms. |
| 35 | * Configure: |
| 36 | * - Region 0 with no access; |
| 37 | * - Region 1 with secure access only; |
| 38 | * - the remaining DRAM regions access from the given Non-Secure masters. |
| 39 | ******************************************************************************/ |
| 40 | #if ENABLE_SPM |
| 41 | #define ARM_TZC_REGIONS_DEF \ |
| 42 | {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ |
| 43 | TZC_REGION_S_RDWR, 0}, \ |
| 44 | {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ |
| 45 | PLAT_ARM_TZC_NS_DEV_ACCESS}, \ |
| 46 | {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ |
| 47 | PLAT_ARM_TZC_NS_DEV_ACCESS}, \ |
| 48 | {ARM_SP_IMAGE_NS_BUF_BASE, (ARM_SP_IMAGE_NS_BUF_BASE + \ |
| 49 | ARM_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ |
| 50 | PLAT_ARM_TZC_NS_DEV_ACCESS} |
| 51 | |
| 52 | #else |
| 53 | #define ARM_TZC_REGIONS_DEF \ |
| 54 | {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ |
| 55 | TZC_REGION_S_RDWR, 0}, \ |
| 56 | {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ |
| 57 | PLAT_ARM_TZC_NS_DEV_ACCESS}, \ |
| 58 | {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ |
| 59 | PLAT_ARM_TZC_NS_DEV_ACCESS} |
| 60 | #endif |
| 61 | |
Chris Kay | 053b4f9 | 2018-05-09 15:46:07 +0100 | [diff] [blame] | 62 | #define ARM_CASSERT_MMAP \ |
| 63 | CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ |
| 64 | assert_plat_arm_mmap_mismatch); \ |
| 65 | CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ |
| 66 | <= MAX_MMAP_REGIONS, \ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 67 | assert_max_mmap_regions); |
| 68 | |
| 69 | /* |
| 70 | * Utility functions common to ARM standard platforms |
| 71 | */ |
Soby Mathew | 4c0d039 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 72 | void arm_setup_page_tables(uintptr_t total_base, |
| 73 | size_t total_size, |
| 74 | uintptr_t code_start, |
| 75 | uintptr_t code_limit, |
| 76 | uintptr_t rodata_start, |
| 77 | uintptr_t rodata_limit |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 78 | #if USE_COHERENT_MEM |
Soby Mathew | 4c0d039 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 79 | , uintptr_t coh_start, |
| 80 | uintptr_t coh_limit |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 81 | #endif |
| 82 | ); |
| 83 | |
Soby Mathew | e40e075 | 2017-02-28 22:58:29 +0000 | [diff] [blame] | 84 | #if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 85 | /* |
| 86 | * Use this macro to instantiate lock before it is used in below |
| 87 | * arm_lock_xxx() macros |
| 88 | */ |
Sandrine Bailleux | 1931d1d | 2018-07-11 13:59:18 +0200 | [diff] [blame^] | 89 | #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) |
Soby Mathew | c04a3b6 | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 90 | #define ARM_LOCK_GET_INSTANCE (&arm_lock) |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 91 | /* |
| 92 | * These are wrapper macros to the Coherent Memory Bakery Lock API. |
| 93 | */ |
| 94 | #define arm_lock_init() bakery_lock_init(&arm_lock) |
| 95 | #define arm_lock_get() bakery_lock_get(&arm_lock) |
| 96 | #define arm_lock_release() bakery_lock_release(&arm_lock) |
| 97 | |
| 98 | #else |
| 99 | |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 100 | /* |
Yatharth Kochar | 6f24934 | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 101 | * Empty macros for all other BL stages other than BL31 and BL32 |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 102 | */ |
Jeenu Viswambharan | 1958316 | 2017-08-23 14:12:59 +0100 | [diff] [blame] | 103 | #define ARM_INSTANTIATE_LOCK static int arm_lock __unused |
Soby Mathew | c04a3b6 | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 104 | #define ARM_LOCK_GET_INSTANCE 0 |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 105 | #define arm_lock_init() |
| 106 | #define arm_lock_get() |
| 107 | #define arm_lock_release() |
| 108 | |
Soby Mathew | e40e075 | 2017-02-28 22:58:29 +0000 | [diff] [blame] | 109 | #endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 110 | |
Soby Mathew | 2204afd | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 111 | #if ARM_RECOM_STATE_ID_ENC |
| 112 | /* |
| 113 | * Macros used to parse state information from State-ID if it is using the |
| 114 | * recommended encoding for State-ID. |
| 115 | */ |
| 116 | #define ARM_LOCAL_PSTATE_WIDTH 4 |
| 117 | #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) |
| 118 | |
| 119 | /* Macros to construct the composite power state */ |
| 120 | |
| 121 | /* Make composite power state parameter till power level 0 */ |
| 122 | #if PSCI_EXTENDED_STATE_ID |
| 123 | |
| 124 | #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ |
| 125 | (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) |
| 126 | #else |
| 127 | #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ |
| 128 | (((lvl0_state) << PSTATE_ID_SHIFT) | \ |
| 129 | ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ |
| 130 | ((type) << PSTATE_TYPE_SHIFT)) |
| 131 | #endif /* __PSCI_EXTENDED_STATE_ID__ */ |
| 132 | |
| 133 | /* Make composite power state parameter till power level 1 */ |
| 134 | #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ |
| 135 | (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ |
| 136 | arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) |
| 137 | |
Soby Mathew | 5f3a603 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 138 | /* Make composite power state parameter till power level 2 */ |
| 139 | #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ |
| 140 | (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ |
| 141 | arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) |
| 142 | |
Soby Mathew | 2204afd | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 143 | #endif /* __ARM_RECOM_STATE_ID_ENC__ */ |
| 144 | |
Jeenu Viswambharan | b10d449 | 2017-02-16 14:55:15 +0000 | [diff] [blame] | 145 | /* ARM State switch error codes */ |
| 146 | #define STATE_SW_E_PARAM (-2) |
| 147 | #define STATE_SW_E_DENIED (-3) |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 148 | |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 149 | /* IO storage utility functions */ |
| 150 | void arm_io_setup(void); |
| 151 | |
| 152 | /* Security utility functions */ |
Summer Qin | 23411d2 | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 153 | void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions); |
Vikram Kanigiri | 618f0fe | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 154 | struct tzc_dmc500_driver_data; |
Summer Qin | 23411d2 | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 155 | void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, |
| 156 | const arm_tzc_regions_info_t *tzc_regions); |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 157 | |
Antonio Nino Diaz | 88a0523 | 2018-06-19 09:29:36 +0100 | [diff] [blame] | 158 | /* Console utility functions */ |
| 159 | void arm_console_boot_init(void); |
| 160 | void arm_console_boot_end(void); |
| 161 | void arm_console_runtime_init(void); |
| 162 | void arm_console_runtime_end(void); |
| 163 | |
Soby Mathew | c1bb8a0 | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 164 | /* Systimer utility function */ |
| 165 | void arm_configure_sys_timer(void); |
| 166 | |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 167 | /* PM utility functions */ |
Soby Mathew | 38dce70 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 168 | int arm_validate_power_state(unsigned int power_state, |
| 169 | psci_power_state_t *req_state); |
Jeenu Viswambharan | 71e7a4e | 2017-09-19 09:27:18 +0100 | [diff] [blame] | 170 | int arm_validate_psci_entrypoint(uintptr_t entrypoint); |
Soby Mathew | f9e858b | 2015-07-15 13:36:24 +0100 | [diff] [blame] | 171 | int arm_validate_ns_entrypoint(uintptr_t entrypoint); |
Soby Mathew | e35a3fb | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 172 | void arm_system_pwr_domain_save(void); |
Soby Mathew | c1bb8a0 | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 173 | void arm_system_pwr_domain_resume(void); |
Sandrine Bailleux | 4c117f6 | 2015-11-26 16:31:34 +0000 | [diff] [blame] | 174 | void arm_program_trusted_mailbox(uintptr_t address); |
Roberto Vargas | dc6aad2 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 175 | int arm_psci_read_mem_protect(int *enabled); |
Roberto Vargas | f145403 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 176 | int arm_nor_psci_write_mem_protect(int val); |
Roberto Vargas | 638b034 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 177 | void arm_nor_psci_do_static_mem_protect(void); |
| 178 | void arm_nor_psci_do_dyn_mem_protect(void); |
Roberto Vargas | f145403 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 179 | int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); |
Soby Mathew | 38dce70 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 180 | |
| 181 | /* Topology utility function */ |
| 182 | int arm_check_mpidr(u_register_t mpidr); |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 183 | |
| 184 | /* BL1 utility functions */ |
| 185 | void arm_bl1_early_platform_setup(void); |
| 186 | void arm_bl1_platform_setup(void); |
| 187 | void arm_bl1_plat_arch_setup(void); |
| 188 | |
| 189 | /* BL2 utility functions */ |
Soby Mathew | cab0b5b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 190 | void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout); |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 191 | void arm_bl2_platform_setup(void); |
| 192 | void arm_bl2_plat_arch_setup(void); |
| 193 | uint32_t arm_get_spsr_for_bl32_entry(void); |
| 194 | uint32_t arm_get_spsr_for_bl33_entry(void); |
Yatharth Kochar | 07570d5 | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 195 | int arm_bl2_handle_post_image_load(unsigned int image_id); |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 196 | |
Roberto Vargas | 81528db | 2017-11-17 13:22:18 +0000 | [diff] [blame] | 197 | /* BL2 at EL3 functions */ |
| 198 | void arm_bl2_el3_early_platform_setup(void); |
| 199 | void arm_bl2_el3_plat_arch_setup(void); |
| 200 | |
Yatharth Kochar | dcda29f | 2015-10-14 15:28:11 +0100 | [diff] [blame] | 201 | /* BL2U utility functions */ |
| 202 | void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, |
| 203 | void *plat_info); |
| 204 | void arm_bl2u_platform_setup(void); |
| 205 | void arm_bl2u_plat_arch_setup(void); |
| 206 | |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 207 | /* BL31 utility functions */ |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 208 | #if LOAD_IMAGE_V2 |
Soby Mathew | 0c306cc | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 209 | void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, |
| 210 | uintptr_t hw_config, void *plat_params_from_bl2); |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 211 | #else |
Soby Mathew | 0c306cc | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 212 | void arm_bl31_early_platform_setup(struct bl31_params *from_bl2, uintptr_t soc_fw_config, |
| 213 | uintptr_t hw_config, void *plat_params_from_bl2); |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 214 | #endif /* LOAD_IMAGE_V2 */ |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 215 | void arm_bl31_platform_setup(void); |
Soby Mathew | 080225d | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 216 | void arm_bl31_plat_runtime_setup(void); |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 217 | void arm_bl31_plat_arch_setup(void); |
| 218 | |
| 219 | /* TSP utility functions */ |
| 220 | void arm_tsp_early_platform_setup(void); |
| 221 | |
Soby Mathew | 181bbd4 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 222 | /* SP_MIN utility functions */ |
Soby Mathew | 0c306cc | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 223 | void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, |
| 224 | uintptr_t hw_config, void *plat_params_from_bl2); |
Dimitris Papastamos | 2156830 | 2017-06-07 13:45:41 +0100 | [diff] [blame] | 225 | void arm_sp_min_plat_runtime_setup(void); |
Soby Mathew | 181bbd4 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 226 | |
Yatharth Kochar | 436223d | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 227 | /* FIP TOC validity check */ |
| 228 | int arm_io_is_toc_valid(void); |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 229 | |
Soby Mathew | c228956 | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 230 | /* Utility functions for Dynamic Config */ |
| 231 | void arm_load_tb_fw_config(void); |
Soby Mathew | cab0b5b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 232 | void arm_bl2_set_tb_cfg_addr(void *dtb); |
| 233 | void arm_bl2_dyn_cfg_init(void); |
Soby Mathew | c228956 | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 234 | |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 235 | /* |
| 236 | * Mandatory functions required in ARM standard platforms |
| 237 | */ |
Soby Mathew | 0108047 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 238 | unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 239 | void plat_arm_gic_driver_init(void); |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 240 | void plat_arm_gic_init(void); |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 241 | void plat_arm_gic_cpuif_enable(void); |
| 242 | void plat_arm_gic_cpuif_disable(void); |
Jeenu Viswambharan | d17b953 | 2016-12-09 11:12:34 +0000 | [diff] [blame] | 243 | void plat_arm_gic_redistif_on(void); |
| 244 | void plat_arm_gic_redistif_off(void); |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 245 | void plat_arm_gic_pcpu_init(void); |
Soby Mathew | e35a3fb | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 246 | void plat_arm_gic_save(void); |
| 247 | void plat_arm_gic_resume(void); |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 248 | void plat_arm_security_setup(void); |
| 249 | void plat_arm_pwrc_setup(void); |
Vikram Kanigiri | 6355f23 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 250 | void plat_arm_interconnect_init(void); |
| 251 | void plat_arm_interconnect_enter_coherency(void); |
| 252 | void plat_arm_interconnect_exit_coherency(void); |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 253 | |
Summer Qin | d8d6cf2 | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 254 | #if ARM_PLAT_MT |
| 255 | unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); |
| 256 | #endif |
| 257 | |
Yatharth Kochar | a8aa7fe | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 258 | #if LOAD_IMAGE_V2 |
| 259 | /* |
| 260 | * This function is called after loading SCP_BL2 image and it is used to perform |
| 261 | * any platform-specific actions required to handle the SCP firmware. |
| 262 | */ |
| 263 | int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); |
| 264 | #endif |
| 265 | |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 266 | /* |
| 267 | * Optional functions required in ARM standard platforms |
| 268 | */ |
| 269 | void plat_arm_io_setup(void); |
| 270 | int plat_arm_get_alt_image_source( |
Juan Castillo | 16948ae | 2015-04-13 17:36:19 +0100 | [diff] [blame] | 271 | unsigned int image_id, |
| 272 | uintptr_t *dev_handle, |
| 273 | uintptr_t *image_spec); |
Soby Mathew | 38dce70 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 274 | unsigned int plat_arm_calc_core_pos(u_register_t mpidr); |
Vikram Kanigiri | 65cb1c4 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 275 | const mmap_region_t *plat_arm_get_mmap(void); |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 276 | |
Soby Mathew | 5486a96 | 2016-10-21 17:51:22 +0100 | [diff] [blame] | 277 | /* Allow platform to override psci_pm_ops during runtime */ |
| 278 | const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); |
| 279 | |
Jeenu Viswambharan | b10d449 | 2017-02-16 14:55:15 +0000 | [diff] [blame] | 280 | /* Execution state switch in ARM platforms */ |
| 281 | int arm_execution_state_switch(unsigned int smc_fid, |
| 282 | uint32_t pc_hi, |
| 283 | uint32_t pc_lo, |
| 284 | uint32_t cookie_hi, |
| 285 | uint32_t cookie_lo, |
| 286 | void *handle); |
| 287 | |
Soby Mathew | 0ed8c00 | 2018-03-01 10:53:33 +0000 | [diff] [blame] | 288 | /* Optional functions for SP_MIN */ |
| 289 | void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, |
| 290 | u_register_t arg2, u_register_t arg3); |
| 291 | |
Roberto Vargas | 1af540e | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 292 | /* global variables */ |
| 293 | extern plat_psci_ops_t plat_arm_psci_pm_ops; |
| 294 | extern const mmap_region_t plat_arm_mmap[]; |
| 295 | |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 296 | #endif /* __PLAT_ARM_H__ */ |