Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PLATFORM_DEF_H__ |
| 32 | #define __PLATFORM_DEF_H__ |
| 33 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 34 | #include <arm_def.h> |
| 35 | #include <board_arm_def.h> |
| 36 | #include <board_css_def.h> |
| 37 | #include <common_def.h> |
| 38 | #include <css_def.h> |
| 39 | #include <soc_css_def.h> |
| 40 | #include <tzc400.h> |
| 41 | #include <v2m_def.h> |
Sandrine Bailleux | edfda10 | 2014-07-17 09:56:29 +0100 | [diff] [blame] | 42 | #include "../juno_def.h" |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 43 | |
Soby Mathew | 5f3a603 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 44 | /* Juno supports system power domain */ |
| 45 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
| 46 | #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ |
| 47 | ARM_CLUSTER_COUNT + \ |
| 48 | PLATFORM_CORE_COUNT) |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 49 | /* |
Soby Mathew | 5f3a603 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 50 | * Other platform porting definitions are provided by included headers |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 51 | */ |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 52 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 53 | /* |
| 54 | * Required ARM standard platform porting definitions |
| 55 | */ |
| 56 | #define PLAT_ARM_CLUSTER0_CORE_COUNT 2 |
| 57 | #define PLAT_ARM_CLUSTER1_CORE_COUNT 4 |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 58 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 59 | /* Use the bypass address */ |
| 60 | #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 61 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 62 | /* |
| 63 | * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB |
| 64 | * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of |
| 65 | * flash |
| 66 | */ |
Juan Castillo | 01df3c1 | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 67 | #if TRUSTED_BOARD_BOOT |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 68 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 |
| 69 | #else |
| 70 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 |
Juan Castillo | 01df3c1 | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 71 | #endif /* TRUSTED_BOARD_BOOT */ |
| 72 | |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 73 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 74 | /* CCI related constants */ |
| 75 | #define PLAT_ARM_CCI_BASE 0x2c090000 |
| 76 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 77 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 |
| 78 | |
| 79 | /* TZC related constants */ |
| 80 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 81 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ |
| 82 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ |
| 83 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ |
| 84 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ |
| 85 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ |
| 86 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ |
| 87 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ |
| 88 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ |
| 89 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ |
| 90 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) |
Juan Castillo | 1217d28 | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 91 | |
| 92 | /* |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 93 | * Required ARM CSS based platform porting definitions |
Juan Castillo | 1217d28 | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 94 | */ |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 95 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 96 | /* GIC related constants (no GICR in GIC-400) */ |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame^] | 97 | #define PLAT_ARM_GICD_BASE 0x2c010000 |
| 98 | #define PLAT_ARM_GICC_BASE 0x2c02f000 |
| 99 | #define PLAT_ARM_GICH_BASE 0x2c04f000 |
| 100 | #define PLAT_ARM_GICV_BASE 0x2c06f000 |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 101 | |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame^] | 102 | /* |
| 103 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 104 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 105 | * as Group 0 interrupts. |
| 106 | */ |
| 107 | #define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ |
| 108 | ARM_G1S_IRQS, \ |
Vikram Kanigiri | a7270d3 | 2015-06-24 17:51:09 +0100 | [diff] [blame] | 109 | JUNO_IRQ_DMA_SMMU, \ |
| 110 | JUNO_IRQ_HDLCD0_SMMU, \ |
| 111 | JUNO_IRQ_HDLCD1_SMMU, \ |
| 112 | JUNO_IRQ_USB_SMMU, \ |
| 113 | JUNO_IRQ_THIN_LINKS_SMMU, \ |
| 114 | JUNO_IRQ_SEC_I2C, \ |
| 115 | JUNO_IRQ_GPU_SMMU_1, \ |
| 116 | JUNO_IRQ_ETR_SMMU |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 117 | |
Achin Gupta | 27573c5 | 2015-11-03 14:18:34 +0000 | [diff] [blame^] | 118 | #define PLAT_ARM_G0_IRQS ARM_G0_IRQS |
| 119 | |
Juan Castillo | 1217d28 | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 120 | /* |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 121 | * Required ARM CSS SoC based platform porting definitions |
Juan Castillo | 1217d28 | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 122 | */ |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 123 | |
Dan Handley | f8b0b22 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 124 | /* CSS SoC NIC-400 Global Programmers View (GPV) */ |
| 125 | #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 126 | |
Soby Mathew | 8c5fe0b | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 127 | |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 128 | #endif /* __PLATFORM_DEF_H__ */ |