Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | 1b70db0 | 2015-03-23 18:13:33 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | #include <assert.h> |
| 9 | #include <debug.h> |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 10 | #include <platform.h> |
Dan Handley | 5f0cdb0 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 11 | #include <platform_def.h> |
Dan Handley | da0af78 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 12 | #include <tsp.h> |
| 13 | #include "tsp_private.h" |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
Soby Mathew | 0244613 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 16 | * This function updates the TSP statistics for S-EL1 interrupts handled |
| 17 | * synchronously i.e the ones that have been handed over by the TSPD. It also |
| 18 | * keeps count of the number of times control was passed back to the TSPD |
| 19 | * after handling the interrupt. In the future it will be possible that the |
| 20 | * TSPD hands over an S-EL1 interrupt to the TSP but does not expect it to |
| 21 | * return execution. This statistic will be useful to distinguish between these |
| 22 | * two models of synchronous S-EL1 interrupt handling. The 'elr_el3' parameter |
| 23 | * contains the address of the instruction in normal world where this S-EL1 |
| 24 | * interrupt was generated. |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 25 | ******************************************************************************/ |
Soby Mathew | 0244613 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 26 | void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3) |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 27 | { |
Soby Mathew | fd650ff | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 28 | uint32_t linear_id = plat_my_core_pos(); |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 29 | |
Soby Mathew | 0244613 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 30 | tsp_stats[linear_id].sync_sel1_intr_count++; |
| 31 | if (type == TSP_HANDLE_SEL1_INTR_AND_RETURN) |
| 32 | tsp_stats[linear_id].sync_sel1_intr_ret_count++; |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 33 | |
Dan Handley | 6ad2e46 | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 34 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 35 | spin_lock(&console_lock); |
Soby Mathew | 0244613 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 36 | VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%lx\n", |
Soby Mathew | fd650ff | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 37 | read_mpidr(), elr_el3); |
Soby Mathew | 0244613 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 38 | VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests," |
| 39 | " %d sync s-el1 interrupt returns\n", |
Soby Mathew | fd650ff | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 40 | read_mpidr(), |
Soby Mathew | 0244613 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 41 | tsp_stats[linear_id].sync_sel1_intr_count, |
| 42 | tsp_stats[linear_id].sync_sel1_intr_ret_count); |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 43 | spin_unlock(&console_lock); |
Dan Handley | 6ad2e46 | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 44 | #endif |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 45 | } |
| 46 | |
Soby Mathew | 404dba5 | 2015-09-22 12:01:18 +0100 | [diff] [blame] | 47 | /****************************************************************************** |
| 48 | * This function is invoked when a non S-EL1 interrupt is received and causes |
| 49 | * the preemption of TSP. This function returns TSP_PREEMPTED and results |
| 50 | * in the control being handed over to EL3 for handling the interrupt. |
| 51 | *****************************************************************************/ |
| 52 | int32_t tsp_handle_preemption(void) |
| 53 | { |
| 54 | uint32_t linear_id = plat_my_core_pos(); |
| 55 | |
| 56 | tsp_stats[linear_id].preempt_intr_count++; |
| 57 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
| 58 | spin_lock(&console_lock); |
| 59 | VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n", |
| 60 | read_mpidr(), tsp_stats[linear_id].preempt_intr_count); |
| 61 | spin_unlock(&console_lock); |
| 62 | #endif |
| 63 | return TSP_PREEMPTED; |
| 64 | } |
| 65 | |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 66 | /******************************************************************************* |
Soby Mathew | 0244613 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 67 | * TSP interrupt handler is called as a part of both synchronous and |
| 68 | * asynchronous handling of TSP interrupts. Currently the physical timer |
| 69 | * interrupt is the only S-EL1 interrupt that this handler expects. It returns |
| 70 | * 0 upon successfully handling the expected interrupt and all other |
| 71 | * interrupts are treated as normal world or EL3 interrupts. |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 72 | ******************************************************************************/ |
Soby Mathew | 0244613 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 73 | int32_t tsp_common_int_handler(void) |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 74 | { |
Soby Mathew | fd650ff | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 75 | uint32_t linear_id = plat_my_core_pos(), id; |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * Get the highest priority pending interrupt id and see if it is the |
| 79 | * secure physical generic timer interrupt in which case, handle it. |
| 80 | * Otherwise throw this interrupt at the EL3 firmware. |
Soby Mathew | 404dba5 | 2015-09-22 12:01:18 +0100 | [diff] [blame] | 81 | * |
| 82 | * There is a small time window between reading the highest priority |
| 83 | * pending interrupt and acknowledging it during which another |
| 84 | * interrupt of higher priority could become the highest pending |
| 85 | * interrupt. This is not expected to happen currently for TSP. |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 86 | */ |
Dan Handley | 9865ac1 | 2014-05-27 16:17:21 +0100 | [diff] [blame] | 87 | id = plat_ic_get_pending_interrupt_id(); |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 88 | |
| 89 | /* TSP can only handle the secure physical timer interrupt */ |
Dan Handley | 5a06bb7 | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 90 | if (id != TSP_IRQ_SEC_PHY_TIMER) |
Soby Mathew | 404dba5 | 2015-09-22 12:01:18 +0100 | [diff] [blame] | 91 | return tsp_handle_preemption(); |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 92 | |
| 93 | /* |
Soby Mathew | 404dba5 | 2015-09-22 12:01:18 +0100 | [diff] [blame] | 94 | * Acknowledge and handle the secure timer interrupt. Also sanity check |
| 95 | * if it has been preempted by another interrupt through an assertion. |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 96 | */ |
Dan Handley | 9865ac1 | 2014-05-27 16:17:21 +0100 | [diff] [blame] | 97 | id = plat_ic_acknowledge_interrupt(); |
Dan Handley | 5a06bb7 | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 98 | assert(id == TSP_IRQ_SEC_PHY_TIMER); |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 99 | tsp_generic_timer_handler(); |
Dan Handley | 9865ac1 | 2014-05-27 16:17:21 +0100 | [diff] [blame] | 100 | plat_ic_end_of_interrupt(id); |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 101 | |
| 102 | /* Update the statistics and print some messages */ |
Soby Mathew | 0244613 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 103 | tsp_stats[linear_id].sel1_intr_count++; |
Dan Handley | 6ad2e46 | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 104 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 105 | spin_lock(&console_lock); |
Soby Mathew | 0244613 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 106 | VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n", |
Soby Mathew | fd650ff | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 107 | read_mpidr(), id); |
Soby Mathew | 0244613 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 108 | VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n", |
| 109 | read_mpidr(), tsp_stats[linear_id].sel1_intr_count); |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 110 | spin_unlock(&console_lock); |
Dan Handley | 6ad2e46 | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 111 | #endif |
Achin Gupta | 6cf8902 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 112 | return 0; |
| 113 | } |