Konstantin Porotchkin | 0ade8cd | 2018-04-24 19:23:09 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | /* Driver for COMPHY unit that is part or Marvell A8K SoCs */ |
| 9 | |
Antonio Nino Diaz | c3cf06f | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 10 | #ifndef COMPHY_H |
| 11 | #define COMPHY_H |
Konstantin Porotchkin | 0ade8cd | 2018-04-24 19:23:09 +0300 | [diff] [blame] | 12 | |
| 13 | /* COMPHY registers */ |
| 14 | #define COMMON_PHY_CFG1_REG 0x0 |
| 15 | #define COMMON_PHY_CFG1_PWR_UP_OFFSET 1 |
| 16 | #define COMMON_PHY_CFG1_PWR_UP_MASK \ |
| 17 | (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) |
| 18 | #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2 |
| 19 | #define COMMON_PHY_CFG1_PIPE_SELECT_MASK \ |
| 20 | (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) |
| 21 | #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13 |
| 22 | #define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \ |
| 23 | (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) |
| 24 | #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14 |
| 25 | #define COMMON_PHY_CFG1_CORE_RSTN_MASK \ |
| 26 | (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) |
| 27 | #define COMMON_PHY_PHY_MODE_OFFSET 15 |
| 28 | #define COMMON_PHY_PHY_MODE_MASK \ |
| 29 | (0x1 << COMMON_PHY_PHY_MODE_OFFSET) |
| 30 | |
| 31 | #define COMMON_SELECTOR_PHY_OFFSET 0x140 |
| 32 | #define COMMON_SELECTOR_PIPE_OFFSET 0x144 |
| 33 | |
| 34 | #define COMMON_PHY_SD_CTRL1 0x148 |
| 35 | #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0 |
| 36 | #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF |
| 37 | #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 |
| 38 | #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \ |
| 39 | (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) |
| 40 | #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 |
| 41 | #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \ |
| 42 | (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) |
| 43 | |
| 44 | #define DFX_DEV_GEN_CTRL12 0x80 |
| 45 | #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7 |
| 46 | #define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \ |
| 47 | (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) |
| 48 | |
| 49 | /* HPIPE register */ |
| 50 | #define HPIPE_PWR_PLL_REG 0x4 |
| 51 | #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 |
| 52 | #define HPIPE_PWR_PLL_REF_FREQ_MASK \ |
| 53 | (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) |
| 54 | #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 |
| 55 | #define HPIPE_PWR_PLL_PHY_MODE_MASK \ |
| 56 | (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) |
| 57 | |
| 58 | #define HPIPE_DFE_REG0 0x01C |
| 59 | #define HPIPE_DFE_RES_FORCE_OFFSET 15 |
| 60 | #define HPIPE_DFE_RES_FORCE_MASK \ |
| 61 | (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) |
| 62 | |
| 63 | #define HPIPE_G2_SET_1_REG 0x040 |
| 64 | #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 |
| 65 | #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ |
| 66 | (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) |
| 67 | #define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 |
| 68 | #define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ |
| 69 | (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) |
| 70 | #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 |
| 71 | #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ |
| 72 | (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) |
| 73 | |
| 74 | #define HPIPE_G3_SETTINGS_1_REG 0x048 |
| 75 | #define HPIPE_G3_RX_SELMUPI_OFFSET 0 |
| 76 | #define HPIPE_G3_RX_SELMUPI_MASK \ |
| 77 | (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET) |
| 78 | #define HPIPE_G3_RX_SELMUPF_OFFSET 3 |
| 79 | #define HPIPE_G3_RX_SELMUPF_MASK \ |
| 80 | (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET) |
| 81 | #define HPIPE_G3_SETTING_BIT_OFFSET 13 |
| 82 | #define HPIPE_G3_SETTING_BIT_MASK \ |
| 83 | (0x1 << HPIPE_G3_SETTING_BIT_OFFSET) |
| 84 | |
| 85 | #define HPIPE_INTERFACE_REG 0x94 |
| 86 | #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 |
| 87 | #define HPIPE_INTERFACE_GEN_MAX_MASK \ |
| 88 | (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) |
| 89 | #define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 |
| 90 | #define HPIPE_INTERFACE_DET_BYPASS_MASK \ |
| 91 | (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) |
| 92 | #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 |
| 93 | #define HPIPE_INTERFACE_LINK_TRAIN_MASK \ |
| 94 | (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) |
| 95 | |
| 96 | #define HPIPE_VDD_CAL_CTRL_REG 0x114 |
| 97 | #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 |
| 98 | #define HPIPE_EXT_SELLV_RXSAMPL_MASK \ |
| 99 | (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) |
| 100 | |
| 101 | #define HPIPE_PCIE_REG0 0x120 |
| 102 | #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 |
| 103 | #define HPIPE_PCIE_IDLE_SYNC_MASK \ |
| 104 | (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) |
| 105 | #define HPIPE_PCIE_SEL_BITS_OFFSET 13 |
| 106 | #define HPIPE_PCIE_SEL_BITS_MASK \ |
| 107 | (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) |
| 108 | |
| 109 | #define HPIPE_LANE_ALIGN_REG 0x124 |
| 110 | #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 |
| 111 | #define HPIPE_LANE_ALIGN_OFF_MASK \ |
| 112 | (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) |
| 113 | |
| 114 | #define HPIPE_MISC_REG 0x13C |
| 115 | #define HPIPE_MISC_CLK100M_125M_OFFSET 4 |
| 116 | #define HPIPE_MISC_CLK100M_125M_MASK \ |
| 117 | (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) |
| 118 | #define HPIPE_MISC_ICP_FORCE_OFFSET 5 |
| 119 | #define HPIPE_MISC_ICP_FORCE_MASK \ |
| 120 | (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) |
| 121 | #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 |
| 122 | #define HPIPE_MISC_TXDCLK_2X_MASK \ |
| 123 | (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) |
| 124 | #define HPIPE_MISC_CLK500_EN_OFFSET 7 |
| 125 | #define HPIPE_MISC_CLK500_EN_MASK \ |
| 126 | (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) |
| 127 | #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 |
| 128 | #define HPIPE_MISC_REFCLK_SEL_MASK \ |
| 129 | (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) |
| 130 | |
| 131 | #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C |
| 132 | #define HPIPE_SMAPLER_OFFSET 12 |
| 133 | #define HPIPE_SMAPLER_MASK (0x1 << HPIPE_SMAPLER_OFFSET) |
| 134 | |
| 135 | #define HPIPE_PWR_CTR_DTL_REG 0x184 |
| 136 | #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 |
| 137 | #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ |
| 138 | (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) |
| 139 | |
| 140 | #define HPIPE_FRAME_DET_CONTROL_REG 0x220 |
| 141 | #define HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET 12 |
| 142 | #define HPIPE_FRAME_DET_LOCK_LOST_TO_MASK \ |
| 143 | (0x1 << HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET) |
| 144 | |
| 145 | #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 |
| 146 | #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 |
| 147 | #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ |
| 148 | (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) |
| 149 | |
| 150 | #define HPIPE_TX_TRAIN_CTRL_REG 0x26C |
| 151 | #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 |
| 152 | #define HPIPE_TX_TRAIN_CTRL_G1_MASK \ |
| 153 | (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) |
| 154 | #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 |
| 155 | #define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ |
| 156 | (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) |
| 157 | #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 |
| 158 | #define HPIPE_TX_TRAIN_CTRL_G0_MASK \ |
| 159 | (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) |
| 160 | |
| 161 | #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 |
| 162 | #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 |
| 163 | #define HPIPE_TRX_TRAIN_TIMER_MASK \ |
| 164 | (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) |
| 165 | |
| 166 | #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 |
| 167 | #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 |
| 168 | #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ |
| 169 | (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) |
| 170 | #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 |
| 171 | #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ |
| 172 | (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) |
| 173 | #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 |
| 174 | #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ |
| 175 | (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) |
| 176 | #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 |
| 177 | #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ |
| 178 | (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) |
| 179 | |
| 180 | #define HPIPE_TX_TRAIN_REG 0x31C |
| 181 | #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 |
| 182 | #define HPIPE_TX_TRAIN_CHK_INIT_MASK \ |
| 183 | (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) |
| 184 | #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 |
| 185 | #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ |
| 186 | (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) |
| 187 | |
| 188 | #define HPIPE_CDR_CONTROL_REG 0x418 |
| 189 | #define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14 |
| 190 | #define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \ |
| 191 | (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET) |
| 192 | #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 |
| 193 | #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ |
| 194 | (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) |
| 195 | #define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 |
| 196 | #define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \ |
| 197 | (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) |
| 198 | #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 |
| 199 | #define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \ |
| 200 | (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) |
| 201 | |
| 202 | #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 |
| 203 | #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 |
| 204 | #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ |
| 205 | (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) |
| 206 | #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 |
| 207 | #define HPIPE_TX_NUM_OF_PRESET_MASK \ |
| 208 | (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) |
| 209 | #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 |
| 210 | #define HPIPE_TX_SWEEP_PRESET_EN_MASK \ |
| 211 | (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) |
| 212 | #define HPIPE_G2_SETTINGS_4_REG 0x44C |
| 213 | #define HPIPE_G2_DFE_RES_OFFSET 8 |
| 214 | #define HPIPE_G2_DFE_RES_MASK (0x3 << HPIPE_G2_DFE_RES_OFFSET) |
| 215 | |
| 216 | #define HPIPE_G3_SETTING_3_REG 0x450 |
| 217 | #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 |
| 218 | #define HPIPE_G3_FFE_CAP_SEL_MASK \ |
| 219 | (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) |
| 220 | #define HPIPE_G3_FFE_RES_SEL_OFFSET 4 |
| 221 | #define HPIPE_G3_FFE_RES_SEL_MASK \ |
| 222 | (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) |
| 223 | #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 |
| 224 | #define HPIPE_G3_FFE_SETTING_FORCE_MASK \ |
| 225 | (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) |
| 226 | #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 |
| 227 | #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ |
| 228 | (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) |
| 229 | #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 |
| 230 | #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ |
| 231 | (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) |
| 232 | |
| 233 | #define HPIPE_G3_SETTING_4_REG 0x454 |
| 234 | #define HPIPE_G3_DFE_RES_OFFSET 8 |
| 235 | #define HPIPE_G3_DFE_RES_MASK (0x3 << HPIPE_G3_DFE_RES_OFFSET) |
| 236 | |
| 237 | #define HPIPE_DFE_CONTROL_REG 0x470 |
| 238 | #define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 |
| 239 | #define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \ |
| 240 | (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) |
| 241 | |
| 242 | #define HPIPE_DFE_CTRL_28_REG 0x49C |
| 243 | #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 |
| 244 | #define HPIPE_DFE_CTRL_28_PIPE4_MASK \ |
| 245 | (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) |
| 246 | |
| 247 | #define HPIPE_G3_SETTING_5_REG 0x548 |
| 248 | #define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0 |
| 249 | #define HPIPE_G3_SETTING_5_G3_ICP_MASK \ |
| 250 | (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) |
| 251 | |
| 252 | #define HPIPE_LANE_STATUS1_REG 0x60C |
| 253 | #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 |
| 254 | #define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ |
| 255 | (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) |
| 256 | |
| 257 | #define HPIPE_LANE_CFG4_REG 0x620 |
| 258 | #define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 |
| 259 | #define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \ |
| 260 | (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) |
| 261 | |
| 262 | #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C |
| 263 | #define HPIPE_CFG_EQ_FS_OFFSET 0 |
| 264 | #define HPIPE_CFG_EQ_FS_MASK (0x3f << HPIPE_CFG_EQ_FS_OFFSET) |
| 265 | #define HPIPE_CFG_EQ_LF_OFFSET 6 |
| 266 | #define HPIPE_CFG_EQ_LF_MASK (0x3f << HPIPE_CFG_EQ_LF_OFFSET) |
| 267 | #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 |
| 268 | #define HPIPE_CFG_PHY_RC_EP_MASK \ |
| 269 | (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) |
| 270 | |
| 271 | #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 |
| 272 | #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 |
| 273 | #define HPIPE_CFG_UPDATE_POLARITY_MASK \ |
| 274 | (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) |
| 275 | |
| 276 | #define HPIPE_LANE_EQ_CFG2_REG 0x6a4 |
| 277 | #define HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET 14 |
| 278 | #define HPIPE_CFG_EQ_BUNDLE_DIS_MASK \ |
| 279 | (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET) |
| 280 | |
| 281 | #define HPIPE_LANE_PRESET_CFG0_REG 0x6a8 |
| 282 | #define HPIPE_CFG_CURSOR_PRESET0_OFFSET 0 |
| 283 | #define HPIPE_CFG_CURSOR_PRESET0_MASK \ |
| 284 | (0x3f << HPIPE_CFG_CURSOR_PRESET0_OFFSET) |
| 285 | #define HPIPE_CFG_CURSOR_PRESET1_OFFSET 6 |
| 286 | #define HPIPE_CFG_CURSOR_PRESET1_MASK \ |
| 287 | (0x3f << HPIPE_CFG_CURSOR_PRESET1_OFFSET) |
| 288 | |
| 289 | #define HPIPE_LANE_PRESET_CFG1_REG 0x6ac |
| 290 | #define HPIPE_CFG_CURSOR_PRESET2_OFFSET 0 |
| 291 | #define HPIPE_CFG_CURSOR_PRESET2_MASK \ |
| 292 | (0x3f << HPIPE_CFG_CURSOR_PRESET2_OFFSET) |
| 293 | #define HPIPE_CFG_CURSOR_PRESET3_OFFSET 6 |
| 294 | #define HPIPE_CFG_CURSOR_PRESET3_MASK \ |
| 295 | (0x3f << HPIPE_CFG_CURSOR_PRESET3_OFFSET) |
| 296 | |
| 297 | #define HPIPE_LANE_PRESET_CFG2_REG 0x6b0 |
| 298 | #define HPIPE_CFG_CURSOR_PRESET4_OFFSET 0 |
| 299 | #define HPIPE_CFG_CURSOR_PRESET4_MASK \ |
| 300 | (0x3f << HPIPE_CFG_CURSOR_PRESET4_OFFSET) |
| 301 | #define HPIPE_CFG_CURSOR_PRESET5_OFFSET 6 |
| 302 | #define HPIPE_CFG_CURSOR_PRESET5_MASK \ |
| 303 | (0x3f << HPIPE_CFG_CURSOR_PRESET5_OFFSET) |
| 304 | |
| 305 | #define HPIPE_LANE_PRESET_CFG3_REG 0x6b4 |
| 306 | #define HPIPE_CFG_CURSOR_PRESET6_OFFSET 0 |
| 307 | #define HPIPE_CFG_CURSOR_PRESET6_MASK \ |
| 308 | (0x3f << HPIPE_CFG_CURSOR_PRESET6_OFFSET) |
| 309 | #define HPIPE_CFG_CURSOR_PRESET7_OFFSET 6 |
| 310 | #define HPIPE_CFG_CURSOR_PRESET7_MASK \ |
| 311 | (0x3f << HPIPE_CFG_CURSOR_PRESET7_OFFSET) |
| 312 | |
| 313 | #define HPIPE_LANE_PRESET_CFG4_REG 0x6b8 |
| 314 | #define HPIPE_CFG_CURSOR_PRESET8_OFFSET 0 |
| 315 | #define HPIPE_CFG_CURSOR_PRESET8_MASK \ |
| 316 | (0x3f << HPIPE_CFG_CURSOR_PRESET8_OFFSET) |
| 317 | #define HPIPE_CFG_CURSOR_PRESET9_OFFSET 6 |
| 318 | #define HPIPE_CFG_CURSOR_PRESET9_MASK \ |
| 319 | (0x3f << HPIPE_CFG_CURSOR_PRESET9_OFFSET) |
| 320 | |
| 321 | #define HPIPE_LANE_PRESET_CFG5_REG 0x6bc |
| 322 | #define HPIPE_CFG_CURSOR_PRESET10_OFFSET 0 |
| 323 | #define HPIPE_CFG_CURSOR_PRESET10_MASK \ |
| 324 | (0x3f << HPIPE_CFG_CURSOR_PRESET10_OFFSET) |
| 325 | #define HPIPE_CFG_CURSOR_PRESET11_OFFSET 6 |
| 326 | #define HPIPE_CFG_CURSOR_PRESET11_MASK \ |
| 327 | (0x3f << HPIPE_CFG_CURSOR_PRESET11_OFFSET) |
| 328 | |
| 329 | #define HPIPE_LANE_PRESET_CFG6_REG 0x6c0 |
| 330 | #define HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET 0 |
| 331 | #define HPIPE_CFG_PRE_CURSOR_PRESET0_MASK \ |
| 332 | (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET) |
| 333 | #define HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET 6 |
| 334 | #define HPIPE_CFG_POST_CURSOR_PRESET0_MASK \ |
| 335 | (0x3f << HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET) |
| 336 | |
| 337 | #define HPIPE_LANE_PRESET_CFG7_REG 0x6c4 |
| 338 | #define HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET 0 |
| 339 | #define HPIPE_CFG_PRE_CURSOR_PRESET1_MASK \ |
| 340 | (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET) |
| 341 | #define HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET 6 |
| 342 | #define HPIPE_CFG_POST_CURSOR_PRESET1_MASK \ |
| 343 | (0x3f << HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET) |
| 344 | |
| 345 | #define HPIPE_LANE_PRESET_CFG8_REG 0x6c8 |
| 346 | #define HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET 0 |
| 347 | #define HPIPE_CFG_PRE_CURSOR_PRESET2_MASK \ |
| 348 | (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET) |
| 349 | #define HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET 6 |
| 350 | #define HPIPE_CFG_POST_CURSOR_PRESET2_MASK \ |
| 351 | (0x3f << HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET) |
| 352 | |
| 353 | #define HPIPE_LANE_PRESET_CFG9_REG 0x6cc |
| 354 | #define HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET 0 |
| 355 | #define HPIPE_CFG_PRE_CURSOR_PRESET3_MASK \ |
| 356 | (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET) |
| 357 | #define HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET 6 |
| 358 | #define HPIPE_CFG_POST_CURSOR_PRESET3_MASK \ |
| 359 | (0x3f << HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET) |
| 360 | |
| 361 | #define HPIPE_LANE_PRESET_CFG10_REG 0x6d0 |
| 362 | #define HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET 0 |
| 363 | #define HPIPE_CFG_PRE_CURSOR_PRESET4_MASK \ |
| 364 | (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET) |
| 365 | #define HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET 6 |
| 366 | #define HPIPE_CFG_POST_CURSOR_PRESET4_MASK \ |
| 367 | (0x3f << HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET) |
| 368 | |
| 369 | #define HPIPE_LANE_PRESET_CFG11_REG 0x6d4 |
| 370 | #define HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET 0 |
| 371 | #define HPIPE_CFG_PRE_CURSOR_PRESET5_MASK \ |
| 372 | (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET) |
| 373 | #define HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET 6 |
| 374 | #define HPIPE_CFG_POST_CURSOR_PRESET5_MASK \ |
| 375 | (0x3f << HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET) |
| 376 | |
| 377 | #define HPIPE_LANE_PRESET_CFG12_REG 0x6d8 |
| 378 | #define HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET 0 |
| 379 | #define HPIPE_CFG_PRE_CURSOR_PRESET6_MASK \ |
| 380 | (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET) |
| 381 | #define HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET 6 |
| 382 | #define HPIPE_CFG_POST_CURSOR_PRESET6_MASK \ |
| 383 | (0x3f << HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET) |
| 384 | |
| 385 | #define HPIPE_LANE_PRESET_CFG13_REG 0x6dc |
| 386 | #define HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET 0 |
| 387 | #define HPIPE_CFG_PRE_CURSOR_PRESET7_MASK \ |
| 388 | (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET) |
| 389 | #define HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET 6 |
| 390 | #define HPIPE_CFG_POST_CURSOR_PRESET7_MASK \ |
| 391 | (0x3f << HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET) |
| 392 | |
| 393 | #define HPIPE_LANE_PRESET_CFG14_REG 0x6e0 |
| 394 | #define HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET 0 |
| 395 | #define HPIPE_CFG_PRE_CURSOR_PRESET8_MASK \ |
| 396 | (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET) |
| 397 | #define HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET 6 |
| 398 | #define HPIPE_CFG_POST_CURSOR_PRESET8_MASK \ |
| 399 | (0x3f << HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET) |
| 400 | |
| 401 | #define HPIPE_LANE_PRESET_CFG15_REG 0x6e4 |
| 402 | #define HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET 0 |
| 403 | #define HPIPE_CFG_PRE_CURSOR_PRESET9_MASK \ |
| 404 | (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET) |
| 405 | #define HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET 6 |
| 406 | #define HPIPE_CFG_POST_CURSOR_PRESET9_MASK \ |
| 407 | (0x3f << HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET) |
| 408 | |
| 409 | #define HPIPE_LANE_PRESET_CFG16_REG 0x6e8 |
| 410 | #define HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET 0 |
| 411 | #define HPIPE_CFG_PRE_CURSOR_PRESET10_MASK \ |
| 412 | (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET) |
| 413 | #define HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET 6 |
| 414 | #define HPIPE_CFG_POST_CURSOR_PRESET10_MASK \ |
| 415 | (0x3f << HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET) |
| 416 | |
| 417 | #define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 |
| 418 | #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 |
| 419 | #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \ |
| 420 | (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) |
| 421 | #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 |
| 422 | #define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \ |
| 423 | (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) |
| 424 | #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 |
| 425 | #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \ |
| 426 | (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) |
| 427 | |
| 428 | #define HPIPE_RST_CLK_CTRL_REG 0x704 |
| 429 | #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 |
| 430 | #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ |
| 431 | (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) |
| 432 | #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 |
| 433 | #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ |
| 434 | (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) |
| 435 | #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 |
| 436 | #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ |
| 437 | (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) |
| 438 | #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 |
| 439 | #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ |
| 440 | (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) |
| 441 | |
| 442 | #define HPIPE_CLK_SRC_LO_REG 0x70c |
| 443 | #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 |
| 444 | #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ |
| 445 | (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) |
| 446 | #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 |
| 447 | #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ |
| 448 | (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) |
| 449 | #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 |
| 450 | #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ |
| 451 | (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) |
| 452 | |
| 453 | #define HPIPE_CLK_SRC_HI_REG 0x710 |
| 454 | #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 |
| 455 | #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ |
| 456 | (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) |
| 457 | #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 |
| 458 | #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ |
| 459 | (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) |
| 460 | #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 |
| 461 | #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ |
| 462 | (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) |
| 463 | #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 |
| 464 | #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ |
| 465 | (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) |
| 466 | |
| 467 | #define HPIPE_GLOBAL_PM_CTRL 0x740 |
| 468 | #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 |
| 469 | #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ |
| 470 | (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) |
| 471 | |
Antonio Nino Diaz | c3cf06f | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 472 | #endif /* COMPHY_H */ |