Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1 | ARM CPU Specific Build Macros |
| 2 | ============================= |
| 3 | |
| 4 | |
| 5 | .. section-numbering:: |
| 6 | :suffix: . |
| 7 | |
| 8 | .. contents:: |
| 9 | |
| 10 | This document describes the various build options present in the CPU specific |
| 11 | operations framework to enable errata workarounds and to enable optimizations |
| 12 | for a specific CPU on a platform. |
| 13 | |
| 14 | CPU Errata Workarounds |
| 15 | ---------------------- |
| 16 | |
| 17 | ARM Trusted Firmware exports a series of build flags which control the |
| 18 | errata workarounds that are applied to each CPU by the reset handler. The |
| 19 | errata details can be found in the CPU specific errata documents published |
| 20 | by ARM: |
| 21 | |
| 22 | - `Cortex-A53 MPCore Software Developers Errata Notice`_ |
| 23 | - `Cortex-A57 MPCore Software Developers Errata Notice`_ |
| 24 | |
| 25 | The errata workarounds are implemented for a particular revision or a set of |
| 26 | processor revisions. This is checked by the reset handler at runtime. Each |
| 27 | errata workaround is identified by its ``ID`` as specified in the processor's |
| 28 | errata notice document. The format of the define used to enable/disable the |
| 29 | errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` |
| 30 | is for example ``A57`` for the ``Cortex_A57`` CPU. |
| 31 | |
| 32 | Refer to the section *CPU errata status reporting* in |
| 33 | `Firmware Design guide`_ for information on to write errata workaround functions. |
| 34 | |
| 35 | All workarounds are disabled by default. The platform is responsible for |
| 36 | enabling these workarounds according to its requirement by defining the |
| 37 | errata workaround build flags in the platform specific makefile. In case |
| 38 | these workarounds are enabled for the wrong CPU revision then the errata |
| 39 | workaround is not applied. In the DEBUG build, this is indicated by |
| 40 | printing a warning to the crash console. |
| 41 | |
| 42 | In the current implementation, a platform which has more than 1 variant |
| 43 | with different revisions of a processor has no runtime mechanism available |
| 44 | for it to specify which errata workarounds should be enabled or not. |
| 45 | |
| 46 | The value of the build flags are 0 by default, that is, disabled. Any other |
| 47 | value will enable it. |
| 48 | |
| 49 | For Cortex-A53, following errata build flags are defined : |
| 50 | |
| 51 | - ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 |
| 52 | CPU. This needs to be enabled only for revision <= r0p2 of the CPU. |
| 53 | |
Douglas Raillard | ca6b1cb | 2017-07-17 14:14:52 +0100 | [diff] [blame] | 54 | - ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and |
| 55 | link time to Cortex-A53 CPU. This needs to be enabled for some variants of |
| 56 | revision <= r0p4. This workaround can lead the linker to create ``*.stub`` |
| 57 | sections. |
| 58 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 59 | - ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 |
| 60 | CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From |
| 61 | r0p4 and onwards, this errata is enabled by default in hardware. |
| 62 | |
Douglas Raillard | ca6b1cb | 2017-07-17 14:14:52 +0100 | [diff] [blame] | 63 | - ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time |
| 64 | to Cortex-A53 CPU. This needs to be enabled for some variants of revision |
| 65 | <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections |
| 66 | which are 4kB aligned. |
| 67 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 68 | - ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 |
| 69 | CPUs. Though the erratum is present in every revision of the CPU, |
| 70 | this workaround is only applied to CPUs from r0p3 onwards, which feature |
| 71 | a chicken bit in CPUACTLR\_EL1 to enable a hardware workaround. |
| 72 | Earlier revisions of the CPU have other errata which require the same |
| 73 | workaround in software, so they should be covered anyway. |
| 74 | |
| 75 | For Cortex-A57, following errata build flags are defined : |
| 76 | |
| 77 | - ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 |
| 78 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 79 | |
| 80 | - ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 |
| 81 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 82 | |
| 83 | - ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 |
| 84 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 85 | |
| 86 | - ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 |
| 87 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 88 | |
| 89 | - ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 |
| 90 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 91 | |
| 92 | - ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 |
| 93 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 94 | |
| 95 | - ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 |
| 96 | CPU. This needs to be enabled only for revision <= r1p2 of the CPU. |
| 97 | |
| 98 | - ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 |
| 99 | CPU. This needs to be enabled only for revision <= r1p2 of the CPU. |
| 100 | |
| 101 | CPU Specific optimizations |
| 102 | -------------------------- |
| 103 | |
| 104 | This section describes some of the optimizations allowed by the CPU micro |
| 105 | architecture that can be enabled by the platform as desired. |
| 106 | |
| 107 | - ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the |
| 108 | Cortex-A57 cluster power down sequence by not flushing the Level 1 data |
| 109 | cache. The L1 data cache and the L2 unified cache are inclusive. A flush |
| 110 | of the L2 by set/way flushes any dirty lines from the L1 as well. This |
| 111 | is a known safe deviation from the Cortex-A57 TRM defined power down |
| 112 | sequence. Each Cortex-A57 based platform must make its own decision on |
| 113 | whether to use the optimization. |
| 114 | |
| 115 | - ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal |
| 116 | hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave |
| 117 | in a way most programmers expect, and will most probably result in a |
| 118 | significant speed degradation to any code that employs them. The ARMv8-A |
| 119 | architecture (see ARM DDI 0487A.h, section D3.4.3) allows cores to ignore |
| 120 | the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this |
| 121 | flag enforces this behaviour. This needs to be enabled only for revisions |
| 122 | <= r0p3 of the CPU and is enabled by default. |
| 123 | |
| 124 | - ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as |
| 125 | ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be |
| 126 | enabled only for revisions <= r1p2 of the CPU and is enabled by default, |
| 127 | as recommended in section "4.7 Non-Temporal Loads/Stores" of the |
| 128 | `Cortex-A57 Software Optimization Guide`_. |
| 129 | |
| 130 | -------------- |
| 131 | |
| 132 | *Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.* |
| 133 | |
| 134 | .. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html |
| 135 | .. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf |
| 136 | .. _Firmware Design guide: firmware-design.rst |
| 137 | .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf |